summaryrefslogtreecommitdiffstats
path: root/drivers
Commit message (Collapse)AuthorAge
* gpu: nvgpu: Record size of page table levelTerje Bergstrom2015-05-05
| | | | | | | | | | | | | | Record size of each page table level. The size of level 0 depends on size of the address space, and we generally do not support the whole address space. Change-Id: Iab47505af1a641e193d9e98a2246e522813f221a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/729730 Reviewed-by: Automatic_Commit_Validation_User Reviewed-on: http://git-master/r/737531 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: Use common allocator for patchTerje Bergstrom2015-05-05
| | | | | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: Idf51831e8be9cabe1ab9122b18317137fde6339f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/721030 Reviewed-on: http://git-master/r/737530 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: Align VA of compressible bufferTerje Bergstrom2015-05-05
| | | | | | | | | | | | | | | Ensure that the GPU VA for a buffer is aligned correctly if compression is enabled. Bug 1605769 Change-Id: I12566ddd554da7cc9fb41dd553576c534ac96ba8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725767 Reviewed-on: http://git-master/r/737529 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Free all page table levelsTerje Bergstrom2015-05-05
| | | | | | | | | | | | | Convert the loop to free page tables into a recursive loop that goes through all levels. Change-Id: I3ab8f021bd8263f2f6dad29b5fbd0e6212c55a86 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/711393 Reviewed-on: http://git-master/r/737528 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Do not send WFI when finishing channelTerje Bergstrom2015-05-05
| | | | | | | | | | | | | | | | | The channel teardown process sends a WFI method to ensure that all work has been completed. But we also preempt the channel a while later, which also ensures that all work is completed. Remove the code for submitting WFI, and rely on preemption to handle idling the pipe. Change-Id: I2af029184440ee73e70d377f15690ddaf9b8599f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/735067 Reviewed-on: http://git-master/r/737527 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Reconfigure instance block with syncptTerje Bergstrom2015-05-05
| | | | | | | | | | | | Resetup RAMFC once sync point id is allocated for a channel. Change-Id: Idbac406bea1c94c89ef587dda08fddc740c1fadb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/711302 Reviewed-on: http://git-master/r/737526 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* platform: tegra: mc: Centralize header filesAlex Waterman2015-05-05
| | | | | | | | | | | | | | | Place all header files under linux/platform/tegra/. Also update all source files that include the moved headers to correctly reflect their new location. Change-Id: Iff5738d3ad75e93519d1a4b573b80d03e6a9b053 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/728636 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/733651 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: made gm20b_pmu_init_acr() global.Mahantesh Kumbar2015-04-27
| | | | | | | | | | | | | | | | | | -made gm20b_pmu_init_acr() method to global to access in pmu-T18x. Bug 200085428 Change-Id: Ic262997d5c6f97cecf12d17d9a64a9d1cd20c83b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/732210 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/735727 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* HACK: Disable genpd_pm_subdomain_attachDan Willemsen2015-04-04
| | | | | | Upstream doesn't keep track of the DT node in the genpd struct anymore. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
* gpu: nvgpu: Sem wakeup to post eventTerje Bergstrom2015-04-04
| | | | | | | | Add posting a channel event whenever we do a wakeup due to semaphore. Change-Id: Id1765123de93bcbc0822af7926d7f4e9919ffe10 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/726420
* gpu: nvgpu: Check alignment of fixed allocsTerje Bergstrom2015-04-04
| | | | | | | | | | | | When mapping buffer on a fixed address, ensure that the alignment of buffer and the address are compabile. When freeing, retrieve page size from the VA instead of choosing it again. Bug 1605769 Change-Id: I4f73453996cd53a912b6a414caa41563cde28da7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725764
* Revert "gpu: nvgpu: zbc: disable activity only ...Sam Payne2015-04-04
| | | | | | | | | | | | This reverts commit 83bc90620f863977101a164780de360bcd0aa088. bug 1628118 Change-Id: I478f9dd3685b55b4fce18354d475ee0b817a7775 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/727152 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Per-SoC compressible page sizeTerje Bergstrom2015-04-04
| | | | | | | | | | | | Define smallest compressible page size per SoC, and use that for determining if a compressible kind should be downgraded to uncompressed. Bug 1605769 Change-Id: I7c9991ba0ae82fe533641f045e506c0b01a10d8b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/724492
* gpu: nvgpu: Use common VM deinitTerje Bergstrom2015-04-04
| | | | | | Change-Id: Ia9aa9cfaaad9e43820fc47f6620bf01c435dad23 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/718726
* gpu: nvgpu: Allow sparse buffers on small pagesTerje Bergstrom2015-04-04
| | | | | | | | | | | Sparse buffers were allowed only with big pages. That restriction is not necessary, so remove it. Bug 1605769 Change-Id: I92efc0efe80edccead47b47d33fd9a75c921ca9a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725763
* gpu: nvgpu: Use common allocator for contextTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I10c226e2377aa867a5cf11be61d08a9d67206b1d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720507
* gpu: nvgpu: don't idle if busy fail in set zbc tblKonsta Holtta2015-04-04
| | | | | | | | | | Move gk20a_idle() under error check in NVGPU_GPU_IOCTL_ZBC_SET_TABLE so that if gk20a_busy fails, the idle is skipped properly. Change-Id: Iffde3734f7fb121e1bc7838a67bfee3dacfd0a46 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/726104 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add priv ring error spewTerje Bergstrom2015-04-04
| | | | | | | | Spew debug lines in case we get a priv ring error. Change-Id: Iba46813a355b5d2d192614a9e146397688e130a7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660850
* gpu: nvgpu: Regenerate HW headersTerje Bergstrom2015-04-04
| | | | | | | | Added fuse for FBP and DS exception register. Change-Id: Ie38a84eac40ca2d8cf3ac8f19ed6bad0d6bc1dd9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/722846
* gpu: nvgpu: Fix the GPFIFO submit conditionGagan Grover2015-04-04
| | | | | | | | | | | | | | | | GPFIFO HW with fifo size N can actually accept N-1 entries. Also, kernel can insert two extra entries, before and after the user GPFIFOs. So, GPFIFO with N size can accept max N-3 user gpfifos. Bug 1613125 Change-Id: I173526afb70dddf1b2b9ec0a99890335c81f0e02 Signed-off-by: Gagan Grover <ggrover@nvidia.com> Reviewed-on: http://git-master/r/725380 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix invalid "reset initiated" printsDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | | | Improve the error path and return values from function gk20a_fifo_handle_sched_error() - return true, when we trigger the recovery in this function - otherwise, return false No need to reset the scheduler error register in this function, since we anyway clear the interrupt in fifo_error_isr() Also, fix the typo "reset initated" -> "reset initiated" Bug 200089043 Change-Id: Ibfc2fd2133982a268699d08682bcd6f044a3196a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/722711 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use sg_alloc_table_for_pagesTerje Bergstrom2015-04-04
| | | | | | | | | | | | | Use sg_alloc_table_for_pages to create sg_table for buffers allocated with NO_KERNEL_MAPPING. The old code returned always an sg_table with one chunk. sg_alloc_table_for_pages returns an sg_table which describes the actual physical chunks of the buffer. Bug 1605769 Change-Id: I412c0151d830fa0f53dbbb08ba8cc9ebce6699e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/723696
* gpu: nvgpu: Fix error paths in init vmTerje Bergstrom2015-04-04
| | | | | | | | Error paths called the wrong cleanup sections. Change-Id: I603af77bf8e3981c029bcf6d582882e51847f137 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/722949
* gpu: nvgpu: Increase GPFIFO priv cmd queue sizeTerje Bergstrom2015-04-04
| | | | | | | | | We're doing two sync point increments, so we need to allocate space for it. Change-Id: I663abb18a930eb3955379d5f8dd1b08c8fa56897 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719884
* gpu: nvgpu: fix sparse tool warningsSandarbh Jain2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: -drivers/gpu/nvgpu/gk20a/gr_gk20a.c:6028:6: warning: symbol 'gr_gk20a_init_sm_dsm_reg_info' was not declared. Should it be static? -gr_gk20a.c:6174:6: warning: symbol 'gr_gk20a_get_sm_dsm_perf_regs' was not declared. Should it be static? -gr_gk20a.c:6184:6: warning: symbol 'gr_gk20a_get_sm_dsm_perf_ctrl_regs' was not declared. Should it be static? -gr_gm20b.c:465:6: warning: symbol 'gr_gm20b_init_sm_dsm_reg_info' was not declared. Should it be static? -gr_gm20b.c:476:6: warning: symbol 'gr_gm20b_get_sm_dsm_perf_regs' was not declared. Should it be static? -gr_gm20b.c:486:6: warning: symbol 'gr_gm20b_get_sm_dsm_perf_ctrl_regs' was not declared. Should it be static? Bug 200067946 Change-Id: Ic14080e94e343386f4fef379152a623c402984fd Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/723518 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Fix offset of PC sampling fieldTerje Bergstrom2015-04-04
| | | | | | | | | | | Fix offset of PM word when changing PC sampling field. Bug 1517458 Bug 1573150 Change-Id: I2b8489b1d3c05f3a20416fc1a46ac1827f453cbc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/721032
* gpu: nvgpu: add platform specific get_iova_addr()Deepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | Add platform specific API pointer (*get_iova_addr)() which can be used to get iova/physical address from given scatterlist and flags Use this API with g->ops.mm.get_iova_addr() instead of calling API gk20a_mm_iova_addr() which makes it platform specific Bug 1605653 Change-Id: I798763db1501bd0b16e84daab68f6093a83caac2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713089 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: improve error print in check_gp_put()Deepak Nibade2015-04-04
| | | | | | | | | | | | | | Improve error print in check_gp_put() and dump put pointer stored in channel's gpfifo structure and the put pointer that we read from memory Bug 200089835 Change-Id: I7e854398811330a43d9d9bf86bf29c5986ab22b7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/722536 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix comptag index in traceTerje Bergstrom2015-04-04
| | | | | | | | | Instead of comptag index we were dumping an offset in buffer. Change-Id: Iaa07919c8d87009227556eacbcb6dcbd83954c7d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/718597 Reviewed-by: Automatic_Commit_Validation_User
* tegra: gpu: disable touch boost for gpuSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | Gpu boosting with input events is causing more gpu power consumption than required. To avoid this, touch boot for gpu is disabled by not registering gpu device for cfboost frame work. Current rail gate entry/exit latencies are fast enough to give smooth user experience. Bug 200087243 Change-Id: I18673d9c95a44ce9bee87e860b4edb29212dc766 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/721989 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use common allocator for compbit storeTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I7c1662b669ed8c86465254f6001e536141051ee5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720435
* gpu: nvgpu: Helper for no kernel mapping allocTerje Bergstrom2015-04-04
| | | | | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by introducing a variant of allocation helper that does not map the allocated buffer to kernel address space. NO_KERNEL_MAPPING allocations return a struct page **, so store the results of allocation in a new field of mem_desc. Bug 1605769 Change-Id: Ib760b9e6d34b229b04d1fb4f3abf10648670fc69 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/721029
* gpu: nvgpu: Use common allocator for GPFIFOTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I81701427ae29b298039a77f1634af9c14237812e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719872
* gpu: nvgpu: Use common allocator for cmd queueTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: If93063acbbfaa92aef530208241988427b5df8eb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719871
* gpu: nvgpu: Skip debug dump on stuck syncpointTerje Bergstrom2015-04-04
| | | | | | | | Skip dumping full debug spew on stuck syncpoint. Change-Id: I22c019bac23c4530229e20c0f8ce00806e23d9a1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719876
* gpu: nvgpu: Catch DS exceptionTerje Bergstrom2015-04-04
| | | | | | | | Catch DS exception and write an error to UART. Change-Id: Iaad9813c48191f0d3d734d4af264b976a3818672 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/679142
* gpu: nvgpu: GM20B extended buffer definitionSandarbh Jain2015-04-04
| | | | | | | | | | | | | | | | Update extended buffer definition for Maxwell. On GM20B only PERF_CONTROL0 and PERF_CONTROL5 registers are restored in extended buffer. They are needed for stopping the counters as late as possible during ctx save and start them as early as possible during context restore. On Maxwell, these registers contain the enable/disable bit. Bug 200086767 Change-Id: I59125a2f04bd0975be8a1ccecf993c9370f20337 Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/717421 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Set default timeout to 5sTerje Bergstrom2015-04-04
| | | | | | | | | | 10s is a too long timeout. Set it to 5s. Change-Id: I7093a8ee5bb27828f27cd06a5b3899a4f2df6280 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717042 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: tegra gpu to emc frequency mappingAnders Kugler2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | o emc clock scaling Only take the gpu load into account for gpu frequencies below fmax @ Vmin. The granularity of frequency steps is much larger in the gpu frequency range below fmax @ Vmin than in the upper frequency range. Above fmax @ Vmin, keep the gpu unblocked and disregard the gpu load when evaluating the emc target. o tegra_postscale() Round the new emc target to nearest discrete frequency. Set the emc frequency only if the new emc target is different from the previously requested emc frequency to avoid the penalty of the locks inside clk_set_rate(). Bug 1591643 Change-Id: I1a1a8734a74569c4d57b6e2bda4c11b2bda3f5f3 Signed-off-by: Anders Kugler <akugler@nvidia.com> Reviewed-on: http://git-master/r/680937 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Infinite syncpt wait on presiliconTerje Bergstrom2015-04-04
| | | | | | | | | On presilicon, syncpt waits should have infinite timeout. Change-Id: Ifa9b2fa0ef164e2f87a631bca77941e995b06ad4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717947 Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
* gpu: nvgpu: Cache channel state before dumpingTerje Bergstrom2015-04-04
| | | | | | | | | | | Split channel debug dump into two phases. In first phase we just copy the data to a temporary buffer, and in second phase we dump the state from the temporary buffer. Change-Id: I2578b9fdaaa76f1230df7badbca9fcb5f3854e56 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717886 Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Use gk20a_mem_phys instead of sg_physTerje Bergstrom2015-04-04
| | | | | | | | | There were still a couple of places using sg_phys directly. Use new gk20a_mem_phys() to make the code shorter. Change-Id: I6eb9b14e0c14a27ec39bacd06ab24e31e99769ca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717502
* gpu: nvgpu: Do not touch gr status maskTerje Bergstrom2015-04-04
| | | | | | | | | GR status disable mask was never set, so driver always disabled all engines from status rollup. Change-Id: I500a127be9253294f73d1f42ce89b886471a9117 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719141
* gpu: nvgpu: zbc: disable activity only from ioctlKonsta Holtta2015-04-04
| | | | | | | | | | | | | | Move the fifo engine activity disabling and wait-for-idle from the lowest-level functions higher, into the ioctl path of zbc operations, so that the sw initialization path wouldn't call them. During the init path, the disable isn't necessary, and the code path could result in a deadlock in the fifo runlist mutex. Change-Id: Ia3d768b7ad2d829416a1144486e6788d3177eb04 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715195 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make the local function staticAmit Sharma (SW-TEGRA)2015-04-04
| | | | | | | | | | | | | | | | | | | Fixed the following sparse warnings by making below APIs static: - gk20a.c: warning: symbol 'gk20a_pm_restore_debug_setting' was not declared. Should it be static? - gr_gk20a.c: warning: symbol 'gr_gk20a_rop_l2_en_mask' was not declared. Should it be static? - gr_gm20b.c: warning: symbol 'gr_gm20b_rop_l2_en_mask' was not declared. Should it be static? Bug 200067946 Change-Id: I334893bb6614171bff835d270716a7dd262c9ba7 Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/718756 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: use vmalloc for temp gpfifo in submitKonsta Holtta2015-04-04
| | | | | | | | | | | | | | | Use vmalloc instead of kzalloc for the temporary gpfifo buffer copied from userspace in the ioctl when submitting gpfifos. The data may be too big for kzalloc, and it doesn't need to be physically contiguous. Bug 1617747 Bug 200081843 Change-Id: I66a43d17eb13a2783bc1f0598a38abbf330b2ba6 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715207 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: 3d.emc frequency scalingAnders Kugler2015-04-04
| | | | | | | | | | | | | | | | | | | | o QoS notifier Refresh the gpu load query because we may update the emc target if gpu load changed. o tegra_postscale() Scaling the emc clock to a new target may be necessary if the gpu load changed at low gpu frequencies. Bug 1591643 Change-Id: Ibc6f73c02eaf6cedb7f0f579d5f4d90c735d354a Signed-off-by: Anders Kugler <akugler@nvidia.com> Reviewed-on: http://git-master/r/680929 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: vgpu: add new attributesAingara Paramakuru2015-04-04
| | | | | | | | | | | | Add support for reading num FBPs and FBP enable mask. Bug 1621056 Change-Id: I92ec1123373308ed280d4ffd30fe77ae6073ac45 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/715826 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reduce gr delaysSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | The delay value used in gr usleep_range calls is too high. We can start at a much lower value. Change-Id: Id141df70b8892bc1ed1b49623c4aa125d541a636 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/715928 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: print also fifo_intr in reset logKonsta Holtta2015-04-04
| | | | | | | | | | | | Print the interrupt code for diagnostics when logging the message about channel reset in fifo_error_isr. Change-Id: I44e9eb818af7264671f1c804d9a77b14c197457d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715804 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:09:21 -0500