summaryrefslogtreecommitdiffstats
path: root/drivers
Commit message (Collapse)AuthorAge
* gpu: nvgpu: Convert logging from dev_*() to nvgpu_*()Terje Bergstrom2017-06-30
| | | | | | | | | | | | Convert a few calls from dev_*() logging to nvgpu_*(). This reduces dependency to Linux specific struct device pointer. JIRA NVGPU-38 Change-Id: Ib51a6b1287db25b7dd4d164aec3ac75fa2801ebf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507929 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Per chip default big page sizeTerje Bergstrom2017-06-30
| | | | | | | | | | | | | | Make default big page size query a HAL op instead of per-platform constant. This allows querying for default big page size without accessing Linux specific gk20a_platform structure. JIRA NVGPU-38 Change-Id: Ibfbd1319764fdae5fdb06700fb64d23f6f3dd01a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507928 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove gk20a supportTerje Bergstrom2017-06-30
| | | | | | | | | | | | Remove gk20a support. Leave only gk20a code which is reused by other GPUs. JIRA NVGPU-38 Change-Id: I3d5f2bc9f71cd9f161e64436561a5eadd5786a3b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507927 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: rename pmu_mclk_gp106 to mclk_gp106Thomas Fleury2017-06-30
| | | | | | | | | | | | | | | Rename files, as they are not directly related to PMU. They just send commands to PMU, similar to all other clock change codes. Bug 1921094 Change-Id: I4a67d4c950d995c68cfce464108cd36104f44080 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master/r/1508820 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move mclk_init to pstate_pmu_supportThomas Fleury2017-06-30
| | | | | | | | | | | | | | | Preparation for all clock changes should happen in P-state module Bug 1921094 Change-Id: I3bfa7d52eee5b40a41d80b362e064665081694a3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master/r/1508819 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move mclk related functions to clkThomas Fleury2017-06-30
| | | | | | | | | | | | | | Move mclk related functions be moved to clk structure instead of pmu. We want to keep pmu only for basic pmu interaction and split clk, lpwr etc. Bug 1921094 Change-Id: I32394bc0e6d3657dfbd34dbcf19c9af56c12e194 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master/r/1506586 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mclk switching sequences for .58 OEM VBIOSThomas Fleury2017-06-30
| | | | | | | | | | | | | | | Add mclk switching sequences for VBIOS 8606580012. Bug 1921094 Change-Id: I0e5b0e967c467a40d498ea5c634302f208722922 Reviewed-on: http://git-master/r/1499550 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 3c60b8ded3764a700a9719ae6bf176dcec94a989) Reviewed-on: https://git-master/r/1506585 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: determine memory configuration in halThomas Fleury2017-06-30
| | | | | | | | | | | | | | | | | | | Remove mem_config_idx from platform data, and instead let HAL determine which memory configuration to use. For this purpose, HAL may use PCI device identifiers, VBIOS version and possibly RAMCFG strap register. Bug 1929155 Change-Id: I6633e9e0c79728c8e3740f3f956b53b3abfc667b Reviewed-on: http://git-master/r/1497812 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit b7141ff5441b7ea95f9826eb37ae869f408e1414) Reviewed-on: https://git-master/r/1506584 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: determine memory configuration in halThomas Fleury2017-06-30
| | | | | | | | | | | | | | | | | | | Remove mem_config_idx from platform data, and instead let HAL determine which memory configuration to use. For this purpose, HAL may use PCI device identifiers, VBIOS version and possibly RAMCFG strap register. Bug 1929155 Change-Id: I9fcd67ff407382839ff81470789043fae1c81283 Reviewed-on: http://git-master/r/1497813 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 3f722945213bacfc5f6707059b9baccebd92cef1) Reviewed-on: https://git-master/r/1506583 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add t19x supportRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | - add commit_inst hal ops - add t19x cmds to cmd big union - add t19x vgpu driver and call t19x hal init - get guest channel_base to calculate hw channel id Jira VFND-3796 Change-Id: Ic2431233fd174afc2c84c4794e20552e6e88b1dc Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1474715 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: fixes for no bar1 support caseRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | - add check of is_bar1_supported - move vgpu_init_fifo_setup_hw to hal - assume it's bar1 reg if no "reg-names" in dts Jira VFND-3796 Change-Id: I022a0ed98144bb8f1e7e55f24fcaf928b4a3fe32 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1474716 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add fifo_t19x and channel_baseRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | - add fifo_t19x to fifo_gk20a - add channel_base to fifo_gk20a It'll make kick off code re-usable by vgpu. Jira VFND-3796 Change-Id: I7f7607d3682f2eaad903e1690d83c1d78eba8052 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1510456 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename hw_chid to chidRichard Zhao2017-06-30
| | | | | | | | | | | | | hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1509530 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gr: rename write_preemption_ptrseshendra Gadagottu2017-06-29
| | | | | | | | | | | Change function name write_preemption_ptr to set_preemption_buffer_va to match with what exactly getting done in that function. Change-Id: Ia20c1df865dde01ab2878d3cf10281676ff5000e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1510972 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: post PMU_STATE_STARTED for pmu threadKonsta Holtta2017-06-29
| | | | | | | | | | | | | Make the PMU_STATE_STARTED state change visible to the thread so that the thread quits when it is no longer necessary. Bug 200317814 Change-Id: I2a2d664bd772b5bb19ec096e50c9992fcec9170e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1509968 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use correct log type print in ftraceKonsta Holtta2017-06-29
| | | | | | | | | | | | | Supply the log type argument as text from the table as the log format string specifies for trace_printk. Change-Id: I9e0f2dd8bffeeb0f8cbdba95d9969403d7161474 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1509334 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: depend on gk20a for all configsKonsta Holtta2017-06-29
| | | | | | | | | | | | | | | | Depend on the main GK20A config for all subitems so that they get grouped properly under the top level item in the menuconfig. Also remove an extraneous CONFIG_ to make the trace printk config visible in the menu when its deps are there. Change-Id: I03ee5b8dff9ad02342ab31d0faad9549e8352059 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1509333 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU reset reorgMahantesh Kumbar2017-06-29
| | | | | | | | | | | | | | | | | | | | | | | | - nvgpu_pmu_reset() as pmu reset for all chips & removed gk20a_pmu_reset() & gp106_pmu_reset() along with dependent code. - Created ops to do PMU engine reset & to know the engine reset status - Removed pmu.reset ops & replaced with nvgpu_flcn_reset(pmu->flcn) - Moved sec2 reset to sec2_gp106 from pmu_gp106 & cleaned PMU code part of sec2. JIRA NVGPU-99 Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: functions made non-staticSeema Khowala2017-06-29
| | | | | | | | | | | | | | gr_gp10b_handle_fecs_error and gr_gp10b_set_cilp_preempt_pending made non-static to be reused for t19x Bug 200289491 Change-Id: I8ef7ffab1209abc7f7d7d05cbbdf8ce4365613c5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1505954 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add GPU_LIT_SM_PRI_STRIDE litter defineSeema Khowala2017-06-29
| | | | | | | | | | | | | Required to support multiple SM JIRA GPUT19X-75 Change-Id: If4397f29bfc4f31da13187182f0ae3c7423d0432 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1490096 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: Support multiple SM for t19xSeema Khowala2017-06-29
| | | | | | | | | | | | | | | | | -Add sm input param for handle_sm_exception and pre_process_sm_exception for gr ops/functions. -Add functions to calculate gpc and tpc reg offsets. -Add function to find SMs which raised SM exception. JIRA GPUT19X-75 Change-Id: I257e7342ddabadb1556c9551c50a54d34b0f9d1e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1476108 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: add GPU_LIT_NUM_SM_PER_TPC litter valueSeema Khowala2017-06-29
| | | | | | | | | | | | | Required for multiple SM support in t19x JIRA GPUT19X-75 Change-Id: I14e19700849faf5180813e82179707a78eb977a5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1510358 GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Set default devfreq polling ratePeter Boonstoppel2017-06-29
| | | | | | | | | | | | | Sets default polling rate for GPU podgov governor to 25ms. Jira NVGPU-20 Change-Id: I994f3aab772b41c238f6755e0bd22ed3d4b27cf4 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: https://git-master/r/1473141 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove gk20a_scale_notify_busy/idle() hooksPeter Boonstoppel2017-06-29
| | | | | | | | | | | | | | | | Remove dependency for nvgpu to invoke devfreq govenor on every gk20a_busy/idle() call. This dependency was originally necessary to track GPU load (busy vs idle) in software. However, since we currently read the load GPU from HW/PMU there is no need to invoke the devfreq governor in this path. Instead it can use timer-based polling. Jira NVGPU-20 Change-Id: Id09f89a8a562ed49164a2e06dcbb901e4a46e7d5 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: https://git-master/r/1473140 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: perfbuffer supportPeter Daifuku2017-06-27
| | | | | | | | | | | | | | | | | Add vgpu support for ModeE perfbuffers - VM allocation is handled by the kernel, with final mapping handled by the RM server - Enabling/disabling the perfbuffer is handled by the RM server Bug 1880196 JIRA EVLR-1074 Change-Id: Ifbeb5ede6b07e2e112b930c602c22b66a58ac920 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master/r/1506747 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove fmodel GMMU allocationAlex Waterman2017-06-27
| | | | | | | | | | | | | | | | | Remove the special cases for fmodel in the GMMU allocation code. There is no reason to treat fmodel any different than regular DMA memory. If there is no IOMMU the DMA api will handle that perfectly acceptably. JIRA NVGPU-30 Change-Id: Icceb832735a98b601b9f41064dd73a6edee29002 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1507562 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorganize ltc HAL initializationSunny He2017-06-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ltc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1110e301e57b502cf7f97e6739424cb33cc52a69 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1507564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove ltc_common.cSunny He2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | Remove ltc_common.c and integrate the included functions into device specific ltc_gXXXX.c files. Merge non-device reg definition dependent ltc functions into ltc_gk20a.c/h. Prior to this patch, ltc_common.c was being directly included into the device specific ltc source files as a workaround to allow different devices to share the same code but still include in different hw reg definitions. Given that this approach was not adopted for other systems, this code has been separated out for readability and consistency. Jira NVGPU-74 Change-Id: I4eea301927418532cc150b029535f165928cab89 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1507502 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_copy_to_dmem()Mahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | - replace usage of pmu_copy_to_dmem() with nvgpu_flcn_copy_to_dmem() - delete nvgpu_flcn_copy_to_dmem() JIRA NVGPU-99 Change-Id: I9bb5837556e144521b181f9e15731beee08b435a Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506577 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon copy to DMEM supportMahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | | - Added falcon interface/HAL copy to DMEM method. JIRA NVGPU-99 Change-Id: I783f8046e96d9e47091afb943697256c289ebab6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506576 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_copy_from_dmem()Mahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | - replace usage of pmu_copy_from_dmem() with nvgpu_flcn_copy_from_dmem() - delete nvgpu_flcn_copy_from_dmem() JIRA NVGPU-99 Change-Id: If0919187078f95a165d6a152f180549ac121beaa Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon copy from DMEMMahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | | | | - Added interface/HAL method for falcon to support copy from dmem - Method to read dmem size - Method to check error on input parameters JIRA NVGPU-99 Change-Id: Id27b2b7f4f338196fc3b187555718543445d35bd Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506525 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move sysfs dependencies from HAL to LinuxTerje Bergstrom2017-06-27
| | | | | | | | | | | | | Move sysfs dependencies from gk20a/ and gp10b/ to common/linux. At the same time the gk20a and gp10b variants are merged into one. JIRA NVGPU-48 Change-Id: I212be8f1beb8d20a57de04a57513e8fa0e2e83b4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1466055 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Remove FECS override sysfs APITerje Bergstrom2017-06-27
| | | | | | | | | | | FECS override PMU support was removed with http://git-master/1297370. Remove the sysfs API that is wired to that. Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops for handling pbdma_intr_1Seema Khowala2017-06-27
| | | | | | | | | | | | This is needed to handle new pbmda intr_1 in t19x JIRA GPUT19X-47 Change-Id: If75de0b57f3f18420aff07ee99feaad67ac63752 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1329373 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: assume no syncpt support if no "nvidia,host1x" in dtRichard Zhao2017-06-24
| | | | | | | | | | | | | | | | | | It'll let gpu tests pass by using sem before enabling syncpt. Especially for vgpu, the plat data is shared across different GPUs, so we can use dt to override and disable syncpt. Jira VFND-3796 Change-Id: I2cc32a1ea1cc1097047427eb1e52ec50c3a0bf90 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1507494 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com>
* gpu: nvpgu: Use correct chipidSamuel Payne2017-06-23
| | | | | | | | | | | | | | | Add gm20b "B" revision chipip. Bug 1870669 Change-Id: Ife31e6d739aabb8ef4a4f401091c3202b415a70e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1490650 Reviewed-by: Samuel Payne <spayne@nvidia.com> Signed-off-by: Samuel Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/1490648 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_* interfacesMahantesh Kumbar2017-06-23
| | | | | | | | | | | | | | - set nvgpu_flcn_reset() to point to gk20a_pmu_reset() - set PMU interrupt using nvgpu_flcn_enable_irq() - replace pmu_idle with nvgpu_flcn_wait_idle() JIRA NVGPU-57 Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1469478 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon reset supportMahantesh Kumbar2017-06-23
| | | | | | | | | | | | | | | | | | | | | | | | | - Added flacon reset dependent interface & HAL methods to perform falcon reset. - method to wait for idle - method to reset falcon - method to set irq - method to read status of CPU - Updated falcon ops pointer to point gk20a falcon HAL methods - Added members to know support of falcon & interrupt. - Added falcon dependency ops member to support flacon speicifc methods JIRA NVGPU-99 JIRA NVGPU-101 Change-Id: I411477e5696a61ee73caebfdab625763b522c255 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1469453 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: hw header for Falcon controllerMahantesh Kumbar2017-06-23
| | | | | | | | | | | | | H/W header for gk20a, gm20b, gp10b & Gp106 falcon controller. JIRA NVGPU-56 Change-Id: Iec2066f83f499e86f5d28860ffaa6bdac0716c71 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1331258 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorder members of gpu_opsSunny He2017-06-22
| | | | | | | | | | | | | | Reorder non-function pointer members of gpu_ops to be at the very end of their respective sub-structs. This allows for easier debug interpretation and slightly improves readability. Jira NVGPU-107 Change-Id: Ife3279180306de70f7fad6760f616c6d69769b36 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: http://git-master/r/1506591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move devfreq field to os_linuxTerje Bergstrom2017-06-21
| | | | | | | | | | | | | Move devfreq field from struct gk20a to os_linux. It's a Linux specific framework. JIRA NVGPU-38 Change-Id: I1e00f5a80e31deb4aaba379274c3a7a7b04d963b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505176 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move dma_params to os_linuxTerje Bergstrom2017-06-21
| | | | | | | | | | | | dma_params is inherently a Linux structure, so move it to os_linux. JIRA NVGPU-38 Change-Id: If81249b3cb7d65187202df72b35a1d24e274263b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505928 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove Linux devnode fields from gk20aTerje Bergstrom2017-06-21
| | | | | | | | | | | | | | | Move Linux devnode related fields to a new header file os_linux.h. The class structure is defined in module.c, so move its declaration to module.h. JIRA NVGPU-38 Change-Id: I5d8920169064f4289ff61004f7f81543a9aba221 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505927 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove some #includes from gk20a.hTerje Bergstrom2017-06-21
| | | | | | | | | | | | | | | | | | | | | linux/version.h and linux/sched.h are not used by gk20a.h, so remove them. acr_gm20b.h and bus_gk20a.h are not needed by gk20a.h, so remove them. pmu_gp106.c relies on implicit #include of acr_gm20b.h by gk20a.h, so add that as an explicit #include. Remove #include of iomap.h. platform_gk20a_tegra.c legacy rail gating code still relies on access to that header, so add it as explicit include. JIRA NVGPU-38 Change-Id: I1cf57b9d3a7ee5e3cad298341107e317b4b8662f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check ctx valid bit at right placeSeema Khowala2017-06-21
| | | | | | | | | | | | | | | | When contexts are unloaded from GR, the valid bit is reset but the instance pointer information remains intact. Check valid bit in *is_channel_ctx_resident* function as valid bit might not be set when *get_channel_from_ctx function* is called from gr_isr Bug 200289491 Change-Id: I4da7f04794c7e7e80b511756dbd851205cd76fbc Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1505908 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: get ctx id from valid ctx memSeema Khowala2017-06-21
| | | | | | | | | | | | | | ctx id should be read from right mem area else it will return 0 and cause issue with fecs methods that depend on ctx id Bug 200289491 Change-Id: Iba74f653afccf34e95cd90175833e3270239c264 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1505902 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Enable debug printing on bootAlex Waterman2017-06-21
| | | | | | | | | | | | | Enable the log.h debug printing to print log messages on boot based on the NVGPU_DEFAULT_DBG_MASK define. Previously this only affected the legacy gk20a_dbg() function which is being slowly phased out. Change-Id: I74caed3bcdeec5481fb34e3151cfbc1acaabf233 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1505922 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: backward support for HW2.5 Rev.AThomas Fleury2017-06-21
| | | | | | | | | | | | | | | | | | | | Add backward support for HW2.5 Rev.A board: - no INA3221 for voltage, current, and power - use PG418 MCLK switching sequences Allow VBIOS from .53 for PG419 Bug 1929155 Change-Id: Ifacfc8cff6d00f66af92305119d0f0d3b9a1e438 Reviewed-on: http://git-master/r/1497001 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 952778f814916b0b3d5043c43755bfccb467c3d4) Reviewed-on: http://git-master/r/1497295 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: g106 hal for mclk switchingThomas Fleury2017-06-21
| | | | | | | | | | | | | move mclk switching to gp106 hal. Bug 1921082 JIRA EVLR-1269 Change-Id: I97812b871384460bec88fddac0f6a326df12fc45 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1499393 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 03:24:14 -0400