| Commit message (Collapse) | Author | Age |
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We initialized vidmem allocator with base=4K, and size of 4GB. This
caused allocator to allocate addresses between 4K and 4GB+4K, causing
a physical MMU fault.
Bug 1793810
Change-Id: I554f62aeee4080acd86ef2c8011089ec9b8120df
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1196300
(cherry picked from commit 41a860e21c6da3f8fda58ceb56e78316f6987f53)
Reviewed-on: http://git-master/r/1200712
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Device nodes for PCI devices need to be RW for everybody.
Bug 200225622
Change-Id: I14de9d17f76ca45ba525d0c4f5e8d448bbfda98b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1198556
(cherry picked from commit 60bf9118715b61b8cd3f2379479caf280ae4e35c)
Reviewed-on: http://git-master/r/1200713
Reviewed-by: Automatic_Commit_Validation_User
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Free the channel used semaphore index during gk20a_free_channel().
Bug 1793819
Change-Id: I4215d05f7f3ba0636e2abb1803011711c8a38301
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1196877
(cherry picked from commit 2c5720de506caac29629f6a1c578e6da80b1a135)
Reviewed-on: http://git-master/r/1198883
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We currently post bpt events (bpt.int and bpt.pause) even
before we process and clear the interrupts and this
could cause races with UMD
Fix this by posting bpt events only after we are done
processing the interrupts
Bug 200209410
Change-Id: Ic3ff7148189fccb796cb6175d6d22ac25a4097fb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1184109
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Initialize character array buf in gk20a_channel_ioctl() to zero
Keeping it uninitialized can result in leaking kernel stack
info to user space since we pass this buffer to UMD
Bug 1793398
Change-Id: Iffd654dbaca3b4e3c8fd2ac270d0febd01c165b8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1195862
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Disabling / enabling of PFIFO must stay inside the isr. It cannot be held
disabled outside the isr -- this causes any kind of preemption mechanism to
fail in the presence of an MMU fault until the channel resets the engine.
Bug 1791696
Change-Id: I16600a8571f6555262a75deb305c1d67eb29581a
Signed-off-by: Cory Perry <cperry@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1191026
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move dbg_session_ops to gops for better code consistency
JIRA VFND-1905
Change-Id: I04a11d77dd8c26d9922e80e556822f80dd2bc36d
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1192641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x
family gr class (PASCAL_B and PASCAL_COMPUTE_B).
Bug 200221149
Change-Id: I859a4d2db518bca0ffeb0d85a6bb271f6b15db87
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1193207
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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is_fmodel flag will be set in gk20a_probe().
Updated code for is_fmodel check, instead of
check for supported simulated platforms.
Bug 1735760
Change-Id: I7cbac2196130fe5ce4c1a910504879e6948c13da
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177869
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Added is_fmodel flag in gk20a platform data and
this flag is set to true for simulated gpu platforms.
Bug 1735760
Change-Id: Ib04579d2e2990ee051039bfb741d6e50523d44ac
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177868
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ayoosh Bansal <ayooshb@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Restores call to gk20a_scale_notify_busy() in
gk20a_busy(), which was unintentionally removed in
commit 6ac44d2813f5ab1873eb5148f26746a8f9dbd4a8
Bug 200187507
Change-Id: I96239d9e3e7cbd0911ebae358ec9dae39ec82566
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1191327
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 200220632
Change-Id: I75f628c54d68bbd06d5d8aeb32b8ee145411b8da
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1185067
(cherry picked from commit 0523a71eaac9dc7751f6e0e7d280b01f3a9e4ea3)
Reviewed-on: http://git-master/r/1189784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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Currently, host1x power refcount may decrement
to 0, while GPU is still powered on and we're still
servicing IRQs. So to prevent this situation,,
take a ref while GPU is being powered on, and
decrement it during power off. Since we are always
holding one reference while GPU is powered on,
we can remove this handling from gk20a_busy/idle()
Bug 200187507
Change-Id: I249a4527178537c1dc53d769411f53c4451352c3
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1172320
(cherry picked from commit 3e27e6a5820f5c1ad05596553d75e8979b71f1bd)
Reviewed-on: http://git-master/r/1172607
(cherry picked from commit 1e01a49fdc139b8cdf5164b4a6767d22ef4ad1d3)
Reviewed-on: http://git-master/r/1185175
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This CL covers the following simple modification,
1) Linux kernel list implementation doesn't handle NULL pointer dereference
at list_del() api.
2) NULL validation before access the command buffer related operations.
This required for prevent the illegal/NULL memory access during
gk20a_ce_create_context_with_cb() failure case.
JIRA DNVGPU-53
Change-Id: I3ad178970ecb1485098124378bfc5256a9455ebd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1184294
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Before calling prod settings functions, check for
availability of those functions.
Similar check is extended for get_clk_freqs.
Bug 1735760
Change-Id: Ic4b38079043ab2049a479a2d8bb0cb6091e94f4a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1181571
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Create sysfs nodes for gpu under host1x, only when
host1x device dependncy present.
For all gpus create syfs nodes under
generic gpu name "gpu.0"
Bug 1735760
Change-Id: I4b4a984139e0c33feadd95613c2f2076bc2db33b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1181068
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Bug 1783210
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Change-Id: Ie62dc86e6dc64c4dd939b54f806df557891fee9d
Reviewed-on: http://git-master/r/1175284
Reviewed-on: http://git-master/r/1177293
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/1183065
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Bug 1783210
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Change-Id: I08e3ffb6b59ab145588a5ecf81b6c2346a481628
Reviewed-on: http://git-master/r/1175267
Reviewed-on: http://git-master/r/1177292
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/1183064
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Include the buffer aperture flag (sysmem/vidmem/invalid) and the size of
the buffer and of the mapping in logging strings during gmmu map path.
Change-Id: Ie4c46bf9cb5db79b738571029d46ce8cbfc63f99
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1189492
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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nvgpu changes needed to handle the newly added ctxsw lists
Fix regops support for ppc registers
Squashed from:
Change-Id: I08e6dec3bb2f7aa51de912c9d1c84a350ce07f72
Signed-off-by: neha <njoshi@nvidia.com>
Reviewed-on: http://git-master/r/1151010
(cherry picked from commit fd03ad9f09e66f78db88fb7ece448e26e0515821)
and:
Change-Id: I75a7f810ee0b613c22ac2cef2d936563d8067f97
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1158888
(cherry picked from commit f00a7fcc57fb937b800e46760087ff6f7637520c)
Bug 200180000
Bug 1771830
Reviewed-on: http://git-master/r/1164397
(cherry picked from commit 7028f051e4f37edeff90a9923f022cec6c645a8f)
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Change-Id: I796ddf93ef37170843a4a6b44190cd6780d25852
Reviewed-on: http://git-master/r/1183588
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
GVS: Gerrit_Virtual_Submit
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When managing GVA spaces the buddy allocator requires PDE size
alignment. This is to ensure that PTE size in buddies always
remains consistent.
Consider the following hypothetical GVA space: it is 32 elements
long, order 0 block size is 1, and PDE size is 8. This leads to:
Base: 8
Size: 24
Managed space: [8, 32)
The start of the space will be 8 (base must be aligned to a PDE
and we need a hole at the bottom for handling errors). Size is
simply the max, 32, minus what we cut out for the low hole. The
two top level buddies are [8 -> 24), and [24 -> 32).
Now, suppose, instead the base were 4:
Base: 4
Size: 28
Managed space: [4, 32)
The top level buddies would be [4 -> 20), [20 -> 28), and [28 -> 32).
This presents several problems: none of the buddies are PDE aligned
and one top level buddy is smaller than the PDE size. The simplest
issue is how to determine the PTE size of the [28 -> 32) block. We
can just set it as small but that's not ideal. The bigger issue is
the mis-alignment of the larger buddies. [20 -> 28) is halfway in
one PDE and halfway in another. That means the allocator would have
to manage the two sub-buddies [20 -> 24) and [24 -> 28) separately.
Instead of dealing with the above issues in the allocator it is much
more simple to require that any GVA space is PDE aligned since they
are already massive and already, in practice, have this alignment.
Change-Id: I9eacd2db6485291db9f9f1d6c4c03c2a5c22de03
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1185137
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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In the buddy allocator the BALLOC_PTE_SIZE_* macros are inconsistent
with the gmmu_page_size_* enum. This patch makes the buddy allocator
use the gmmu_page_size_* fields and now has only BALLOC_PTE_SIZE_ANY
for when the allocator does not care about PTE size.
Change-Id: Idbe727b8208e1ace2b947d67f698c471782d5587
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1185136
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Correct the formula used to determine the range for BE registers
Bug 1778245
Change-Id: I5443b3e68d920cecd031a9b154ed90f26e5251b2
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1170602
(cherry picked from commit 813a08f1aa758d718987b4e6f2cf2ac8d15a1611)
Reviewed-on: http://git-master/r/1177828
(cherry picked from commit de8239a5c6241419b98276a5f549ed8cfd7f4cf9)
Reviewed-on: http://git-master/r/1181500
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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When mapping a userspace buffer, determine if it was vidmem allocated
from the aperture of the current gpu, and pass that information into
page tables.
Mapping a vidmem buffer to a gpu it wasn't allocated from is disallowed.
This includes mapping vidmem to igpus and to possibly other dgpus on the
system.
Jira DNVGPU-19
Change-Id: Ia9d2d0133e77659ab96b36ed61eeb4cd5a2b7dff
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1169309
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add NVGPU_GPU_IOCTL_ALLOC_VIDMEM to the ctrl fd for letting userspace
allocate on-board GPU memory (aka vidmem). The allocations are returned
as dmabuf fds.
Also, report the amount of local video memory in the gpu
characteristics.
Jira DNVGPU-19
Jira DNVGPU-38
Change-Id: I28e361d31bb630b96d06bb1c86d022d91c7592bc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1181152
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Use the nvgpu-internal buddy allocator for video memory allocations,
instead of nvmap. This allows better integration for copyengine, BAR1
mapping to userspace, etc.
Jira DNVGPU-38
Change-Id: I9fd67b76cd39721e4cd8e525ad0ed76f497e8b99
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1181151
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Fix some checkpatch warnings and copyright issues.
Change-Id: I841492d1e83ced3483b559ad4d9c4404d1adb83f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1183570
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Added interface to allow kernel to create privileged CE channels for
page migration and clearing support between sysmem and videmem.
JIRA DNVGPU-53
Change-Id: I3e18d18403809c9e64fa45d40b6c4e3844992506
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1173085
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Unset get_phys_addr_bits as PCIe devices do not need
to care if SMMU is enabled or not.
Jira VFND-1965
Change-Id: I358834863fb365092904da219be80d764f6af8ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1183089
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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In addition to nonwpr_base address, allocate also the wpr_base that is
configured as wpr, in order to not overlap user allocations on that
area.
This patch adds just the wpr region's mem_desc field available. For
devices that use the wpr separately, the field is used for that alloc.
Jira DNVGPU-18
Change-Id: I4a7523f2af2379ee38bdd34cb8ca2d81360dff7b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1182873
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Fixed the following warning:
- gk20a.c:147:5: warning: symbol
'gk20a_railgating_debugfs_init'
was not declared ?
Bug 200067946
Bug 200088648
Change-Id: Ic7b1a24cee5066249e7d25db87a3e1569a608e6c
Signed-off-by: Minal Ugale <mugale@nvidia.com>
Reviewed-on: http://git-master/r/1183272
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Implement a bitmap allocator for GPU use. This allocator is useful for
managing memory (or resource) regions where the buddy allocator is not
ideal. Some instances are small regions or where the resource management
must not make calls to the kernel's memory allocation routines (anything
that ultimately calls alloc_page()).
The code path where this avoidance of alloc_page() is most required is
the gpfifo submit path. In order to keep this routine fast and have
predicable time constraints no alloc_page() calls is necessary. The
buddy allocator does not work for this since every time a buddy is
allocated there is the possibility that a pair (or more) buddy structs
have to be made. These allocs could perhaps require a call into
alloc_page() if there is not enouch space in the kmem_cache slab for
the buddy structs.
Change-Id: Ia46fce62d4bdafcebbc153b21b515cb51641d241
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1176446
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Allow individual allocacators to be debugged without enabling debugging
on all allocators. The ALLOCATOR_DEBUG define will still work as
expected and enable debugging for all allocators that see this define.
Change-Id: I0d59fa29affeaac15381e65d4128e7bef2f15bd5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1178689
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Move to a more generic name of GPU_ALLOC_*.
Change-Id: Icbbd366847a9d74f83f578e4d9ea917a6e8ea3e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1176445
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Move the buddy allocator implementation to a new file to make the
code more organized. Also, as part of this, commonize some macros
and functions which will be used by future allocator implementations.
Bug 1781897
Change-Id: I1611534d5d872bf3b4677f7a1cc024a94b1c437e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1172116
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Support multiple types of allocation backends. Currently there is
only one allocator implementation available: a buddy allocator.
Buddy allocators have certain limitations though. For one the
allocator requires metadata to be allocated from the kernel's
system memory. This causes a given buddy allocation to potentially
sleep on a kmalloc() call.
This patch has been created so that a new backend can be created
which will avoid any dynamic system memory management routines
from being called.
Bug 1781897
Change-Id: I98d6c8402c049942f13fee69c6901a166f177f65
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1172115
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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When processing FECS traces, a hash table is used
to retrieve the 'pid' of the process that created
the channel/TSG. Report process identifer (aka
tgid in kernel) instead of thread identifier (aka
pid) for FECS traces.
Bug 1736423
Change-Id: I54cb9d298b9fe3e1cccdd7145604cd01c5758c9d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1166501
(cherry picked from commit f7fd1f6d7ad0753b787ec20604a08a1f4882fe6f)
Reviewed-on: http://git-master/r/1168728
(cherry picked from commit 97a62e5b89352fce576f1bca71b38bf2242ff047)
Reviewed-on: http://git-master/r/1177823
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Jira VFND-1968
Change-Id: Id84c5732e312e44db3d412df5c21e429227dd7fa
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1171286
(cherry picked from commit 13a3a4355914635ed175708affef17dc8ef0b133)
Reviewed-on: http://git-master/r/1177824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Added a dedicated device node to allow an
app manager to control TSG scheduling parameters:
- Get list of TSGs
- Get list of recent TSGs
- Get list of TSGs per pid
- Get TSG current scheduling parameters
- Set TSG timeslice
- Set TSG runlist interleave
Jira VFND-1586
Change-Id: I014c9d1534bce0eaea6c25ad114cf0cff317af79
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1160384
(cherry picked from commit 75ca739517cc7f7f76714b5f6a1a57c39b8cb38e)
Reviewed-on: http://git-master/r/1167021
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- remove checking of has_physical_mode
- check whether get_physical_addr_bits is null
JIRA VFND-1965
Change-Id: If19b297dc853b9e0b5879c5b2e0a350b5d9b279a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1175738
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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This patch calculates:
-Total time spent by GPU with rails gated.
-Total time spent by GPU with rails ungated.
-Total Railgating Cycles.
and dumps this information in debugfs file.
This feature requires CONFIG_DEBUG_FS set to true.
Bug 200195100
Change-Id: I1379f11237ce4900076947e18524caaa3304c7cb
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1178308
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Replace kfree with nvgpu_free in error handling path in
gk20a_alloc_channel_gpfifo where the gpfifo pipe buffer is being
allocated, because it's allocated with nvgpu_alloc.
Jira DNVGPU-21
Change-Id: I73100394b67da2ab064e4e9df6b430d818abce56
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1182401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add "soc/tegra/fuse.h" to include declaration of tegra_get_chip_id()
for kernel version 4.4 and higher as upstream fuse header is not
available in older kernel versions.
Change-Id: Ib83fc6965bc46bb729eab1cc583b9c963f501738
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/1180686
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Add static qualifier to nvgpu_pci_pm_init, as it is
only used within the current file.
Bug 200067946
Bug 200088648
Change-Id: Ifb7d3ec174a9f8eea0ac53421c953761886f48c6
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1181867
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
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Bug 1781383
CID 37989
- Changed for_each_set_bit addr parameter to unsigned long.
Change-Id: I3f3f314a1aea9d376d45699f870a9e372854f069
Signed-off-by: George Bauernschmidt <georgeb@nvidia.com>
Reviewed-on: http://git-master/r/1177417
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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If page tables are allocated from vidmem, cpu cache flushing doesn't
make sense, so skip it. Unify also map/unmap actions if the pages are
not mapped.
Jira DNVGPU-20
Change-Id: I36b22749aab99a7bae26c869075f8073eab0f860
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1178830
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Send cmd to RM server to change clk rate when PM_QOS_GPU_FREQ_BOUNDS
max changes.
Bug 200206160
Change-Id: I7f19e5f711426517baf8e7f934bf41972012644b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1172792
(cherry picked from commit 973c258fd85449c3862df2498362e358fd3682c9)
Reviewed-on: http://git-master/r/1180892
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Enable runtime power management ops for PCIe devices, and
move gk20a_pm_finalize_poweron call into the resume routine.
This change only implements suspend as a stub, as suspend/resume
has not yet been verified for dGPU
Bug 1785512
Bug 200187507
Change-Id: I076bafc03c6b4ba10dce874804ed3fd0b9c7b0d8
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1179860
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Set has_physical_mode if running on native linux for better performance.
Set it false if running on native gpu but on linux-hv, as the driver
can not get real physical address.
JIRA VFND-1965
Change-Id: I6e0322e64ad14d35d179a33e979157b53d77005a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1175739
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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The allocator doesn't give us empty pages, so make sure that they're
full of zeros, just like the sysmem alloc path does.
Jira DNVGPU-16
Change-Id: I0ff8a0718829b13973535ba1111a8a11b91be04d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1178829
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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