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* gpu: nvgpu: HAL to get current pstateMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | - Added HAL support to get current pstate from clk_arb Note - This function is inherently unsafe to call while arbiter is running arbiter must be blocked before calling this function JIRA DNVGPU-165 Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1286378 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix pmu->mscg_stat optimization issueMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | | | | | | - with help of WRITE_ONCE() & ACCESS_ONCE() make sure variable pmu->mscg_stat read/write goes through without optimization - Added WRITE_ONCE() define for kernel-3.18 version & below to support backward compatibility issue: inconsistencies on getting MSCG to trigger consistently in P5 due to a lack of memory barrier around and volatile accesses to the variable pmu->mscg_stat JIRA DNVGPU-71 Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252524 (cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b) Reviewed-on: http://git-master/r/1271614 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix freq roundingDeepak Nibade2017-01-17
| | | | | | | | | | | | | | | | | In gp10b_round_clk_rate(), we right now return next higher freq value than requested if requested value matches a value in the table Fix this by adding a right comparison Bug 200194487 Change-Id: Ia99abfe4b247701d5ee1cda26b3ffcc18efba353 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1284302 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: print process name on submit failureDeepak Nibade2017-01-17
| | | | | | | | | | | | | | | | | | | Print process name if we fail submit due to gk20a_busy() failure This is helpful in debugging and to know the process name submitting jobs to nvgpu after system shutdown was already triggered Bug 200262275 Change-Id: I34d8c07fc96fd5556afa982bfd56f7f3964449d0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1284113 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: sim: avoid fecs golden context restoreseshendra Gadagottu2017-01-16
| | | | | | | | | | | | | | | | | | | When gpu host is executing a context, there should not be any calls to fecs that can change the current context in execution. For some reason legacy fmodels are calling fecs method to golden context restore while loading golden context for new channel. This call is not required and should not be called. Only first time during golden context creation, fecs methods like bind can be called and it is pretty safe to do. Bug 1834201 Change-Id: Ia6178e875e3ac37fb1cf10e27976c26b9a02c56f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1284512 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use HAL to set TSG timesliceThomas Fleury2017-01-16
| | | | | | | | | | | | | | | | | | | | | | | | | Setting timeslice for virtualized case was not effective, because both ioctls NVGPU_TSG_IOCTL_SET_TIMESLICE and NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE were calling the native function to set TSG timeslice. - Fixed wrapper function to call HAL - Defined HAL function for "native" set TSG timeslice - Also, properly update timeout_us in TSG context, in virtualized case. This change also moves the min/max bounds checking for tsg timeslice into the native function implementation. There is no sysfs node for these parameters for vgpu, as RM server is ultimately responsible for this check. Bug 200263575 Change-Id: Ibceab9427561ad58ec28abfff0c96ca8f592bdb9 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1283180 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PG sysfs update for RPPG/MSCGMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | | | | | - Added sysfs node to control RPPG/MSCG enable/disable - RPPG is controlled with elpg_enable node, same node used to control ELPG. - MSCG is controlled with mscg_enable node JIRA DNVGPU-71 Change-Id: I1a1b33d7425c25c9cfd466f7cabce08f3152326d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1251611 (cherry picked from commit eaf255f2dd3d20c071714dd509a785e9172399bf) Reviewed-on: http://git-master/r/1274645 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: HAL to query LPWR feature supportMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | HAL to query LPWR feautre's RPPG/MSCG support based on current pstate configured. JIRA DNVGPU-71 Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1283916 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* nvgpu: gp10b: remove EMC floor when GPU FminCyril Raju2017-01-13
| | | | | | | | | | | | | | | | | | Remove EMC floor when GPU frequency is Fmin. At Fmin, we most likely require a very low memory bandwidth. At Fmin on load, actmon should sufficiently scale EMC and hence not bottlenecking GPU. Bug 1850297 Change-Id: I98b9dae648ea28910d534a9286ce2e9e91ea5fec Signed-off-by: Cyril Raju <craju@nvidia.com> Reviewed-on: http://git-master/r/1284572 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add sysfs nodes for timeslice min/maxPeter Boonstoppel2017-01-12
| | | | | | | | | | | | | | | | | | The timeslice values that can be selected for a particular channel/tsg are bounded by a static min/max. This change introduces two sysfs nodes that allow these bounds to be configured from userspace. min_timeslice_us max_timeslice_us Bug 200251974 Bug 1854791 Change-Id: I5d5a14225eee4090e418c7e43629324114f60768 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1280372 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update patch count after addingTerje Bergstrom2017-01-11
| | | | | | | | | | | | | | | | | | When kernel adds patches to a context, kernel needs to update the patch count in order for FECS to pick up the new patches. Previously patching was done only at the context creation time. Now patching is used also when changing preemption mode, but the patches did not take effect due to not updating count. Update patch count every time we end patching of a context. Bug 1852094 Change-Id: Ic2150741609d1d1956769e439ce1c5f2edcacb84 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280424 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gp106 HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp106 HW headers to a new directory specially for them: include/nvgpu/hw/gp106 And change the code to include like so: #include <nvgpu/hw/gp106/hw_fb_gp106.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280327 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gp10b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp10b HW headers to a new directory specially for them: include/nvgpu/hw/gp10b And change the code to include like so: #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gm206 HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gm206 HW headers to a new directory specially for them: include/nvgpu/hw/gm206 And change the code to include like so: #include <nvgpu/hw/gm206/hw_fb_gm206.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I90dc39e64e1b58ee9e87fbc26ad0d18c361e239c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244792 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gm20b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gm20b HW headers to a new directory specially for them: include/nvgpu/hw/gm20b And change the code to include like so: #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I0765e2f6bcd5aa1e803efd250056de3cf9bfa7ed Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244791 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Start re-organizing the HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | | | | Reorganize the HW headers of gk20a. The headers are moved to a new directory: include/nvgpu/hw/gk20a And from the code are included like so: #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> This is the first step in reorganizing all of the HW headers for gm20b, gm206, etc. This is part of a larger effort to re-structure and make the driver more readable and scalable. Bug 1799159 Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244790 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for refcount trackingKonsta Holtta2017-01-11
| | | | | | | | | | | | | | | | | If enabled, track actions (gets and puts) on channel reference counters. Dump the most recent actions to syslog when gk20a_wait_until_counter_is_N gets stuck when closing a channel. GK20A_CHANNEL_REFCOUNT_TRACKING specifies the size of the action history. Default is to disable completely, as this has some runtime overhead. Bug 1826754 Change-Id: I880b0efe8881044d02ae224c243a51cb6c2db8c1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1262424 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set PMU "queue full" as debug messageMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | Queue full message is not an error, it informs queue is full & wait till it gets space in queue to upload pending request. Bug 200256603 Change-Id: I14f4196b391cd54e1b9616f0555a5ce0856af428 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1260494 (cherry picked from commit e7360fb52b2030c9c68aa5ed06ecd7c32b47a8c5) Reviewed-on: http://git-master/r/1271619 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pg mscg state updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | - Added mscg_transition_state to know mscg allow/disallow status - reused ELPG state transition defines for mscg state transition JIRA DNVGPU-71 Change-Id: Ie0214a174ceecf7e97a1086f53fd965b0b655d14 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1253508 (cherry picked from commit 726dde9cff1da38525518a91e756598a5ab71f73) Reviewed-on: http://git-master/r/1271617 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu->pmu_state updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | - set pmu->pmu_state to PMU_STATE_ELPG_BOOTED only for ELPG after PMU_STATE_ELPG_BOOTING state Bug N/A Change-Id: I08480e2afd5a5050a903327b91e43b25780cdaf8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1254429 (cherry picked from commit d68f4f91796d1d98dbc1b5b24d526fe2e487966f) Reviewed-on: http://git-master/r/1271616 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal alarm notification for UMDLakshmanan M2017-01-10
| | | | | | | | | | | | | | | Added the thermal alarm notification handling for UMD JIRA DNVGPU-130 Bug 200231080 Change-Id: I034c7b35a18a091ef7659ff992f1950576623cad Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1251760 (cherry picked from commit 9e66f2e2f7fbcab29e25c976c1d5fa29671afcd0) Reviewed-on: http://git-master/r/1282084 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pg stat read updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added struct pmu_pg_stats_data to extract data from multiple version of pmu pg statistics - Added pmu_pg_stats_v2 interface to fetch PG statistics data from PMU - Added MSCG debugfs node to read mscg statistics from PMU. - Added pmu_elpg_statistics HAL support for gp106 PG statistics read. - Made changes to gp104/gp106 pmu_elpg_statistics HAL to support for struct pmu_pg_stats_data JIRA DNVGPU-165 Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252798 (cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd) Reviewed-on: http://git-master/r/1271615 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal alert limit IOCTL for UMDLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | Added the thermal alert lmit IOCTL for UMD JIRA DNVGPU-130 Bug 200231080 Change-Id: I43a3a5df18467e05c32d043f49440d2086438ebe Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1249490 (cherry picked from commit b4123e45956bd02994fd284e8bfd6ce015aa0867) Reviewed-on: http://git-master/r/1282082 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add thermal alert event handlingLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | * Added the thermal alert event handling * Added the thermal alert event PMU RPC JIRA DNVGPU-130 Bug 200231080 Change-Id: I54ab0dc35a940e70733238fd95669db28389619a Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1248968 (cherry picked from commit a20593c89a374d64201e4720552160a65533ecc3) Reviewed-on: http://git-master/r/1282076 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add thermal alert limit IOCTL for UMDLakshmanan M2017-01-10
| | | | | | | | | | | | | | | Added the thermal alert lmit IOCTL for UMD JIRA DNVGPU-130 Bug 200231080 Change-Id: I4a84157d90b12b576fa144567a3bdd5d39f5278e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1249483 (cherry picked from commit d3458008cc3dd98d3a51841b6ed8cea1aed9eb89) Reviewed-on: http://git-master/r/1253457 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add thermal alert event handlingLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | * Added the thermal alert event handling * Added the thermal alert event PMU RPC JIRA DNVGPU-130 Bug 200231080 Change-Id: If5ff2704e5aa6ad2f25123f72c3049a311dae5dc Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1248964 (cherry picked from commit 1850e5a9b9dfa2f9df634e2f284ab282ad9f7fc8) Reviewed-on: http://git-master/r/1253452 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable mscgMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | | | | - Enable MSCG support to engage/disengage MSCG if selected PSTATE supports - MSCG is dependent on RPPG to engage/disengage else MSCG doesn’t engage/disengage. JIRA DNVGPU-71 Change-Id: I8301f3354f2be8bbef70b292cbe4ae3fc22cd54e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1250909 (cherry picked from commit 0fd98aee7f290b76d3eead1b7e491edc207ae34c) Reviewed-on: http://git-master/r/1270974 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable RPPGMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | - enable RPPG support to engage/disengage RPPG if selected PSTATE supports JIRA DNVGPU-71 Change-Id: I188c8e6235a25ed8c342aef42b39d48cc6378db3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1250509 (cherry picked from commit a6ef8204538bb94a53a09e569e727c02dab7fdd0) Reviewed-on: http://git-master/r/1270973 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move GPFIFO to sysmemTerje Bergstrom2017-01-09
| | | | | | | | | | | | | | | Kickoff latencies when GPFIFO is in vidmem grow significantly as function of number of GPFIFO entries. Move GPFIFO to sysmem to improve kickoff latency. Bug 1848369 Change-Id: Ie95d10df26b4f1370f7250a8fbf0f7ef0211df32 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry-picked from commit 897cb579a759bbe8455ce368413979e91eb0d475) Reviewed-on: http://git-master/r/1281564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move allocators to common/mm/Alex Waterman2017-01-09
| | | | | | | | | | | | | | | | | | | Move the GPU allocators to common/mm/ since the allocators are common code across all GPUs. Also rename the allocator code to move away from gk20a_ prefixed structs and functions. This caused one issue with the nvgpu_alloc() and nvgpu_free() functions. There was a function for allocating either with kmalloc() or vmalloc() depending on the size of the allocation. Those have now been renamed to nvgpu_kalloc() and nvgpu_kfree(). Bug 1799159 Change-Id: Iddda92c013612bcb209847084ec85b8953002fa5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1274400 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: receive event TEGRA_VGPU_EVENT_SM_ESRRichard Zhao2017-01-06
| | | | | | | | | | | | | | | | - allocate gr.sm_error_state - handle event of sm error state - add callback of clear sm error state JIRA VFND-3291 Bug 200257899 Change-Id: I49b9437013e8c65290750b7fe21fc6819ea93b1c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1278397 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: restructure event handlingRichard Zhao2017-01-06
| | | | | | | | | | | | | | | | Take interrupts as one kind of event message, and make it easier to add new kind of events. JIRA VFND-3291 Bug 200257899 Change-Id: I83482293230c0aa10b05caf61e249a042bf6653c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1278396 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: CPU timestamps for alarmsThomas Fleury2017-01-06
| | | | | | | | | | | | | | | Use sched_clock() for alarm timestamps to return number of nanoseconds since the system was started. Jira DNVGPU-186 Change-Id: Ie16fe5442ea8a5213bf5401a3faedcce387b3d93 Reviewed-on: http://git-master/r/1259026 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 383601c4d006734e13f0bfa386381573c87209da) Reviewed-on: http://git-master/r/1280888 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for alarms in arbiterDavid Nieto2017-01-06
| | | | | | | | | | | | | | | | | Add a queue system to collect alarm notifications and deliver them to user space Add interface for driver to set global alarms JIRA: DNVGPU-189 Change-Id: I24a340283c02d8ea95ad6ea148acdb37157ef69c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1252475 (cherry picked from commit 5b79c7541066148ce0580d25daad54a8fa82f8be) Reviewed-on: http://git-master/r/1280887 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for alarms in arbiterDavid Nieto2017-01-06
| | | | | | | | | | | | | | | Pass flags as mask in event initialization JIRA: DNVGPU-189$ Change-Id: Ied22a585a8f59f44e577bc678f8cef380432c9a2 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1252474 (cherry picked from commit 56fa34b8ac0ebafaf09a8760bec6200adf9f3c39) Reviewed-on: http://git-master/r/1280886 GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add read and ioctl for eventsThomas Fleury2017-01-06
| | | | | | | | | | | | | | | Add support for poll/read/ioctl for events in clock arbiter. Jira DNVGPU-186 Change-Id: Id95264fffae2b83a388ff8f186ebe7d723029b7f Reviewed-on: http://git-master/r/1253659 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 8d652a7313722aab331f82f0841b490ca25cb51d) Reviewed-on: http://git-master/r/1280885 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: round clock locallyDeepak Nibade2017-01-06
| | | | | | | | | | | | | | | | | | In gp10b_round_clk_rate(), we currently call clk_round_rate() to round the clock rate for us But since the frequency table is prepared using the frequency values supported in h/w, we can round the rate locally using the table Bug 1827281 Change-Id: I85d034326539590352badceb4164aa5d89ee8842 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1280630 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: select N'th freq from all available frequenciesDeepak Nibade2017-01-06
| | | | | | | | | | | | | | | | | | | | | | | | | We right now get min and max frequencies, and then interpolate rest of the frequencies. With this approach, we do not select exact frequencies as supported by h/w Fix this so that we query all supported frequencies using clk_round_rate() and then select every N'th frequency to keep number of frequencies under limit Use GP10B_FREQ_SELECT_STEP (currently set to 8) to configure frequency selection step Raise GP10B_MAX_SUPPORTED_FREQS to 200 since h/w supported frequencies could be in that range Bug 1827281 Change-Id: Id8678d7a0280a249e4affbba084ff2e33b6694e6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1280629 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not access NULL pointer devTerje Bergstrom2017-01-06
| | | | | | | | | | | | | In gk20a_busy() we check if dev is NULL and return -ENODEV if so. But before that we've already dereferenced dev by passing it to get_gk20a(). Defer call to get_gk20a() until after the NULL check. Bug 200192125 Change-Id: I943a9e96d13ff8cb4333fe20a941c8e95d159a66 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280349 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Do not recursively #include clk.hTerje Bergstrom2017-01-06
| | | | | | | | | | | | | clk.h #includes clk_vin.h, which recursively #includes clk.h without needing anything from clk.h. Remove the #include to improve build time. Bug 200192125 Change-Id: Icab32b7e73a1eaaee8e017367d71b8ebde47c21e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280350 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Use perf table only if VBIOS supports itTerje Bergstrom2017-01-06
| | | | | | | | | | | | | | | | We retrieve perf table from VBIOS only if respective HAL op is implemented. Later in code we unconditionally dereference a pointer which can lead to NULL pointer access. Fix two new cases by early aborting creation of devinit tables if the perf VBIOS getter is missing. Bug 200192125 Change-Id: I30f20f1829305ecc1117c6301e26ff1b869967eb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280347 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Don't recursively #include ctrlvolt.hTerje Bergstrom2017-01-06
| | | | | | | | | | | | | ctrlvolt.h #includes ctrlperf.h, which recursively #includes ctrlvolt.h without needing anything from it. Remove the #include to improve built time. Bug 200192125 Change-Id: I8c917533127e6d42aae6ad1401860c1f5d110d81 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280345 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix out-of-bound access on gr->map_tilesDeepak Nibade2017-01-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix slab-out-of-bounds issue reported by KASAN [ 28.464077] BUG: KASAN: slab-out-of-bounds in gr_gk20a_init_map_tiles+0x624/0x708 at addr ffffffc1a098ee01 ... [ 28.503241] INFO: Allocated in gr_gk20a_init_map_tiles+0x2dc/0x708 age=11 cpu=5 pid=1 out-of-bound access from below 3 stacks : [1] [ 28.782886] [<ffffffc0007d5f64>] gr_gk20a_init_map_tiles+0x624/0x708 [ 28.789228] [<ffffffc0007eadf0>] gk20a_init_gr_support+0x2d0/0xeb0 [ 28.795397] [<ffffffc00079d9c8>] gk20a_pm_finalize_poweron+0x738/0xd10 [2] [ 29.268070] [<ffffffc0007d618c>] gr_gk20a_zcull_init_hw+0x144/0x730 [ 29.274329] [<ffffffc0007d6a00>] gk20a_init_gr_setup_hw+0x288/0x1530 [ 29.280677] [<ffffffc0007eac6c>] gk20a_init_gr_support+0x14c/0xeb0 [ 29.286938] [<ffffffc00079d9c8>] gk20a_pm_finalize_poweron+0x738/0xd10 [3] [ 50.076223] [<ffffffc000d1df14>] gr_gk20a_setup_rop_mapping+0x5e4/0x2018 [ 50.082913] [<ffffffc000d2559c>] gr_gk20a_init_fs_state+0x80c/0x1028 [ 50.089259] [<ffffffc000ddcbc8>] gr_gm20b_init_fs_state+0xc8/0x960 [ 50.095430] [<ffffffc000e413f8>] gr_gp10b_init_fs_state+0x5c0/0x5d8 [ 50.101687] [<ffffffc000d2ed30>] gk20a_init_gr_setup_hw+0x1b48/0x2418 [ 50.108115] [<ffffffc000d50bc0>] gk20a_init_gr_support+0x19e0/0x1ab0 [ 50.114457] [<ffffffc000cc7af8>] gk20a_pm_finalize_poweron+0xd20/0x1558 Fix this by adding below - allocate gr->map_tiles[] with size of (num_gpc * num_tpc_per_gpc) intead of num_gpc - add new static API gr_gk20a_get_map_tile_count() which returns tile count for given index, and returns 0 for out-of-bounds access Bug 200257557 Change-Id: If572837ffb661f92a21be5ce855d0146b2609cb0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1279411 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Don't recursively #include gk20a.hTerje Bergstrom2017-01-05
| | | | | | | | | | | | | | | | | gk20a.h includes pmu_gk20a.h, which #includes gpmuifboardobj.h, which recursively #includes gk20a.h without needing anything from it. Remove the #include to improve built time. gpmuifboardobj.h also includes pmu_gk20a.h, when it actually needs a definition from pmu_common.h. Change the #include to prevent another recursive #include. Bug 200192125 Change-Id: Idb8c13bceeae1a60a4efa466c07e78cb15ffa1fb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280348 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: free boardobj if construct hits an errVijayakumar2017-01-05
| | | | | | | | | | | | | | | | | | | During construct of some VFE/CLK boardobjs, some data is filled after a boardobj allocation is done. Free up boardobj memory if an error is encountered in the data filling. Coverity ID 490171 Coverity ID 490172 Bug 200192125 Change-Id: I20621f7f9f9e379b8dced4905cd417c2ffa905b0 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1280700 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add GPCCLK on ioctl APIThomas Fleury2017-01-05
| | | | | | | | | | | | | | | Internally we use GPC2CLK in the arbiter, but we should expose GPCCLK on kernel API and in user space. Added GPCCLK on the ioctl API. Arbiter uses GPC2CLK to make queries, then converts to GPCCLK. Jira DNVGPU-210 Change-Id: Id0b8134d0505c1f9bfd655a08e902bdcd03ebd96 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1280316 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Apply default pri timeout on all SKUsDavid Nieto2017-01-05
| | | | | | | | | | | | | | | Previous patch added ability so set default PRI timeout and set it for one of the dGPU boards. Set the timeout to all known dGPU boards. Bug 200246808 Change-Id: I645ca8b4a51d61c924a9f52b1fc6e884795adf19 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1264304 Reviewed-on: http://git-master/r/1280436 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: return error on pmu_ucode_details() failureDeepak Nibade2017-01-05
| | | | | | | | | | | | | | | | | | | | | | In lsfm_discover_ucode_images(), we currently collect pmu ucode details with API pmu_ucode_details() But if this API fails, we still continue loading other firmwares In case loading of pmu firmware fails due to some reason, we should actually bail out immediately with error Also, remove unnecessary chekc (ucode_img.lsf_desc != NULL) since pmu_ucode_details() ensures that this cannot be NULL Bug 200265373 Change-Id: I68e7f9575e2a07b473ceacc528a5d172b58d6fb6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1276555 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement SET_RD_COALESCETerje Bergstrom2017-01-05
| | | | | | | | | | | | | Implement SW method SET_RD_COALESCE to implement correct handling of texture read coalescing. Bug 200223870 Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1271303 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: remove default verbose in pbus isrDavid Nieto2017-01-04
| | | | | | | | | | | | | | And reduce pri timeout to match PCIE specs bug 200246808 Change-Id: I0225ae964b5635665fe774c43f773d0ce86650ab Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1264179 (cherry picked from commit 1c3dbf8324b7ec5d06bd0e57e7deee9a1c8e9411) Reviewed-on: http://git-master/r/1280328 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:52:01 -0500