nvgpu.git - Tegra GPU Driver. Originally from nv-tegra.nvidia.com/linux-nvgpu.git.

	Commit message (Expand)	Author	Age
...
*	gpu: nvgpu: gp10b: setup mm hw init	Seshendra Gadagottu	2016-12-27
*	gpu: nvgpu: gp10b: update fb headers	Seshendra Gadagottu	2016-12-27
*	gpu: nvgpu: gp10b: update headers	Seshendra Gadagottu	2016-12-27
*	gpu: nvgpu: gp10b: add ce interrupt support	Sam Payne	2016-12-27
*	gpu: nvgpu: Add ELPG_ENABLE register	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b specific LTC ISR	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Set correct PBDMA signature	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Enable warnings as errors	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: reg with FECS HALT method	Supriya	2016-12-27
*	gpu: nvgpu: gp10b: dump GR status registers	Deepak Nibade	2016-12-27
*	gpu: nvgpu: gp10b: use tight loop for fecs method	Vijayakumar	2016-12-27
*	gpu: nvgpu: headers for linsim CL 34116551	Peng Du	2016-12-27
*	gpu: nvgpu: gp10b: Enable debug spew	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: enable CDE for t18x	Jussi Rasanen	2016-12-27
*	gpu: nvgpu: read gobs_per_comptagline_per_slice	Jussi Rasanen	2016-12-27
*	gpu: nvgpu: gp10b: Compression page size to 64k	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Add Bar2 support	Seshendra Gadagottu	2016-12-27
*	gpu: nvgpu: gp10b: enable replayable fault interrupt	Seshendra Gadagottu	2016-12-27
*	gpu: nvgpu: headers for linsim CL 34000094	Adeel Raza	2016-12-27
*	gpu: nvgpu: gp10b: update headers	Seshendra Gadagottu	2016-12-27
*	gpu: nvgpu: gp10b: Enable cycling through ctx bins	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Default page size 64kB	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Fix L2 size calculation	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Enable CILP mode for compute	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: Handle MC pmu interrupts	Mahantesh Kumbar	2016-12-27
*	gpu: nvgpu: gp10b: gpmu elpg support	Mahantesh Kumbar	2016-12-27
*	gpu: nvgpu: Implement gp10b context creation	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Correct SMMU bit number	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Change order of alpha & beta	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Program CB sizes	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Implement SW methods	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Calc global context buffer size	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Add new supported kind	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Define pagepool size	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Define physical address width	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: Write ZBC registers to DSS	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: Define gp10b big page size	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: Add SM registers	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: Use queried interrupt ids	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Implement L2 query	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: headers for linsim CL 33823014	Adeel Raza	2016-12-27
*	gpu: nvgpu: gp10b: Enable interrupts in linsim	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Fill class numbers	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: Add own platform data to enable host1x	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b: Add SM debug registers	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: gp10b specific CB callbacks	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: Implement gp10b intr processing	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: t18x, gp10b framework	Kenneth Adams	2016-12-27
*	gpu: nvgpu: Synchronize gp10b headers with gm20b	Terje Bergstrom	2016-12-27
*	gpu: nvgpu: headers for linsim CL 33759297	Adeel Raza	2016-12-27