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* gpu: nvgpu: Remove setting of PRI timeoutTerje Bergstrom2018-06-14
| | | | | | | | | | | | | PRI timeout should always use the HW initialization value. Do not set it explicitly. JIRA NVGPU-588 Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730892 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove direct MC and GR deps from busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | | | bus_gk20a.c had some debug dump references to MC and GR registers. The dumps have not been very useful, so instead of refactoring the code just remove the dumps. JIRA NVGPU-588 Change-Id: Id974731716d058ef4a3fe77240c11b1c53db169c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting of BAR0_WINDOW to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to common code so that pramin_gk20a.[ch] can be deleted. JIRA NVGPU-588 Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730890 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting priv interrupt to priv_ringTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Registers to set priv interrupts are in priv_ring, but the code was in bus HAL. Move the code and related HALs to priv_ring instead. JIRA NVGPU-588 Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730889 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: bus: Remove use of extra includesTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | bus_gk20a.c had a few unnecessary includes. Remove them to speed up compilation. JIRA NVGPU-588 Change-Id: I0e94e788104ba6acb259c315734e6b42f69a8074 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730888 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: clean up nonstall isrsRichard Zhao2018-06-14
| | | | | | | | | | | | | | | | | | It has moved to use TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP, removing legacy isrs. Jira EVLR-2696 Change-Id: Ie977bba59c0af8589989d872150c3f9b2080854a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1736399 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gr: remove only created sysfs nodesNitin Kumbhar2018-06-14
| | | | | | | | | | | | | | | | Sysfs nodes for GR stats are created on GR init. If nvgpu module is removed without any ops, then it tries to remove sysfs nodes which do not exist resulting in kernel panic. Fix this issue by removing sysfs nodes only if ecc counters are initialized. Bug 1987855 Change-Id: I3f967ee92ec02ad19ffbd9bfa8bace5bfd229dd2 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: skip destroy if vidmem not initializedNitin Kumbhar2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | The vidmem shall be destroyed only if it has been initialized. If not skipped, it accesses mutexes which are in invalid state. This results in BUG like: BUG: spinlock bad magic on CPU#0, rmmod/1560 Also, destroy vidmem bootstrap allocator which is set up in nvgpu_vidmem_init(). Bug 1987855 Change-Id: I68e91422a54b40feeb9071158b797828e2391303 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730535 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add Ctrl API to read SM error stateVinod G2018-06-14
| | | | | | | | | | | | | | Expose IOCTL to Ctrl node to read Single SM error under NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE bug 200412642 JIRA NVGPU-700 Change-Id: I3cbcf4d7f23a53dbd2350b38a5e259559d5fd3af Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gpu railgate handling with runtime pmseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier implementation of railgate disable config is disabling runtime pm during pm_init. This is causing multiple issues: 1. gpu rail will be on as soon as nvgpu driver probe is called. Actual gpu hw init may happen at much later point of time. 2. This is breaking railgate_enable sysfs node functionality. railgate_enable is not working if runtime pm is disabled. To avoid all these issues for railgate disable, enable runtime pm during pm_init and set auto-suspend delay to negative (-1), which will disable runtime pm suspend calls. Also fixed following issues along with this: 1. Updated railgate_enable debugfs implementation to use auto-suspend delay. To disable railgating: Set auto-suspend delay with negative value(-1) which will disable runtime pm suspend. To enable railgating: Set auto-suspend delay with railgate_delay value. Also removed redundant user_railgate_disabled gk20a device data and replaced with can_railgate, where ever it is applicable. 2. Initialized default railgate_delay to 500msec to avoid railgate on/off transitions with railigate enable from disabled state. 3. Created railgate_residency debug fs node irrespective of can_railgate initial state. This is helping with the case, where initial state of railgate state off and then railgate enable is done through sysfs node. Bug 2073029 Change-Id: I531da6d93ba8907e806f65a1de2a447c1ec2665c Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694944 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set gv10x boot clockVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | - Set gv10x boot gpcclk to 952 MHz - Created ops to set gv10x boot gpcclk instead of using clk arbiter to set clocks Bug 200399373 Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700788 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu : nvgpu: gv100 pmu f/w version updateVaikundanathan S2018-06-14
| | | | | | | | | | | | | | -gv100 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1708170/ Change-Id: I91b900dc3c2e702ec1341ac882b4abc7df875c4c Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726913 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: gv100: Fix therm gopsVaikundanathan S2018-06-14
| | | | | | | | | | | | | Fix test crash with therm sw setup by assigning therm limit and alert HAL functions. Bug 200399373 Change-Id: I972b92d949648a9278d3d351a80cc9a68e23cffc Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703778 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add gops to load pstate functionsVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | Add gops to choose to/not to enable 1. clk_freq_controller 2. pmgr_domain 3. lpwr_pg Bug 200399373 Change-Id: Ie5131f9ea260f777fded8392f24815acef6cfbea Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702216 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Update vfe_load for GV100Vaikundanathan S2018-06-14
| | | | | | | | | | | | Add gops to choose vfe_load between GP and GV. Bug 200399373 Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702143 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add option for split rail supportVaikundanathan S2018-06-14
| | | | | | | | | | | | Add gops to check whether split rail is suported in the chip Bug 200399373 Change-Id: I5e955127e06d1fbc9b3eca0a895afa0a06f39d91 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702130 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Set DMA mask on a per-platform basisAlex Waterman2018-06-14
| | | | | | | | | | | | | | | | | | | | Each GPU platform has different DMA limitations. For older chips the maximum size of a DMA buffer was more limited than newer SoCs (read: Xavier) and discrete GPUs. This patch adds support to set the DMA mask for a GPU on a per platform basis by adding a platform field that is populated with the maximum allowed DMA mask. That mask is programmed by the driver common code. If no mask is specified then the default mask size is 16GB (34 bits). Bug 2043276 Change-Id: I9c3c76c86bac6c485eb1197326e662516fbcaa41 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700980 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for pll setupTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | Before nvlink 2.2, driver was responsible for setting the NVLink clocks during NVLink initialization. For the purpose of security, NVLink PLL handling is moved to Minion in nvlink 2.2 and driver should stop writing to these registers. JIRA NVLINK-167 Change-Id: I18392a29c322da55053037bfde62c8f74ee75288 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730597 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for RXDETTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | | RXDET is supported only on nvlink 2.2 devices and forward. Add HAL to run RXDET selectively based on chip. RXDET needs to be done after the links are out of reset but before any other link level initialization. minion_send_cmd is also made non-static to support RXDET functionality. JIRA NVLINK-160 Change-Id: Ic65b8dbc7281743f62072089ff3c805521ac9b38 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729525 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialze bundle64 stateDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | We receive bundle with address and 64 bit values from ucode on some platforms This patch adds the support to handle 64 bit values Add struct av64_gk20a to store an address and corresponding 64 bit value Add struct av64_list_gk20a to store count and list of av64_gk20a Add API alloc_av64_list_gk20a() to allocate the list that supports 64bit values In gr_gk20a_init_ctx_vars_fw(), if we see NETLIST_REGIONID_SW_BUNDLE64_INIT, load the bundle64 state into above local structures Add new HAL gops.gr.init_sw_bundle64() and call it from gk20a_init_sw_bundle() if defined Also load the bundle for simulation cases in gr_gk20a_init_ctx_vars_sim() Jira NVGPUT-96 Change-Id: I1ab7fb37ff91c5fbd968c93d714725b01fd4f59b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1736450 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: adding USERMODE enable bit.Prateek Sethi2018-06-14
| | | | | | | | | | | | | | | | | | This change is required to keep enable USERMODE on QNX as part of gpu characteristics unification. Jira VQRM-3996 Change-Id: I9881c8d3a2dfcadf618a56deee847cd9b575ed7b Signed-off-by: Prateek Sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735573 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix crash due to accessing incorrect TSG pointerDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_gr_isr(), we handle various errors including GPC/TPC errors. And then if BPT errors are pending we call gk20a_gr_post_bpt_events() at the end and pass channel pointer to it gk20a_gr_post_bpt_events() extracts TSG pointer based on ch->tsgid But in some race conditions it is possible that we clear the error and trigger recovery and as a result channel is unbounded from TSG and closed by user space before calling gk20a_gr_post_bpt_events() And in that case the code above results in getting incorrect TSG pointer and hence crashes as below Unable to handle kernel paging request at virtual address ffffff8012000c08 ... [<ffffff8008081f84>] el1_da+0x24/0xb4 [<ffffff80086e72e0>] gk20a_tsg_get_event_data_from_id+0x30/0xb0 [<ffffff80086e7560>] gk20a_tsg_event_id_post_event+0x50/0xc8 [<ffffff800872922c>] gk20a_gr_isr+0x27c/0x12e0 To fix this extract the TSG pointer before handling all the errors and pass this pointer to gk20a_gr_post_bpt_events() will post the events if they are enabled and if TSG is still open Bug 200404720 Change-Id: I4861c72e338a2cec96f31cb9488af665c5f2be39 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735415 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: implement .free_syncpt_bufRichard Zhao2018-06-14
| | | | | | | | | | | | | | | vgpu needs to free the va range besides unmap the syncpt buffer. Jira VFND-4870 Change-Id: Ia9edb687b66db6da8529bf256d348999e24a0bc3 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1693094 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialize HAL for NEXT_2 gpuDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | In gpu_init_hal(), call NVGPU_NEXT_2_INIT_HAL() if we detect chip NVGPU_GPUID_NEXT_2 Jira NVGPUT-95 Change-Id: Ie1121591e53a1587766ea03bb62d0aae01d9ccbf Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1734099 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add g->fifo_eng_timeout_usThomas Fleury2018-06-14
| | | | | | | | | | | | | | Add g->fifo_eng_timeout_us to define engine timeout in microseconds. It is initialized with GRFIFO_TIMEOUT_CHECK_PERIOD_US. In RM server case, it can be overriden with value defined in device tree. Jira EVLR-2674 Change-Id: I69ac2ce779fe575566c8ba48e8cd2d0e6b2d93cf Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728391 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove check to disallow gv100 link0/1Tejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | On GV100, we could not enable reflck repeater at source of PLL which is shared by link 0/1. So we do not allow link 0 and 1 to be used on GV100. This refclk repeater is present only on GV100. Remove the check as we currently use link3 on GV100 and do not plan to use any other link. JIRA NVLINK-162 Change-Id: I9ffcc0b20d084a208271d2c594ec64b5bafaabfb Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1734538 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support CAU ctxsw listDeepak Nibade2018-05-30
| | | | | | | | | | | | | | | | | | | | | | | CAU (Counter Aggregation Unit) registers might be split out from SMPC registers and moved into their own list on some platforms In gr_gk20a_init_ctx_vars_fw() add support to check if pm_cau list is available If list is available, count will be set to non-zero here In add_ctxsw_buffer_map_entries_gpcs(), parse the pm_cau list if count is non-zero Bug 2139870 Change-Id: Ia630e7d03481a6f927c6739d28ebfe49f221326f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1733208 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Braun (SW-GPU) <matthewb@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b/gv100: add SHADER_CUT_COLLECTOR compute classSeema Khowala2018-05-30
| | | | | | | | | | | | | | | | | | | | Support NVC3C0_SET_SHADER_CUT_COLLECTOR s/w method for compute class. This is needed to enable/disable SHADER_CUT_COLLECTOR_STATE. Bug 2108381 Bug 2099681 Change-Id: I228dcc55b6df605aeeee094f872157023e3c783c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730634 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Wei Sun <wsun@nvidia.com> Tested-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: undef min, max macros is definedAlex Waterman2018-05-30
| | | | | | | | | | | | | | | | | | | These macros are sometimes defined by the std library headers. So when they are defined #undef them and use our own version. Also explicitly include types.h from gmmu.c since it uses the min and max macros. JIRA NVGPU-525 Change-Id: I905ff23ef7a4a96467be59c4a124cb09b63f1f96 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721015 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: add impl for nvgpu_is_soc_t194_a01()Alex Waterman2018-05-29
| | | | | | | | | | | | | | | | | This function was added for Linux but not for posix. Thankfully the implementation for posix is trivial: just return false. JIRA NVGPU-525 Change-Id: Ib5af66dedeabb754ce36cbf6f0351e4af3926c52 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730742 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix include path for clockgating headersVinod G2018-05-29
| | | | | | | | | | | | Removed the reference for $NVGPU/drivers/gpu/nvgpu/common from Makefile and fixed the include path for the clockgating headers in HAL files. Change-Id: I34c179866d28c932501b38184ec18d20dce81480 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730759 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: move to use gops.fifo.check_tsg_ctxsw_timeoutRichard Zhao2018-05-25
| | | | | | | | | | | | | Fixing RM server crash when handles ctxsw timeout. RM server needs to call its own HAL of .check_tsg_ctxsw_timeout. Jira EVLR-2691 Change-Id: Ibbc09cbcda39d44dc2a721c9b270d065e13fa9e2 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729900 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract submit profilingKonsta Holtta2018-05-25
| | | | | | | | | | | | | | | | Add gk20a_fifo_profile_snapshot() to store the submit time in a profiling entry that was acquired from gk20a_fifo_profile_acquire(). Also get rid of ifdef CONFIG_DEBUG_FS by stubbing the acquire and free functions when debugfs is not enabled. This reduces some cyclomatic complexity in the submit path. Jira NVGPU-708 Change-Id: I39829a6475cfe3aa582620219e420bde62228e52 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729545 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove empty gk20a_mm_debugfs_initKonsta Holtta2018-05-25
| | | | | | | | | | | | gk20a_mm_debugfs_init() used to initialize one mm-specific debugfs knob, but now that there aren't any, delete the function and the related files. Change-Id: Ic3177945bbab501c506b5199b44c87450df75452 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729530 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove unused function declarationsAlex Waterman2018-05-25
| | | | | | | | | | | | Change-Id: I36f2d13ed3797719137c670afef9b644d48ea16e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727485 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: Use GCC builtins for ffs(), fls()Alex Waterman2018-05-25
| | | | | | | | | | | | | | | | These intrinsics will be fast for the given platform that the compiler is targeting. This also reduces complexity in the code. Change-Id: I6cfb761d6f881056446fa9a5de53dca50ed93c34 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727383 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move bus HAL to commonTerje Bergstrom2018-05-25
| | | | | | | | | | | Move implementation of bus HAL to common/bus. Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726337 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add types.h to clock gating headersAlex Waterman2018-05-24
| | | | | | | | | | | | | | The headers use u32 and bool but do not include <nvgpu/types.h>. Moving around header includes exposed this issue in the cascade builds. This patch fixes the problem in all clock gating headers to avoid this being a concern in the future. Change-Id: Id56074df393d95bf65baf4062ac811d80d87e96b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729748 Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Don't use -lpthread for QNXAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | | The QNX compiler seems to automatically link against this library and as such the extra -lpthread is not necessary. Instead it causes a link failure since the pthread library is not present. JIRA NVGPU-525 Change-Id: Id5a6fcdffb067ed961665a3ee44a9d44301b725b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722157 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove __uXX typedefsAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | | Integrity already typedefs these and complains if you override them even with the same underlying type. Since we only use these in the regops_gk20a.h header file (outside of the Linux specific code, that is) this patch just changes the __uXX to uXX. With that we can delete the now unnecessary __uXX defs. JIRA NVGPU-525 Change-Id: I01dd2723b68db2170449342f73c711ee5a589adb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721186 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add posix condition in sim.hAlex Waterman2018-05-24
| | | | | | | | | | | | | | | Without this the default fall back includes are the rmos headers which are obviously not present for the POSUX build. Change-Id: Iaf7d459e09c62dd57c5b33e21934e40f5780840a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727427 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use proper include path for clockgating headerAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | | | Instead of referencing the header from $NVGPU/drivers/gpu/nvgpu/common reference it from $NVGPU/drivers/gpu/nvgpu. This makes the POSIX compilation happy since we don't do a -Idrivers/gpu/nvgpu/common. Not sure exactly why the regular kernbel build does this but it probably should not. Change-Id: I00aee373b651e3b7710669fa04c5b75fc1c814d9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727426 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix oob access in submit profiling dumpKonsta Holtta2018-05-24
| | | | | | | | | | | | | | | | The number of samples has to be at least the number of percentile ranges (here 20) for the reporting to work as expected and also to not cause negative indices in reading the sorted profile data. If there are not enough samples, just report all zeroes. Change-Id: Ie893859d95074f5ceabf6abe873941873668861d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721892 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to enable/disable hub interruptsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | Add below two new HALs gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs Call the HALs everywhere instead of calling the APIs directly Jira NVGPUT-44 Change-Id: Id299c6d228733ed365a71be6b180186776cc1306 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725977 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export hub intr handling APIsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | Export below APIs in fb_gv11b.h gv11b_fb_handle_dropped_mmu_fault() gv11b_fb_handle_other_fault_notify() gv11b_fb_handle_mmu_nonreplay_replay_fault() gv11b_fb_handle_nonreplay_fault_overflow() gv11b_fb_handle_replay_fault_overflow() gv11b_handle_l2tlb_ecc_isr() gv11b_handle_hubtlb_ecc_isr() gv11b_handle_fillunit_ecc_isr() Jira NVGPUT-44 Change-Id: Ib50e3f3c2f698d486ffe718ebf4a651ccfe8cd93 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725976 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regenerated the gating_reglist.c files for various chips after fixing the script for MISRA C-2012 violations Rule 15.5: Multiple points of exit detected Rule 15.6: "if" body without compound statement Rule 10.3: Implicit conversions of 64bit to 32bit int Rule 7.2: Const must be declared with "U" Rule 5.7: Tags with name xxx already declared Add preprocessor conditional gaurds in gating_reglist header files JIRA NVGPU-671 JIRA NVGPU-656 JIRA NVGPU-688 JIRA NVGPU-686 JIRA NVGPU-644 Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724444 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete unused static variableAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | This variable is never used. So remove it. JIRA NVGPU-525 Change-Id: I7ace77ffe1c2da58d8d9cee3bbbcf8361886bddf Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724094 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cast unsigned arith to signed for abs()Alex Waterman2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | Before passing in an unsigned value to abs() cast the result of the subtraction to signed. In Linux this happens automatically but on non-Linux platforms abs() does not necessarily do this. clang flags this case as a pointless operation: abs(x) obviously must equal x for any unsigned x. This change should hopefully preserve the Linux behavior but avoid the compiler warning from clang. JIRA NVGPU-525 Change-Id: I71320964c0922f1e4890c8b25d801f17e54ed3c0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724093 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove broken force_pramin featureKonsta Holtta2018-05-24
| | | | | | | | | | | | | | The forced PRAMIN reads and writes for sysmem buffers haven't worked in a while since the PRAMIN access code was refactored to work with vidmem-only sgt allocs. This feature was only ever meant for testing and debugging PRAMIN access and early dGPU support, but that is stable enough now so just delete the broken feature instead of fixing it. Change-Id: Ib31dae4550f3b6fea3c426a2e4ad126864bf85d2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723725 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_current_time_ns in submit profilingKonsta Holtta2018-05-24
| | | | | | | | | | | | | Replace Linux-specific and dubious sched_clock() with common nvgpu_current_time_ns(). sched_clock() used also nanoseconds. Jira NVGPU-708 Change-Id: I70f992fe42cc9c3ffed374fdebd582867475e84f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723202 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 09:09:24 -0500