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* gpu: nvgpu: make debugger register access ELPG protectedDeepak Nibade2020-03-16
| | | | | | | | | | | | | | | | | | | | Some of the APIs that access debugger register are not protected from ELPG. This might trigger PRI access timeouts for corresponding registers if GR engine is power gated. Add gr_gk20a_elpg_protected_call() to protect against ELPG. Bug 2820066 Change-Id: I467ea28aaea1c0e36c2d6aabce6a2daea6ee9911 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306383 (cherry picked from commit 0c0eb25ee798db3a8dcd8cab7db06312a220240e) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313210 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: decrease refcount when sync-unmap failsddutta2020-03-05
| | | | | | | | | | | | | | | | | | | | | | | | | When nvgpu_vm_unmap_sync fails, nvgpu_unmap_sync currently bails out without decreasing the buffer refcount. This prevents from releasing the buffer, in case a deferred job completes after the timeout (which was observed 2 times during overnight stress tests). This also means that the fixed address is not re-useable. Throw out a warning when nvgpu_vm_unmap_sync fails, but proceed with decreasing refcount. Bug 200578193 Change-Id: Ie0cc7caa7d12ca0a3b42123a5f7a28bda72dabbc Signed-off-by: ddutta <ddutta@nvidia.com> (cherry picked from commit a433f26d5bb1ec3253fc2655998b1ef7fb2847cb in dev-main) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2291352 Tested-by: Naveen Kumar S <nkumars@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove blcg_enable/disableddutta2020-02-28
| | | | | | | | | | | | | | | | | | blcg is always enabled by default and there is no need for disabling this during gr init or gr reset. Bug 2866010 Change-Id: Iaf17b7fdf05ad04fe435e1a1fda758deedc6484c Signed-off-by: ddutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2303114 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add checks for kzalloc() allocationsNitin Kumbhar2020-02-24
| | | | | | | | | | | | | | | Check kzalloc() allocations for failures and return an error if an allocation fails. Bug 2279948 Change-Id: I8a2c3b84904da897ad6118900c11489c8656c20f Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2020123 (cherry picked from commit fadd0014da39cb9498472494e52590db4b0bd7b9) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298066 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: fix tsg_unbind in recovery casePeter Daifuku2020-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When unbinding a channel from a tsg when virtual, vgpu_tsg_unbind_channel would return an error if unbinding the channel on the guest side failed, and did so before notifying the RM server of the unbind. Later on in the recovery process, the guest OS would remove the channel from the TSG's list, but this would leave the RM server with an out-of-date channel list. Fix this by making the tsg_unbind_channel HAL optional and implemented only for vgpu: the vgpu version now just notifies the RM server so that it can clean up its version of the TSG; if vgpu, always call the tsg_unbind_channel HAL whether or not the local unbind succeeded. Minimal port from dev-main of https://git-master.nvidia.com/r/c/linux-nvgpu/+/2084029 Bug 2766920 Bug 200587845 Change-Id: I75bddf3a28ac20bf4fb7510ff64097a32c7eec3f Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287774 (cherry picked from commit 471c72c1efcc4fe6d547f556edf7773827fd2674) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289928 Reviewed-by: Thomas Steinle <tsteinle@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: added tsg_release for gp10b halaalex2020-02-22
| | | | | | | | | | | | | | | | | tsg_release hal_fn was missing in vgpu_gp10b causing proper cleanup not to happen at the rm-server. Bug 2766920 Bug 200587845 Change-Id: Ic0e57d1d37e0f92eea23087299c8c22c094199b0 Signed-off-by: aalex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1830192 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287773 (cherry picked from commit db765a8b898e1fd74a447081ea5e7de195ad3ce7) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289927 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move cg_enable after pmu_init is completeDebarshi Dutta2020-02-19
| | | | | | | | | | | | | | | | | | This patch help resolve the boot time failures happening with pmu_exterr for porg. cg_enable can race with pmu_init thread, cg_enable is moved post pmu init thread to avoid the above race. Bug 200565050 Change-Id: I2192053eff8767847ea012ca20b3607d2f6cd26f Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2239959 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: add mmu_debug_mode supportAparna Das2020-02-05
| | | | | | | | | | | | | | | | | | Added two new IVC commands that set gr and fb mmu debug mode. Bug 2586624 Change-Id: I358fb04713a9754fb209c0a90d02130dd4a1caf6 Reviewed-on: https://git-master.nvidia.com/r/2204980 (cherry picked from commit db4e5b09891aff075dfffb7cc2fe0630a71ab9a6) Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288347 Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use refcnt for ch mmu_debug_modeThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replaced ch->mmu_debug_mode_enabled with ch->mmu_debug_mode_refcnt. If channel is enabled multiple times by userspace, then ref count is updated accordingly. There is an expectation that enable/disable calls are balanced for setting channel's mmu debug mode. When unbinding the channel, decrease refcnt for the channel until it reaches 0. Also, removed tsg parameter from nvgpu_tsg_set_mmu_debug_mode as it can be retrieved from ch. Bug 2515097 Bug 2713590 Change-Id: If334e374a55bd14ae219edbfd3b1fce5ff25c226 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2184702 (cherry picked from commit f422aee39387a5aa337de69cc21a67f16697ae0e) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208772 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: set FB/HSMMU debug modeThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | Set NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and NV_PFB_PRI_MMU_DEBUG_CTRL in addition to NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL, in NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE Bug 2515097 Bug 2713590 Change-Id: I1763b43e79fac3edb68a35980683d58bfa89519f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115785 (cherry picked from commit 8057514a9f7fc5f175e2e0571dfa91d78ebb6410) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208771 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: accessors for FB/HSSMU MMU_DEBUG_CTRLThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | Add accessors for NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and NV_PFB_PRI_MMU_DEBUG_CTRL Bug 2515097 Bug 2713590 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Change-Id: Ieadee041854bc9a17721b5b17938a106e205517f Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208770 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add refcounting for MMU debug modeThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | GPC MMU debug mode should be set if at least one channel in the TSG has requested it. Add refcounting for MMU debug mode, to make sure debug mode is disabled only when no channel in the TSG is using it. Bug 2515097 Bug 2713590 Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123017 (cherry picked from commit a1248d87fe6e20aab3e5f2e0764f9fe8d80d0552) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208769 Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: enable MMU_DEBUG_MODE for gv11bThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | | NV_PGPC_PRI_MMU_DEBUG_CTRL is now context switched in gv11b FECS ucode. Enable NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, so that userspace can use NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl for gv11b. Bug 2515097 Bug 2713590 Change-Id: Ia9fb36cffc9e67cf96c31c50ffa4c59997258ce2 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115019 (cherry picked from commit 3f9ea7dfd854d748c3d0fae52e2981bae1c8e650) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208768 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctlThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU debug mode for a given context. Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL for a given channel. HAL implementation for native case is gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly writes to the register if the context is resident, or writes to gr context otherwise. Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature. NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode, so the feature is only enabled on TU104 for now. Bug 2515097 But 2713590 Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2110720 (cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767 Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix sched get_params for 0 timeslicePeter Daifuku2020-01-24
| | | | | | | | | | | | | | | | | | | | When the TSG is initialized, the timeslice is initially set to 0, which is a flag for using the default timeslice. The sched get_params ioctl was returning 0 in this case; instead, call gk20a_tsg_get_timeslice() to get the correct value. Bug 2818547 Change-Id: I29fde48240098074de12e9a9a3e347e4042a64e8 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283962 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: avoid double mapping of usermode mmap regionDebarshi Dutta2020-01-24
| | | | | | | | | | | | | | | | | | | | | gk20a_pm_runtime_suspend can fail and invoke gk20a_pm_finalize_poweron that can cause double mapping of the usermode mmap region via io_remap_pfn_range(). Avoid this by using a boolean variable to track whether the region is already mapped. Bug 2707416 Bug 200582208 Change-Id: I4d8cbe427400a5b986348a19af145367cc08ffc6 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2229312 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283801 Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Amulya Yarlagadda <ayarlagadda@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add struct nvgpu_sched_ctrl to gk20aPeter Daifuku2020-01-22
| | | | | | | | | | | | | | | | | Add struct nvgpu_sched_ctrl to struct gk20a Delete struct gk20a_sched_ctrl from struct nvgpu_os_linux Update sched_ctrl functions to use the nvgpu_sched_ctrl struct Bug 200576520 Change-Id: I35b13219e5ef0a8a03333dfd7d46e1d308aec541 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279152 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add fecs flag in poweronJeremy Ho2020-01-17
| | | | | | | | | | | | | | | | | Nvgpu flags will miss fecs when nvgpu poweron. We have to add this fecs in flag when we are seeing trace was initialized before. Bug 2629615 Change-Id: I7815af7bf66a7a103a14cd375a3fd394243035b1 Signed-off-by: Jeremy Ho <jeremyh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279244 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add platform atomic supportsh2020-01-08
| | | | | | | | | | | | | | | | | | | Set platform atomic attribute flag. bug 200580236 Change-Id: I06fd0cf363886922ad5145837004d04e35383470 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2016078 (cherry picked from commit ef5aac37d9a4531fecd1f1dae0581a2bd28f164d) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274970 GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable platform atomic featureVinod G2020-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support following changes related to platform atomic feature NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege, so atomic mode register bits cannot be updated from kernel code. atomic capability and atomic_sys_ncoh_mode bits are copied from fb mmu_ctrl to gpcs_mmu_ctrl register. new tu104 hal for fb_enable_nvlink function. bug 200580236 Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2013481 (cherry picked from commit 251e3eaa8029c4ae07b2cde7af5d9775e1cd8ec1) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274932 GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add platform atomic supportVinod G2020-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | Add new variable in nvgpu_as_map_buffer_ex_args for app to specify the platform atomic support for the page. When platform atomic attribute flag is set, pte memory aperture is set to be coherent type. renamed nvgpu_aperture_mask_coh -> nvgpu_aperture_mask_raw function. bug 200580236 Change-Id: I18266724dafdc8dfd96a0711f23cf08e23682afc Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012679 (cherry picked from commit 9e0a9004b71f92b7713fd3b30141b0d9d4cfa2c6) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274914 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: re-enable elpg after golden img initPeter Daifuku2019-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typically, the PMU init thread will finish up long before the golden context image has been initialized, which means that ELPG hasn't truly been enabled at that point. Create a new function, nvgpu_pmu_reenable_pg(), which checks if elpg had been enabled (non-zero refcnt), and if so, disables then re-enables it. Call this function from gk20a_alloc_obj_ctx() after the golden context image has been initialized to ensure that elpg is truly enabled. Manually ported from dev-main Bug 200543218 Change-Id: I0e7c4f64434c5e356829581950edce61cc88882a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2245768 (cherry picked from commit 077b6712b5a40340ece818416002ac8431dc4138) Reviewed-on: https://git-master.nvidia.com/r/2250091 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gk20a_busy_noresume and gk20a_idle_nosuspendDebarshi Dutta2019-11-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gk20a_idle can still race with gk20a_busy_noresume as the following pm_runtime's functions can run concurrently. i.e. pm_runtime_suspend and pm_runtime_get_noresume. pm_runtime_get_noresume simply increments the refcount without first acquiring the pm_runtime's power_lock. This can be resolved by the use of pm_runtime_get_if_in_use which acquires a the power lock of PM runtime. This prevents a potential use of register after power_off in the l2_ops ioctl path. We still call pm_runtime_get_noresume even if pm_runtime_get_if_in_use returns <= 0. This helps in the following ways. 1) The signature of the function gk20a_busy_noresume remains same w.r.t QNX code 2) Any calls to gk20a_busy_noresume() in the driver is followed by a check to g->power_on. When pm_runtime_get_if_in_use() returns <=0, g->power_on is false and would immediately call gk20a_suspend_noidle() thus keeping the original 'intent' of the gk20a_busy_noresume intact. Bug 200507468 Change-Id: Id46bf2124047bb0e9a299fda57441e425195468f Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180787 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set CE prod valuesDeepak Nibade2019-11-04
| | | | | | | | | | | | | | | | | | | | | Add g->ops.ce.init_prod_values() hal for gv11b to initialize PROD values of CE unit Bug 2526212 Chery-pick/manual port from dev-main Change-Id: I8e516b292622e09c537feb7830392648116baa7c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2150874 (cherry picked from commit 0e6a305c6af3ea6d9a0cad7b4071f68028a1aebe) Reviewed-on: https://git-master.nvidia.com/r/2224709 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add clock gating support for HSHUBDeepak Nibade2019-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add BLCG and SLCG clock gating support for HSHUB unit on gv11b Register list for BLCG and SLCG is auto generated with scripts. Add HAL operations to enable/disable HSHUB clock gating Re-generate gv11b reglist so that all the manually commented registers are automatically deleted. Some of the unicast registers are also deleted. We already have corresponding broadcast registers present. Cherry-pick/manually port from dev-main Bug 2526212 Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2150199 (cherry picked from commit e34b6f76d38ad5641c1ed7c3a4b36752d9dd4750) Reviewed-on: https://git-master.nvidia.com/r/2224708 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable PG189 dGPUThomas Fleury2019-10-28
| | | | | | | | | | | | | | | | | | PG189 is not supported on rel-32. Remove related device ids from nvgpu list of supported devices. Bug 2732086 Change-Id: I800251a864357daab87769ec33a1e7268a2f7b57 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2222547 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: fix railgate_enable_storeLeon Yu2019-10-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing same value to railgate_enable_store should be treated as nop and made successfully. Doing so is not only an optimization for the operation but also convention that users expect for "settings". This change is primary for fixing a peculiar situation in the driver: root@localhost:/sys/devices/17000000.gp10b# cat railgate_enable 0 root@localhost:/sys/devices/17000000.gp10b# echo 0 > railgate_enable bash: echo: write error: Invalid argument Attempt to disable railgating on a platform where railgating isn't supported shouldn't be treated as 'invalid'. It's disabled after all. Bug 200562094 Change-Id: I3c04934bdbaf337c33d7de9cac6d53c96b4dacae Signed-off-by: Leon Yu <leoyu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2225476 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: vgpu: no debugfs entries that rely on PMUPeter Daifuku2019-10-14
| | | | | | | | | | | | | | | | | | | When virtualized, the guest OS has no direct access to PMU functionality so don't create debugfs entries that rely on PMU access Bug 200543218 Change-Id: I12730b600802448a240f3de042760041d3ae7d29 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2213650 (cherry picked from commit 053131ef44252748aecaad11ba8dc54f1dc40fce) Reviewed-on: https://git-master.nvidia.com/r/2215162 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: channel_setup_bind: must be bound to TSGPeter Daifuku2019-10-14
| | | | | | | | | | | | | | | | | In nvgpu_channel_setup_bind, return an error if the channel isn't bound to a TSG, as future operations rely on being bound. Bug 200543218 Change-Id: If33b01b8176c7488445c23080ad9d11f341bff43 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2215160 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: fix get_maxrate when no dvfsPeter Daifuku2019-10-14
| | | | | | | | | | | | | | | | | | In nvgpu_linux_get_maxrate, if tegra_dvfs_get_maxrate returns 0 (a sign that there is no dvfs support), call nvgpu_clk_arb_get_arbiter_clk_range to get the max gpu frequency. Bug 200543218 Change-Id: I4f9bc0acaef98cd9dfa22f709656f4bb7e9fd349 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2215161 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix NVGPU_COND_WAIT_INTERRUPTIBLEThomas Fleury2019-10-11
| | | | | | | | | | | | | | | | | | | | | | | | When called with timeout=0, NVGPU_COND_WAIT_INTERRUPTIBLE macro ignores the return code from wait_event_interruptible. As a result we do not detect when the call is interrupted, and the calling process hangs. Use wait_event_interruptible return code in case of infinite timeout. Bug 200384829 Bug 200543218 Change-Id: I930f0d08c73a3b91ab20a6c8faaf633a3d7aee4d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1982242 (cherry picked from commit 78c513790ac64605cea673c26e6d0d71c3d8db0a) Reviewed-on: https://git-master.nvidia.com/r/2215159 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix PMU destroy sequenceAbhiroop Kaginalkar2019-09-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A call to exit the PMU state machine/kthread must be prioritized over any other state change. It was possible to set the state as PMU_STATE_EXIT, signal the kthread and overwrite the state before the kthread has had the chance to exit its loop. This may lead to a "lost" signal, resulting in indefinite wait during the destroy sequence. Faulting sequence: 1. pmu_state = PMU_STATE_EXIT in nvgpu_pmu_destroy() 2. cond_signal() 3. pmu_state = PMU_STATE_LOADING_PG_BUF 4. PMU kthread wakes up 5. PMU kthread processes PMU_STATE_LOADING_PG_BUF 6. PMU kthread sleeps 7. nvgpu_pmu_destroy() waits indefinitely This patch adds a sticky flag to indicate PMU_STATE_EXIT, irrespective of any subsequent changes to pmu_state. The PMU PG init kthread may wait on a call to NVGPU_COND_WAIT_INTERRUPTIBLE, which requires a corresponding call to nvgpu_cond_signal_interruptible() as the core kernel code requires this task mask to wake-up an interruptible task. Bug 2658750 Bug 200532122 Change-Id: I61beae80673486f83bf60c703a8af88b066a1c36 Signed-off-by: Abhiroop Kaginalkar <akaginalkar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2177112 (cherry picked from commit afa49fb073a324c49a820e142aaaf80e4656dcc6) Reviewed-on: https://git-master.nvidia.com/r/2190733 Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu memtest: put memory ref countBruce Xu2019-09-12
| | | | | | | | | | | | | | | | | after check failed, need release memory reference Bug 200531152 Change-Id: I6bfad867eb9bd636a48b5ceb3a4417a80994a3ec Signed-off-by: Bruce Xu <brucex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2194025 (cherry picked from commit f85504ae46d65d5346d9e2a5cc84ffb960ba9fb7) Reviewed-on: https://git-master.nvidia.com/r/2195437 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix trace ring read after invalid entryDeepak Nibade2019-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gk20a_fecs_trace_poll() right now calls gk20a_fecs_trace_ring_read() to read the trace ring buffer written by FECS gk20a_fecs_trace_ring_read() returns number of trace entries written to local buffer if successful, otherwise returns error In case there is really an invalid entry, gk20a_fecs_trace_poll() will just stop reading more entries, write current read pointer to h/w and return When gk20a_fecs_trace_poll() is called next time, we again read that invalid entry, and again skip it, and again return This keeps happening, and we never move on to read new entries Fix this by always continuing to read next entry irrespective of current entry is valid or not gk20a_fecs_trace_poll() now just prints a debug message instead of breaking the loop Bug 200491708 Bug 200542611 Reviewed-on: https://git-master.nvidia.com/r/2020167 (cherry picked from commit decbbf35041e7e551b3f354e582daaa5c8c3cc0a) Change-Id: If8b3c8af63ce662a41ada93a6986fa149e34f664 Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2190151 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix enable/disable fecs traceseshendra2019-09-06
| | | | | | | | | | | | | | | | | | | | | | - This patch fixes enable/disable fecs trace logic. - Added enable_lock and enable_count to handle multiple enable/disable of fecs trace logic. - If user does trace disable twice, enable_count will become negative and when user tries to re-enable it, fecs trace will not be enabled. Bug 2672760 Bug 200542611 Change-Id: Ic7d4883b899f01dcf43058d0e7c9d1223a716c9b Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2189371 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Enabling/disabling FECS trace supportseshendra2019-09-06
| | | | | | | | | | | | | | | | | | | - To enable FECS trace support, nvgpu should set the MSB of the read pointer (MAILBOX1). - The ucode will check if the feature is enabled/disabled before writing a record into the circular buffer. If the feature is disabled, it will not write the record. - If the feature is enabled and the buffer is not allocated, HW will throw a page fault error. Bug 2459186 Bug 200542611 Change-Id: I6f181643737d1cf1bda02077eaa714a3f4ef3d8c Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2189250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: Fix the race between runtime PM and L2 flush"Debarshi Dutta2019-09-05
| | | | | | | | | | | | | | | This patch results in a flaw that doesn't clear the GPU cache. This reverts commit 47f6bc0c2e85d0a8ff943b88c81108ca1bfc588e. Bug 2687410 Change-Id: If78bd7ca29eb5621d4369cbddf21320e2a77a41a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2186886 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct handling of pbdma rcDebarshi Dutta2019-09-04
| | | | | | | | | | | | | | | | | | | | | | | The current code reads the pbdma_status info after clearing the interrupt. Other interrupts/sleep can cause enough delay between clearing the interrupt and pbdma switching the channel leading to invalid channel/tsg ID. Correct that by reading the pbdma_status info register before clearing of the pbdma interrupt to correctly read the context information before the pbdma can switch out the context. Bug 200533450 Change-Id: Ic2f0682526e00d14ad58f0411472f34388183f2b Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2165047 (cherry-picked from 0ef96e4b1a7979d2bae0e52924e976515cb87400 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2188861 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for XPU rail splitDebarshi Dutta2019-09-04
| | | | | | | | | | | | | | | | | | | | | | Check if CPU/GPU rails are joint, disable railgating if they are. Add the DT support for T194 and T186 platforms. Disable railgate_enable sysfs node update in the above condition. Bug 200546450 Bug 200545711 Change-Id: I002488f6418805569b0ef0fc3032b58297adeafb Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2185221 Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Tested-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: don't report max load when counter overflowLeon Yu2019-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is to prevent GPU (and thus EMC) frequency from being boosted from time to time when system is completely idle. It's caused by max GPU load being incorrectly reported by perfmon. When the issue happens, it can be observed that max load is reported but busy_cycles read from PMU is actually zero. Even though busy and total cycles returned by PMU may not be completely accurate when counter overflows, the counters accumulated so far still have some value that we shouldn't ignore. OTOH, returning max load could be the least accurate approximation in such cases. So let's just clear the interrupt status and let rest of the code handle the exception cases. Bug 200545546 Change-Id: I6882ae265029e881f5417fb2b82005b0112b0fda Signed-off-by: Leon Yu <leoyu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180771 Reviewed-by: Peng Liu <pengliu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mubushir Rahman <mubushirr@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use vpr resize APIVedashree Vidwans2019-08-30
| | | | | | | | | | | | | | | | | | | | This patch adds nvgpu API in linux and qnx to query vpr resize. The new API nvgpu_is_vpr_resize_enabled() is used in nvgpu_submit_channel_gpfifo(). Previously, if non-deterministic channel has timeout disabled and GPU cannot railgate on some platform, then channel doesn't power ref count and results in video freeze. This requires non-determinstic channel job tracking to be enabled if vpr resize is supported or if GPU can railgate. Bug 200532122 Change-Id: Icfbff6253762b195b2f5955749343974b1a7a269 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2167082 Reviewed-on: https://git-master.nvidia.com/r/2180581 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix race for channel sync read/writeVedashree Vidwans2019-08-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CTS test dEQP-VK.api.object_management.max_concurrent.device_group crashes with invalid userspace memory access. Currently, nvgpu_submit_prepare_syncs() races with gk20a_channel_clean_up_jobs() and this race condition is exposed when aggressive_sync_destroy_thresh is set to non-zero value. nvgpu_submit_prepare_syncs() gets ref for c->sync to submit job and releases channel sync_lock immediately. Meanwhile, gk20a_channel_worker_process() triggers gk20a_channel_clean_up_jobs(), which destroys ref'd c->sync pointer. Channel sync is deleted by gk20a_channel_clean_up_jobs() only if aggressive_sync_destroy_thresh is non-zero. So, gk20a_channel_clean_up_jobs() and nvgpu_submit_prepare_syncs() will race only in this scenario. Hence, if aggressive_sync_destroy_thresh value is non-zero, this patch protects channel's sync pointer by holding channel sync_lock during complete execution of nvgpu_submit_prepare_syncs(). Bug 2613870 Change-Id: I6f3d48aff361d1cb38c30d2ce5de276d0c55fb6f Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180550 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: support usermode submitKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | Use usermode_base HAL from gv11b and turn on NVGPU_SUPPORT_USERMODE_SUBMIT for gv100. Bug 200145225 Bug 200541476 Change-Id: I9f60a1fb07ae19ee9e0de9e28d56789fe282907f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1924509 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit a39d91b591d79827fc315218393b03365cc6e502 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170622 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mark usermode submit supported for gv11bKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | Mark usermode submit supported in gv11b and add the characteristics flag to expose the capability to userspace. Bug 200145225 Bug 200541476 Change-Id: Id9dcb0c71c020bd509fbdbffb94a756c69377f20 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795822 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 37659f5c8e0571655178c50a6296b68e3ebdc4cb in rel-32) Reviewed-on: https://git-master.nvidia.com/r/2170604 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support usermode submit buffersKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import userd and gpfifo buffers from userspace if provided via NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token (i.e., the hw channel id) to userspace. To keep the buffers alive, store their dmabuf and attachment/sgt handles in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for buffers that are mainly in kernel use. The buffers are freed via a new API in the os_channel interface. Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the usermode gpfifo buffer. Bug 200145225 Bug 200541476 Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795821 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 99b1c6dcdf328efcfe47338ad1b71a114ab7f272 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170603 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add FOREIGN_SGT mem flagKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | Add an internal flag NVGPU_MEM_FLAG_FOREIGN_SGT to specify that the sgt member of an nvgpu_mem must not be freed when the nvgpu_mem is freed. Bug 200145225 Bug 200541476 Change-Id: I044fb91a5f9d148f38fb0cbf63d0cdfd64a070ce Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1819801 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 9de6d20abb8fef0cd11c22676846d809ee3f9afc in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170602 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: provide usermode region via mmapKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | Add a mmap callback on the control device node for mapping the usermode register region to userspace. Each such mapping is removed when the GPU railgates, and brought back again on unrailgate. The mapping offset must be 0 and its size must be 4 KB. Bug 200145225 Bug 200541476 Change-Id: Ie8d3758da745b958376292691d7d1d02a24e7815 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795819 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit f33935f426c46b70b7aee33a1e52d5fdae5ca376 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170035 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: track opened Linux ctrl filesKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | An upcoming patch will need to enumerate opened ctrl nodes; track them in a list, protected by a mutex. Bug 200145225 Bug 200541476 Change-Id: I50dc15056832a3bb53fbdd7bd2bffcdaecc7b21c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811840 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit d53495400e15fdef80be2f04a9f2312b81d2bd6d in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170005 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add usermode_base HALKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | Add a HAL function pointer to fifo to for reading the usermode_cfg0 register and implement it for gv11b. Bug 200145225 Bug 200541476 Change-Id: I5f77b15d3b502d9370b1f14129314eaf51a9d7d1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811839 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit fddb2969240652e1a56089b249684b55430d45c5 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170004 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: store bus addr of gpu regsKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | Usermode submit needs to access the usermode region of registers from userspace. Store the start address of register resource in struct nvgpu_os_linux to be used in remap to userspace. Bug 200145225 Bug 200541476 Change-Id: I3796b6bf67942af0cc16c86accb82a013032bfc8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811838 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 38c11db264f776fa495a3ba74caadf4262062b78 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2169921 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:43:52 -0500