| Commit message (Collapse) | Author | Age |
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NVGPU_DBG_GPU_IOCTL_PC_SAMPLING ioctl is not handled properly for HV
case for both Linux and QNX. Currently guest vm is trying to perform
gpu memory read and write operations which supposed to be done by RM
server, causing the crash. This patch is supposed to fix ioctl failure.
Bug 2052040
Change-Id: Ia0773959b84739a1bced858331764751520a3561
Signed-off-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708102
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Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Currently gpu sysfs retrieves Fmax@Vmin by direct call into Tegra DVFS
driver that introduces compile time dependencies on CONFIG_TEGRA_DVFS.
In addition incorrect clock is used for DVFS information access.
Re-factored sysfs node to use generic GPU clock operation for Fmax@Vmin
read. This would fix a bug in target clock selection, and allows to
remove dependency of sysfs on CONFIG_TEGRA_DVFS.
Updated nvgpu_linux_get_fmax_at_vmin_safe operation itself so it can be
called on platforms that does not support Tegra DVFS, although 0 will
still be returned as Fmax@Vmin on such platforms.
Bug 2045903
Change-Id: I32cce25320df026288c82458c913b0cde9ad4f72
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1710924
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This will make it easier to stage the make build of userspace nvgpu
through module branching. Otherwise we will have a nightmare of
integration with almost certain dev-kernel lockdowns.
As functions get unit tested they should be added to the exports
file.
Change-Id: I7833fa0895c44282ec6a690dc5de43e01336292a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1711314
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Read GP_GET and GET from hardware every time when the poll timer expires
instead of when the watchdog timer expires. Restart the watchdog timer
if the get pointers have increased since the previous read. This way
stuck channels are detected quicker.
Previously it could have taken at most twice the watchdog timeout limit
for a stuck channel to get recovered; with this change, a coarse sliding
window is used. The polling period is still 100 ms.
The difference is illustrated in the following diagram:
time 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
get a b b b b b b b b b b b b b b b b b b b b
prev - n n n n n n n n n A n n n n n n n n n S
next - A s s s s s s s s s S
"time" represents wall time in polling units; 0 is submit time. For
simplicity, watchdog timeout is ten units. "get" is the GP_GET that
advances a little from a and then gets stuck at b. "prev" is the
previous behaviour, "next" is after this patch. "A" is when the channel
is detected as advanced, and "S" when it's found stuck and recovered;
small "s" is when it's found stuck but when the time limit has not yet
expired and "n" is when the hw state is not read.
Bug 1700277
Bug 1982826
Change-Id: Ie2921920d5396cee652729c6a7162b740d7a1f06
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1710554
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The pmc access has to be through pmc driver. This prevents the direct access
to pmc registers and supports onlt tz access to it in t210 platforms.
Bug 1811649
Change-Id: I235768a07fa93ce4cced656aade160bbd853be62
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704315
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Dump fecs method data and adr if ucode times out or
errors out. This is good to have for debugging.
Change-Id: I79c4bc3bc30cfd09f273f4eb6b53863653227ecd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1707761
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We don't need to configure mc_enable_pb_r() register in any of the supported
chips, so remove access to this register
Jira NVGPUT-52
Change-Id: I8a7a524367ce7953f926143242c6d63bc8fd5ed1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1711245
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Replaced all instances of sync_fence in gk20a_fence* code with
nvgpu_os_fence. Added the API install_fence for the nvgpu_os_fence
abstraction. sync_fence mechanism and its dependencies are completely
removed from the fence_gk20a methods. Due to the recent os_fence changes
and the changes to fence_gk20a, we can finally get rid of all the CONFIG_SYNCS
present in the submit path.
JIRA NVGPU-66
Change-Id: I3551dab04b93b1e94db83fc102a41872be89e9ed
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1701245
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This patch adapts gk20a_channel_syncpt to use os_fence for post fence
as well as pre-fence(wait) use cases.
Jira NVGPU-66
Change-Id: I49627d1f88d52a53511a02f5de60fed6df8350de
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676631
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This patch constructs an abstraction to hide the sync_fence
functionality from the common code. struct nvgpu_os_fence acts as an
abstraction for struct sync_fence.
struct nvgpu_os_fence consists of an ops structure named nvgpu_os_fence_ops
which contains an API to do pushbuffer programming to generate wait
commands for the fence.
The current implementation of nvgpu only allows for wait method on a
sync_fence which was generated using a similar backend(i.e. either
Nvhost Syncpoints or Semaphores). In this patch, a
generic API is introduced which will decide the type of the underlying
implementation of the struct nvgpu_os_fence at runtime and run the
corresponding wait implementation on it.
This patch changes the channel_sync_gk20a's semaphore specific
implementation to use the abstract API. A subsequent patch will make
the changes for the nvhost_syncpoint based implementations as well.
JIRA NVGPU-66
Change-Id: If6675bfde5885c3d15d2ca380bb6c7c0e240e734
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667218
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We so far do not support unbinding a channel from TSG explicitly through IOCTL
Channel is unbound from TSG when channel fd is closed
But this could create issue in case process is forked and fd is duplicated
In worst case it is possible that duplicate fd is closed sometime later when
TSG is active and that could lead to corruption of TSG state
Fix this by implementing NVGPU_TSG_IOCTL_UNBIND_CHANNEL API
This API will simply call gk20a_tsg_unbind_channel() API to unbind the
channel
Note that we also mark the channel has_timedout since unbound channel does
not have any context of its own and it cannot serve any job
Remove call to gk20a_disable_channel() while closing the channel.
We do not support bare channels without TSG, and if channel is not part of TSG
then it means channel is already unbound from TSG with call to
NVGPU_TSG_IOCTL_UNBIND_CHANNEL, and there is nothing to do while closing the
channel
Bug 200327095
Jira NVGPU-229
Change-Id: Ib7f6710f0dc8125caafabe7bee737622c3dd9fa3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708902
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Clean up redundand function declarations in vgpu.h
JIRA ESRM-299
Change-Id: I9b3a2aee6be68dffce47897baed2e7b9290026e9
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1710885
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Split sim initialization to two parts,
first part gets invoked as part of probe and
second part gets invoked in the finalize_poweron
after the hal has been initialized.
This is done because some of the sim init
code uses mm api's which are assigned as
part of hal init.
replaced sim buffer allocation api's
with nvgpu_dma_sys_alloc.
Change-Id: Ib019fbb747bdf6dcc74e7deba732ab41f0869e96
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705424
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Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
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added a os-agnostic sim.h header which could be
included in by any platform, moved out os specific
headers to nvgpu/linux.
JIRA VQRM-2368
Change-Id: I3861bfa75a6b8d2d909bc7223467fd68c208275b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702816
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segregated os-agnostic function from linux/sim.c and linux/sim_pci.c
to sim.c and sim_pci.c, while retaining os-specific functions.
renamed all gk20a_* api's to nvgpu_*.
renamed hw_sim_gk20a.h to nvgpu/hw_sim.h
moved hw_sim_pci.h to nvgpu/hw_sim_pci.h
JIRA VQRM-2368
Change-Id: I040a6b12b19111a0b99280245808ea2b0f344cdd
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702425
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moved sim buffer(send, recv and msg) from
os-specific structure to OS agnostic structure.
JIRA VQRM-2368
Change-Id: I10ff23fe24d86f2bd372f1bae0369cc45aadfb80
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702178
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refactored sim_readl and sim_writel to use
os-agnostic structures.
converted all sim buffers to the type nvgpu_mem and
replaced all alloc_page and free_page calls with
corresponding nvgpu_dma_alloc/nvgpu_dma_free calls.
JIRA VQRM-2368
Change-Id: Ia9d29119d31f239ed16be932cfd16c334002c727
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702050
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Move nvlink endpoint operations to common code. These operations
are invoked when handling nvlink core driver requests.
Jira VQRM-3523
Change-Id: I93024bf88a8caa3765b33c1264dde452c1a85ee3
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698686
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PMU ucode is updated to include LDIV slowdown factor in gr_init_param command.
- Defined a new version gr_init_param_v2.
- Updated the PMU FW version code.
- Set the LDIV slowdown factor to 0x1e by default.
- Added sysfs entry to program ldiv_slowdown factor at runtime.
Bug 200391931
Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
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set_user_nice is no longer needed to improve the efficiency of
gk20a_finalize_poweron and can be removed as suggested by Terje.
Change-Id: I303bbee266b4624bb775ea793f843dbfc8f88c5d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1692609
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Get host1x node reference from c1_rp device tree node, and
enable syncpoints shim in case of nvlink.
JIRA EVLR-2441
JIRA EVLR-2585
Change-Id: Idbf1edf656557f2ed2d3bd27393c2f4d5d1ad75a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts
We already handle nonstall interrupts in nvgpu_intr_nonstall()
But this API is completely in linux specific code
Separate out os-independent code to handle nonstall interrupts in new API
mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all
existing chips
Call this HAL from nvgpu_intr_nonstall()
Jira NVGPUT-8
Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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Implement a worker thread to replace the workqueue based
handling for clk arbiter update callbacks.
The work items scheduled with the thread are of two types,
update_vf_table and arb_update. Previously, there were two
workqueues for handling these two work struct's separately.
Now the single worker thread would process these two events.
If a work item of a particular type is scheduled to be run
on the worker, another instance of same type won't be
scheduled, which mirrors the linux workqueue behavior.
This also removes dependency on linux workqueues/work struct
and makes code portable to be used by QNX also.
Jira VQRM-3741
Change-Id: Ic27ce718c62c7d7c3f8820fbd1db386a159e28f2
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
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clk arbiter code uses linux kernel specific 'list' handling.
Use 'nvgpu_list' data structure and constructs instead.
Also, remove other linux includes from clk_arb.c, while at it.
Jira VQRM-3741
Change-Id: I89bf73a62537447dc23726a43e1f6ad96589ae34
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705962
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RCU's are available only in (linux) kernel. Though they are
able to achieve lockless access in some specific scenarios,
they are heavily dependent on the kernel for their functionality.
E.g. synchronize_rcu(), which depends on the kernel in order to
delimit read side critical sections.
As such it is very difficult to implement constructs analogous
to RCUs in userspace code. As a result the code which depends on
RCU's for synchronization is not portable between OS'es,
especially if one of them is in userspace, viz. QNX.
Also, if the code is not in performance critical path, we can do
with non-RCU constructs.
For clk arbiter code here, RCU's are replaced by the traditional
spinlocks, so that the code could be used by QNX down the line.
Jira VQRM-3741
Change-Id: I178e5958788c8fd998303a6a94d8f2f328201508
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705535
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In order to enable the movement of clk arbitrator to common
code, we need to remove the linux specific POLL* defines
and instead use NVGPU defines. Add a conversion function
for the same.
Also remove debugfs include, while at it.
Jira VQRM-3741
Change-Id: I3c367625f9fa5fb8480d01bdaf6233df8cc2c722
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704885
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In order to enable the movement of clk arbitrator to common
code, we need to remove the NVGPU_GPU_EVENT_* defines (which
are present in uapi) and instead use the common code defines.
Add a conversion function for the same.
With this the uapi header is no longer required to be included
inside clk_arb.c
Jira VQRM-3741
Change-Id: If01614b01733876046f98b97e70285c52bc33e45
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699241
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Clk arbiter uses the legacy gk20a_dbg_fn logging APIs.
Use nvgpu logging instead, while also defining a new
log mask for clk arbiter.
Jira VQRM-3741
Change-Id: I86feb4fa434b404705cc3fba1e854180d4df508d
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1707394
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Add support for compiling nvgpu in a POSIX compliant userspace.
This code adds all of the necessary abstraction interfaces (mostly
stubbed) to enabled extremely limited and basic functionality in
nvgpu.
The goal of this code is to facilitate unit testing of the nvgpu
common core. By doing this in userspace it is much easier to write
tests that rely on very particular states within nvgpu since a user
can very precisely control the state of nvgpu.
JIRA NVGPU-525
Change-Id: I30e95016df14997d951075777e0585f912dc5960
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683914
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Mostly just including necessary includes to make sure that
global function declarations actually match their implementations.
Also work around pointer munging warning:
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c: In function 'nvgpu_pmu_process_init_msg':
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c:348:4: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing]
(*(u32 *)gid_data.signature == PMU_SHA1_GID_SIGNATURE);
Work around this warning by simply moving the type punning.
This code is certainly dangerous - it assumes the endianness
of the header data is the same as the machine this code is
running on. Apparently it works, though, so this ignores
the warning.
JIRA NVGPU-525
Change-Id: Id704bae7805440bebfad51c8c8365e6d2b7a39eb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1692454
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/1702217
- APP_VERSION_GP10X 23913597 to 24008084
- nvgpu clk_vin interface as per chips_a_23609936 CL
https://git-master.nvidia.com/r/#/c/1687591/
p4 CL # 24069912
Bug 200399373
Change-Id: If16566aaf42dfc2460d426f18927eab08309dfcf
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702218
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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clk_vin data structures updated as new calibration type (v20) is added.
GP106 header does not have vin calibration type.
Assuming V10 if calibration type is not V20.
Add fuse calibration for V20 type.
Bug 200399373
Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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mmu fault information for client and gpc differ
on various chip. Add separate table for each chip
based on that change and add hal functions to access
those descriptors.
bug 2050564
Change-Id: If15a4757762569d60d4ce1a6a47b8c9a93c11cb0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704105
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Set rpc buffer to 0xFF instead of 0x0 to handle fucntions with rpc id 0
Change-Id: Ife692d9fd19008e225975e41bb13e53522283a54
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702133
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Add Nvdclk domain as a valid vbios domain for GV100
Change-Id: Ib65d880b26c279018bbf7d2faa304084f9ce4b1a
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702121
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- Made change to pass correct VOLT RPC param to get
voltage request.
- Change VOLT_SET_VOLTAGE request to blocking call
to make sure, set voltage request completes in
PMU & ACK's
- Created rail count define for pascal & volta then
made changes to use define as needed.
Change-Id: I2662fadbe32b82585711f2568c4f800162899206
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1693402
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Added sw method for NVC397_SET_SHADER_CUT_COLLECTOR
to enable/disable SHADER_CUT_COLLECTOR_STATE.
Added support for this sw method in gv11b and gv100.
Bug 2108381
Change-Id: Ief2c2bf5d9c99779dad3b1243041c5efe56287d3
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703662
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Add below rc_types to be passed to gk20a_fifo_recover
MMU_FAULT
PBDMA_FAULT
GR_FAULT
PREEMPT_TIMEOUT
CTXSW_TIMEOUT
RUNLIST_UPDATE_TIMEOUT
FORCE_RESET
SCHED_ERR
This is nice to have to know what triggered recovery.
Bug 2065990
Change-Id: I202268c5f237be2180b438e8ba027fce684967b6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Rename mutex to runlist_lock in fifo_runlist_info_gk20a
struct. This is good to have for code readability.
Bug 2065990
Bug 2043838
Change-Id: I716685e3fad538458181d2a9fe592410401862b9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Currently gv100 is using very large timeout for polling
eng preempt done. This will prevent eng preempt polling
loop from timing out. Also before eng preempt loop times
out, there could be channel timeout getting kicked in.
Avoid this by using gr_idle_timeout defined by driver.
Change-Id: Icff5ae37f95f58f3195b9d630bdae42c08ced9a6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1701059
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The return value from NVGPU_COND_WAIT_INTERRUPTIBLE in
channel poll worker is wrongly compared with 0 and the
boolean result is assigned to ret value used subsequently.
Instead, the direct return value from
NVGPU_COND_WAIT_INTERRUPTIBLE should be used.
This bug seems remnant of the following patch which moved
the handling from 'wait_event_timeout' to 'NVGPU_COND_WAIT'.
commit 301965fb77b3dc97445957712b82ce430eaa17e3
gpu: nvgpu: Use nvgpu_cond in channel worker
Change-Id: Id48e197756a6855b35a9ee0dc26d014b62ed3860
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705976
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Necessary in order for QNX to avoid setting __NVGPU_POSIX__ globally.
Change-Id: I020609c28766951269371358bae71b0fb4de7803
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703386
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fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug
Bug 2093809
Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Bug 2102373
Change-Id: I13a5faa18cf26233eb04ac08d2b8755aeb56ae4b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1696890
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- total DMA memory allocation is currently tracked by adding page aligned
size of nvgpu_mem
- The sequence is roughly as follows:
- total dma memory used += mem->aligned_size
- mem->aligned_size = PAGE_ALIGN(size)
- In above sequence, nvgpu_mem structure is initially zero when it is added
to total dma memory used after which it is assigned page aligned value
- This patch fixes total dma memory usage tracking.
Change-Id: Ibb879c8d38ae9077c3d198d9bb008a72e9208b4d
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1685312
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Add new HAL gops.fifo.ring_channel_doorbell() to update channel doorbell
register and to trigger a runlist scan
Set existing API gv11b_ring_channel_doorbell() to this HAL for all volta chips
Jira NVGPUT-18
Change-Id: I9d5e84cf5aa7b763363d84befe169efda00a0932
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702114
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sim pointer is not init for non simulation
platforms.
Change-Id: Ia30e66efbb009293b4e1151c2f1e4ac5d08c3d78
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1701681
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Clk arbiter code contains two significant portions -
the one which interacts with userspace and is OS specific,
and the other which does the heavylifting work which can
be moved to the common OS agnostic code.
Split the code into two files in prep towards refactoring
the clk arbiter.
Jira VQRM-3741
Change-Id: I47e2c5b18d86949d02d6963c69c2e2ad161626f7
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
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ETIME does not exist on integrity.
Jira VQRM-2344
Change-Id: I4c9642c5ccf6d5d7ada456716589461b27b72c99
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699843
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