| Commit message (Collapse) | Author | Age |
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Add function pointer to add chip specific commit_inst.
Update this function pointer for gk20a and gm20b.
JIRA GV11B-21
Change-Id: Iae7231fae70c7b4f56647fe242776670675de3fd
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1258275
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add IOCTL API NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
to read/write fb/vidmem memory
Interface will accept dmabuf_fd of the buffer in vidmem,
offset into the buffer to access, temporary buffer
to copy data across API, size of read/write and
command indicating either read or write operation
API will first parse all the inputs, and then call
gk20a_vidbuf_access_memory() to complete fb access
gk20a_vidbuf_access_memory() will then just use
gk20a_mem_rd_n() or gk20a_mem_wr_n() depending
on the command issued
Bug 1804714
Jira DNVGPU-192
Change-Id: Iba3c42410abe12c2884d3b603fa33d27782e4c56
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1255556
(cherry picked from commit 2c49a8a79d93fc526adbf6f808484fa9a3fa2498)
Reviewed-on: http://git-master/r/1260471
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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gm20b_init_gr does not inherit the ops set by gk20a_init_gr_ops, and the
gr.setup_rop_mapping HAL was not set there, so it was not set for chips
that inherit from gm20b_init_gr and do not override it explicitly.
Set the pointer in gm20b_init_gr, which other chips inherit, and delete
the surrounding if condition from the call, making sure that future
users always call it, because there is an implementation since the
earliest supported chip.
Bug 1833382
Change-Id: I7893c9aac7c5c49ce9a55031ea6baa9382a1b7ca
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1258960
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Change-Id: I354d4bbddb2aba2a1a668cc0401437f1e2403b79
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1259495
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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gk20a/gm20b do not have an fbpa unit, although the
hw header files claim they do. Hardcode all fbpa
values to 0.
Bug 200249125
Change-Id: I4afb29795199552979247de7c76b6b55ea4f368f
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1256420
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add function pointer to add chip specific init_inst_block.
Update this function pointer for gk20a and gm20b.
JIRA GV11B-21
Change-Id: I74ca6a8b4d5d1ed36f7b25b7f62361c2789b9540
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254875
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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During gk20a_remove_gr_support, free veid bundle
init data.
JIRA GV11B-21
Change-Id: Ie1ea7387202c0bae55d5e5f0e1827b5b7b826e96
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254869
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This change fixes error handling logic in
gk20a_alloc_channel_gpfifo(). In cases, where we don't
allocate a channel_sync at gpfifo allocation time,
we shouldn't attempt to destroy it while handling
an error.
Bug 200253447
Change-Id: I57a78c74bbce84fa17fb0360c59b8f413a9124a7
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1255858
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add FBPA broadcast support to hwpm regops
Bug 200249125
Change-Id: Iaf413a162a8985bcce94ff96ec6318e129609c4c
Signed-off-by: Tejaswi K <tk@nvidia.com>
Reviewed-on: http://git-master/r/1247408
(cherry picked from commit 4e0a805f5a8762d1a90f3b5dd76902a04941d9ef)
Reviewed-on: http://git-master/r/1252160
Tested-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix pri_is_gpc_addr: determines whether a register offset
is a GPC address.
Needed for:
Bug 200249125
Change-Id: I8322efc95cb8d02fa42b916f6649d9fa3f93171c
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1255061
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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On dGPU so far we boot only at maximum GPC2CLK frequency. Expose that
as maximum clock rate to user space.
Bug 200251486
Change-Id: Ie3463782a0e36028074325ce652c7ef554f6ea2c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252907
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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We build all necessary components only on builds with T18x support.
Bug 200251486
Change-Id: I927ceecbbc8c9e83ee84656fb4a8643356f224ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1253632
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Instead of using enum type for litter values, use
define macros. This will fix:
1. Resolve ambiguity associated with enum type size.
2. Litter values can be extended easily in future chips.
JIRA GV11B-21
Change-Id: Idca5144ea3754820c67831a716bb0aaf2e375eb2
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254854
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix small problems related to signed versus unsigned comparisons
throughout the driver. Bump up the warning level to prevent such
problems from occuring in future.
Change-Id: I8ff5efb419f664e8a2aedadd6515ae4d18502ae0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252068
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Currently, in gk20a_scale_target, we set clock frequency
even if it is equivalent to the rate previously requested by
the governor. This change adds a check to bypass this in
case new_frequency == prev_frequency.
These clocking operations result in multiple BPMP calls, and add
significant overhead to submit time. So, we avoid these
operations when possible.
Bug 1795076
Change-Id: I0f180564e54581f0f4add4626c647e0b9a1bbe43
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1247913
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aaron Huang <aaronh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We right now obtain pm_qos frequency requirments in
qos notifier callback gk20a_scale_qos_notify()
But now we want to limit GPU frequencies based on
frequency limited from devfreq nodes
And devfreq requirement should precede over
qos requirements
Hence, move all frequency estimation and clipping
to function gk20a_scale_target() which sets the
frequency at the end
Bug 200245796
Change-Id: I0572c676dce0acc0917924a11e4c0fb4a9db4e6e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1243427
(cherry picked from commit 81c757a3232463d126aecba64ca0c55d8e4423d2)
Reviewed-on: http://git-master/r/1239936
Reviewed-by: Aaron Huang <aaronh@nvidia.com>
Tested-by: Aaron Huang <aaronh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 200233943
Change-Id: I80c859e96ae12057fae70d56f93a0b4878e5225b
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1242482
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Register gpcclk with Common Clock Framework to expose GPCPLL frequency
control
Bug 200233943
Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1236979
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This allows us to use these functions with both Tegra and Common Clock
Frameworks
Bug 200233943
Change-Id: I5a394d7bacfecabeabc64d32dab214d2e7cf89d7
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1242481
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Tegra fuse driver no longer supported on k4.4
Bug 200233943
Change-Id: I31b58d947436a51ff57b16f7903e9ef8daaf66fc
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1242480
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug: 200233943
Change-Id: I8eb2f3cf45b23d7d4e30bf4d5dfc2d6f09c8481e
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/1250979
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
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This reverts commit 5f1c2bc27fb9dd66ed046b0590afc365be5011bf.
Added back now that matching RM server has been updated:
In hypervisor mode, all GPU VA allocations must be done by client;
fix this for the allocation of the hwpm ctxt buffer
Bug 200231611
Change-Id: Ie5ce2c2562401b1f00821231d37608e3fc30d4a4
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1252138
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We have never used the IOCTL FREE_OBJ_CTX. Using it leads to context
being only partially available, and can lead to use-after-free.
Bug 1834225
Change-Id: I9d2b632ab79760f8186d02e0f35861b3a6aae649
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1250004
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue:
warning: symbol 'pmu_allocation_get_fb_size_v3' was not declared.
Should it be static?
Fix:
Declare the 'pmu_allocation_get_fb_size_v3' as static
Bug 200067946
Change-Id: If93e074ecc041e33f91cb46913f6632bf32f48f0
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1250905
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Skip checking of u32 event_id if it's smaller than zero.
Change-Id: I207c244eeff10f294c41a76b53f9393d50a84026
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249967
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Integration error has resulted into kfree() being called twice for
PM FBPA region of ctxsw registers.
Change-Id: Ia959e024ba6f8d2c7fc43b0c7e082f34b50962a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249966
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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If gk20a_engine_id_to_mmu_id() fails, it returns ~0. Deal with this
by checking the results in each call to it.
Change-Id: I6fb9f7151f21a6c4694bfb2ea3c960d344fe629f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249965
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In calls to gk20a_fifo_recover() we pass a bitfield of engines to
recover. We generate the bitfield by acquiring engine id from FIFO,
and using BIT(). If GR engine is now known, the resulting engine ID is
u32 with all bits set, which cannot be passed to BIT().
gk20a_fifo_recover() can already deal with all bits set, so pass that
verbatim instead.
Change-Id: Ib79d8e7e156deef0d483642cfb1ce7bf55f3c572
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249964
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When buffer's IOVA is zero, treat that as error condition instead of
ignoring and continuing.
Change-Id: I2ede9921945645f526b0600f61f7e5ed19af6d73
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249963
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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In CDE GPU CONFIGURATION the result is computed using 32-bit
arithmetic and returned as 64-bit unsigned integer. Cast intermediate
result to u64 to prevent unintentional overflow.
Change-Id: Iebe53e2b17c1aaa498245a52962c3dbad7ce893e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249962
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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vgpu_vm_alloc_share() wants to return -EINVAL if VMA areas requested
do not fulfill the criteria. The error code gets overwritten by a
call to vgpu_comm_sendrecv(), which makes vgpu_vm_alloc_share() always
return 0.
Change-Id: I93f56025f963d1d4ad2f9b06139fce742d3be41b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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railgate_enable_store() has two places where err is checked and
returned. Because we have only one place where err can be set,
the second check and return are superfluous.
Change-Id: Id45923fc829f061fee34fa1abca0359b443e6f0d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249960
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Move debug write so that we access length and base of allocation
before the alloc structure gets freed.
Change-Id: I02e418f423beaa2b52a32d1abcff327b68dd5fa6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249959
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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When allocating a fence fails, free sync_fence only if one has been
created.
Change-Id: I2ecefd25c4e000f415b28c7c2b01b91654d6ef43
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249958
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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We multiply integer entry size and number of runlist entries and
store the result in u64. The result is used as size of memory, so
it should be size_t instead.
Change-Id: I0f5baa66ede259c9b42ede64c08f821c3e74a20b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249957
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Fix FBP and ROP_L2 enable masks for Maxwell+. Deprecate rop_l2_en_mask
in GPU characteristics by adding _DEPRECATED postfix. The array is
too small to hold ROP_L2 enable masks for desktop GPUs.
Add NVGPU_GPU_IOCTL_GET_FBP_L2_MASKS to expose the ROP_L2 masks for
userspace.
Bug 200136909
Bug 200241845
Change-Id: I5ad5a5c09f3962ebb631b8d6e7a2f9df02f75ac7
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1245294
(cherry picked from commit 0823b33e59defec341ea7919dae4e5f73a36d256)
Reviewed-on: http://git-master/r/1249883
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Define fuse macros depending on kernel version as fuse
offset got changed in K4.4 and for K4.4 fuse defines are
defined in common header file (tegra-fuse.h)
- Use fuse control read/write APIs when reading control
registers for K4.4.
Bug 200243956
Change-Id: I5a86ef58d9de17a273aea8d3ce8ad5772444dac2
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1245824
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Change-Id: Ia1157198aad248e12e94823eb9f273497c724b2c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1248366
Tested-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This reverts commit 57821e215756b3df7acc9c0eb5017e39f141d381.
Change-Id: Ic4801115064ccbcd1435298a61871921d056b8ea
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/1247825
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Babu Bodla <rbodla@nvidia.com>
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In hypervisor mode, all GPU VA allocations must be done by client;
fix this for the allocation of the hwpm ctxt buffer
Bug 200231611
Change-Id: I0270b1298308383a969a47d0a859ed53c20594ef
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1240913
(cherry picked from commit 49314d42b13e27dc2f8c1e569a8c3e750173148d)
Reviewed-on: http://git-master/r/1245867
(cherry picked from commit d0b10e84d90d0fd61eca8be0f9e879d9cec71d3e)
Reviewed-on: http://git-master/r/1246700
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added PMU thermal slct RPC handling for WARN_TEMP threshold
configuration.
JIRA DNVGPU-130
Change-Id: I5011db5f08476516f72722e639838e968e7e60dd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1242132
(cherry picked from commit 6e87a23ca04be435107da801c15f7b55a1f45e8b)
Reviewed-on: http://git-master/r/1246211
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The following CL contains the following VBIOS thermal table parsing
and PMU interface support.
1) Thermal device table
2) Thermal channel table
JIRA DNVGPU-130
Change-Id: I3c1baca3fec2727b6d20aa6c007096372a6a3efe
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1240631
(cherry picked from commit 1d6fa9ab49b1c84e7f845de206821d879cbda356)
Reviewed-on: http://git-master/r/1246204
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Populate chip specific sm id table.
JIRA GV11B-21
Change-Id: I58869b2c3e55449a7d999ddf73d6eb7b359b2a07
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1227095
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-122
Change-Id: I8491dc0b534c99d43057de1b35d8cdacde93f658
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1224366
Reviewed-on: http://git-master/r/1245118
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Implement chip specific commit_global_timeslice function.
JIRA GV11B-21
Change-Id: I937dda77870f164d034686d6d41482c875940320
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1243944
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Update pmu HAL to check for pmu support.
pmu initialization will check for pmu support in
that platform.
JIRA GV11B-21
Change-Id: Ib55be58a1540862b7a91a6162544d10be85b5eb4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1243911
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In the nvgpu_pci_devnode() function only set the mode if the mode
pointer is valid. In some cases this function only needs the name
of the node and not its permissions.
Bug 1816516
Change-Id: I603c1499083fb29cb5fe4a871068e0bf2cbe9c3d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1225614
(cherry picked from commit 11874ad9df49b44fac4e90d83e138ead63bbb2f9)
Reviewed-on: http://git-master/r/1244907
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-123
Change-Id: Ia28db5d645aa431f11dc8720bf1d08e6d756e20f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1227670
(cherry picked from commit 2c7f89ceef3f9173fefa44b1a959345744e66536)
Reviewed-on: http://git-master/r/1244659
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- added voltage interface & ctrl defines.
JIRA DNVGPU-122
Change-Id: Ia1a4c655c3c5faa638cafcdc75bdfb0e3c3be54f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1222775
(cherry picked from commit 46ff4d54d3cc02d9f039091f09eea09a5d6c22ce)
Reviewed-on: http://git-master/r/1244654
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-70
Change-Id: I927240432c4e27c01912d073ad9725f0c526288c
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1239804
Reviewed-on: http://git-master/r/1242203
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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