| Commit message (Collapse) | Author | Age |
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations caused by
include guards in pmuif by renaming them to follow the convention,
'NVGPU_PARENT-DIR_HEADER_H'.
JIRA NVGPU-1028
Change-Id: I19471ed8d8f7b278f497df74f760cdb1edc43ed0
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808133
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Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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The original change caused cuda atomic perf regression.
Bug 2310618
This reverts commit 10c3d4447d4206302f5d51695bf1f193255dd889.
Change-Id: Iea5391a89fdfadfb9a79cda57e71f1c9e87ca882
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1793880
(cherry picked from commit d0e51ddcb8139de70916335f124a80b8b588308b)
Reviewed-on: https://git-master.nvidia.com/r/1804945
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Move all code from fb_gk20a.c to fb_gm20b.c.
Change-Id: I87fbdfee76599e019564d66bf248aaffcf978498
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801422
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fb_gm20b.c included hw_gmmu_*.h header. It was not used, so remove the
include directive.
Change-Id: I0ea64bf38a3680ad5deb11a1d02c320fbba57685
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801421
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HUB and GPC MMU debug modes were set in the same function. This
introduced a dependency from FB code to GR registers. Split setting
of GPC MMU debug mode to GR HAL.
Change-Id: I003446f9dfa147f526bd01d3b6130f4037d9b183
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801420
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This patch corrects a handful of MISRA 10.1 violations involving
illegal arithmetic operations (e.g. bitwise OR) on boolean values:
* fix to status handling in regops validation code
* fix to debugger event handling in gr code
* fix to entries_left tracking in runlist construct code
* fix to verbose channel dumping and reset tracking in fifo code
JIRA NVGPU-650
Change-Id: I3c3d9123b5a0e08fc936d0e63d51de99fc310ade
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810957
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g->clk_arb is currently initialized as a part of gk20a_finalize_poweron().
Any subsequent call to gk20a_finalize_poweron reinitializes the clk_arb
and leading to memory leaks. This is resolved by protecting the
g->clk_arb initialization with a mutex clk_arb_enable_lock in struct
gk20a. We skip initializing the g->clk_arb if its not NULL.
Bug 2061372
Change-Id: I59158e0a5e4c827fdbd6d9ea2d04c78d0986347a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1811650
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Currently, clock arbiter code is extensively using dgpu specific
implementation. This patch restructures the clk_arbiter code and moves
gp106 specific code into HAL. Following changes are made in this patch
1) clk_domain_get_f_points is now invoked via HAL for gp106 i.e.
g->ops.clk.clk_domain_get_f_points.
2) moved nvgpu_clk_arb_change_vf_point and other related static
functions to clk_arb_gp106.c.
3) Instead of only checking if get_arbiter_clk_domain is empty, a
check for support_clk_freq_controller is also added. This is to enable
the clk_arbiter based on support from both the OS and the chips.
Bug 2061372
Change-Id: I65b0a4e02145a86fbbfb420ed591b1fa3c86f6dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774279
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print the correct error code when the sync_fence construction fails
instead of just an error message.
Bug 200421587
Change-Id: I9d6f9df8bec0e43d0a1198fbe7ab2631f12f572a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809642
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Declare the ID table as a device table to enable autoloading
of the module as the device tree is instantiated.
Change-Id: I4f29259a0a9af6b72be99ed27789ee4d5d7a1aa2
Signed-off-by: Preetha Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809174
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Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.
In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.
Bug 200412641
Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
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Debug fused chips do not have production signature. Use debug
signature for memory unlock binary. Requires also exporting a HAL
for checking debug mode from PMU.
Bug 200445202
Change-Id: I7f88ed6db2fe1c614fe9d4074dbf974c3817f453
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809225
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: If5e4350a337b61b8a82870860a690d06b89c88c1
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808972
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- Remove the usage of NVGPU_CTXSW_FILTER_ISSET splattered
across nvgpu, and replace with a MACRO defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "uapi/linux/nvgpu.h" from common code.
EVLR-3078
Change-Id: I60b0e1627576a4b255671d58530d8c773ea6154c
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803210
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Convert linux nvgpu ctxsw tags type of the form
of NVGPU_CTXSW_TAG_* into common nvgpu ctxsw tags
type of the form of NVGPU_GPU_CTXSW_TAG_*
EVLR-3078
Change-Id: I337487722c103c05003457f74ad6e05bf3bd38fc
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803209
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- Remove the usage of nvgpu_ctxsw_trace_entry splattered
across nvgpu, and replace with a struct defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "asm/barrier.h" as "nvgpu/barrier.h" is already
included.
EVLR-3078
Change-Id: Iabfb105b891b0078ed326a8047ef14ebe1888cf2
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803208
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Currently, we need to include the MC hardware header in nvlink file
to generate reset mask.
We can use the reset_enum present in DEVICE_INFO table's IOCTRL entry
which is meant to index into NV_PMC_ENABLE_DEVICE register bitfields.
This allows us to not #include the MC hardware header in nvlink IP
file.
JIRA NVGPU-966
Change-Id: I037498038b12f795ee444916fb586355ebf04bb3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796819
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We parse the DEVICE_INFO table entries to get IOCTRL(NVLINK)
engine related information like the pri_base_addr, reset_enum,
and the intr_enum.
For grouping the chained entries per IP, the current parsing logic
relies on the fact that engine_type entry for an IP will be parsed
before other entries in the chained group.
As the enum_type entry (which contains the reset_enum) appears
ahead of the engine_type entry, the parsing logic fails and we read
reset_enum as 0.
Modify the parsing logic to group the chained entries correctly.
Also we were using a wrong API to extract the reset/intr_enum from the
table entry.
JIRA NVGPU-966
Change-Id: I68052db5d1c88a15e04f311486f3f639caf9ed9e
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796808
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The scrubber binary after completion updates its return
code in mailbox register 0. The memory unlock code reads
this registers to determine the success of memory scrubbing.
This register is initialized to 0 during nvdec falcon reset.
If the scrubber binary halts due to an error condition, the
return code is not updated and it stays at 0.
Initialize the status register explicitly to non-zero value
helps avoid just false positives.
Add falcon register dump and PC trace to help debug the memory
unlock failures.
Change-Id: I3086dda2a9719c2d0b8a7ae898f1a03bedfa21b0
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808899
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This reverts commit 96d53bff8598a44fcec3f2492c8ec630d71d5dd0.
Bug 2330230
Change-Id: Icd146e80bac0425fcb59f266f1d3582c40211739
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804753
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The common channel header was missing include guards, so add them. Also
rename the Linux channel header guard that was in conflict.
Jira NVGPU-967
Change-Id: If782407ef1497202196a362893ef9c1b2330977a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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struct priv_cmd_queue and struct priv_cmd_entry are related to the list
of jobs in a channel, so move their definitions from the mm header to
the channel header.
Jira NVGPU-967
Change-Id: Ib0cf3fd52be463e720165a47e56b14724273473e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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struct gpfifo_desc belongs to channel; reduce dependencies to mm by
moving it there.
Jira NVGPU-967
Change-Id: I3c6ac3d4e47fc0c843d407ee0e1100a009763d08
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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The graphics subctx header object is nothing but memory. Drop the
dependency to gr header file in the channel header file and substitute
struct nvgpu_mem for struct ctx_header_desc.
Jira NVGPU-967
Change-Id: Ic3976391016c42d2ada4aac3e0851a1222244ce9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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GM20B GPCPLL registers are accessed via sys address space with the
exception of the last dvfs2 register that can be accessed only through
bcast address. However, in debugfs loop dvfs2 sys address should be
used as loop terminator; otherwise, loop body is never executed, and
GPCPLL registers debugfs node is broken. Fixed it in this commit.
Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808784
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HW headers in nvgpu have gotten a bit out of date. Regenerate
headers and add the following registers:
* Add PTIMER timeout registers to all chips
* Add PD, SCC, SSYNC and MME interrupt registers to all chips
* Add HWW ESR INFO register to all chips
Change-Id: I34e09371083ac1568666b0cd487a106fad56aa12
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807709
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Management of kinds was moved to user space. Remove the lists of kind
types in kernel.
Change-Id: I9872626850d19132715fb8903a0bb13a0d319654
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807708
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Add usermode_gpfifo member to channel to store the usermode-owned buffer
data. This makes it more explicit about which (user or kernel) memory is
accessed.
Jira NVGPU-967
Change-Id: I98e4f4568f04aa31e00e497794fadd4997ba8aab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807503
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Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The gr_gk20a_add_zbc() routine returns a signed error
(errno) status value.
Current callers of this function use a bitwise OR to collect
the returned error status values to generate a single value
to return.
Bitwise OR on signed status values is flagged as a
violation of MISRA Rule 10.1 (not to mention that in this
case it potentially results in a garbage return value).
To eliminate such violations this change modifies the
following routines to fail immediately on the first error
from a call to gr_gk20a_add_zbc():
* gr_gk20a_load_zbc_default_table()
* gr_gv11b_load_stencil_default_tbl()
JIRA NVGPU-650
Change-Id: If733c1bb0e05943ff5d0355de729133c89233583
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805501
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We want to support 1/8th mode only if both endpoints have enabled
it. To know if each endpt supports 1/8th mode in the core driver,
we added a new field in shared nvlink_link struct.
Initialize this new field to false as dGPU nvlink does not currently
support 1/8th mode.
Bug 2341788
Change-Id: I6f67b6368163cbe2df3f437d2b0bf85f5f114a5b
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1806087
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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debug_clk.c implements clk debugfs of gm20b. Rename the file
to reflect clk debugfs functions implemented for gm20b.
JIRA NVGPU-603
Change-Id: I6ff4b71abe400b8fc2a8d79e12e53e2048ccdc05
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797903
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Currently only cde uses nvgpu_os_linux_ops to set up linux
specific ops. Move nvgpu_os_linux_ops of a gpu to a common
file so that those can be reused for other os ops of that
gpu.
JIRA NVGPU-603
Change-Id: Icf1ff275d3832229137f730fe8183b8015e82673
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797902
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This reverts commit d029ad5d8d39e7f153b43ca9d60c0ed1f23c8037.
Bug 200441252
Change-Id: I1fe7cd1c9446d6572711b050e946b03605acf422
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808563
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MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.
This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.
JIRA NVGPU-647
Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
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In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h
JIRA-597
Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I8493274995ed8de526902dd0ca0808b2972e28aa
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796806
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fix violations where an arithmetic operation is performed on
signed and unsigned int types.
In balloc_get_order_list() the argument "int order" has been changed to
a u64 because all callers of this function pass a u64 argument.
JIRA NVGPU-992
Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The comptag allocates memory based on the available total RAM, which
theoretically should be the MAX physical RAM size however practically
should deduct the part being taken by the running system. Otherwise,
the taken memory part will never get used and wasted.
This change adds a comptag_mem_deduct to each platform and to allow
them to assign the deductible value based on their own use cases so
as to save memory.
Bug 2327574
Bug 2284925
Change-Id: I124e20a66183c22723c34a7ec6ce34832c12f02e
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804157
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Fix violations where a boolean is used as an operand in bit-shift
operations and is interpreted as a numerical value.
JIRA NVGPU-649
Change-Id: I4494c3b69d0e53319331b47d0a4de0b3de279f4f
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I604d85367cd4b99c39df2b9fa2d7a7219ef941d5
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807153
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I1651ae8ee680bdeb48606569c4e8c2fc7cb87f20
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805077
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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nvgpu_os_fence_syncpt_create returns ERR_PTR instead of NULL whenever
its unable to construct a valid struct sync_fence instance. The
current code is not handled to detect errors returned using
ERR_PTR. This patch replaces the !fence check with IS_ERR() that
handles the return correctly.
Bug 200421587
Change-Id: I0ecfa8a651b8d5b743d11aab80d7a4cd71be8b1a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804509
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I1562bd1b109a100af29bd147ed8b56463b6a8e63
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796674
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Added support for below multiple therm sensor device & defined macros
GPC_TSOSC
GPC SCI
HBM2_SITE
HBM2_COMBINED
- Added PMU interface for listed therm sensor device
- Added nvgpu interface for listed therm sensor device
- Added construct boardobj support for listed therm sensor device
& called to update nvgpu interface.
- Updated devinit_get_therm_device_table() to read sensor info from
therm device table from vbios table & construct respective
therm device boardobj using construct_therm_device_*()
based on class_id param read from vbios table.
- Updated RPC handler to handle THERM ack request
- Updated gv100 therm ops "get_internal_sensor_limits"
to point to gp106_get_internal_sensor_limits()
Change-Id: I4b4ed501d0625cb8fc7b300c820622e40ae59fe6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676785
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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When we program MMU debug mode, we program it to both HUB and GPC
MMU. The query retrieved the value from GPC MMU, which introduces
a dependency from FB to GR. Change the code to retrieve the mode
from HUB MMU instead.
Change-Id: I6fa98e050480f7405395b7e44965defa386734d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Implement HW scrubber specific code for filling in ACR header. The
PMU code relied on PMU debug mode for choosing between dbg/prod
signature, and also introduced a direct dependency from FB to ACR.
Change-Id: I08fa31538bec3dcb5d161a6e7076ffad76129a97
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801418
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Do not refer to bit width in RAM_IN field when shifting MMU fault
buffer entries. Export the correct bit shift values for the fields
and shift with that.
Change-Id: I6878118bb14f070626e8244d5044b6818c8ea283
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801417
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Remove extra UART spew in fb_gv100.c. We were using nvgpu_info()
instead of nvgpu_log_info().
Change-Id: Ideb44e492a76ca2f58c14b445bb0a31ebe4c995a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805692
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I18cf871f2d1296b931d6ab43f1ac668551171dcc
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805076
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: Ib5961506b0f95867a57f8c0d7024568785fe7b93
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797332
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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