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* gpu: nvgpu: do not use raw spinlock for ch->timeout.lockSeema Khowala2019-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | With PREEMPT_RT kernel, regular spinlocks are mapped onto sleeping spinlocks (rt_mutex locks), and raw spinlocks retain their behaviour. Schedule while atomic can occur in gk20a_channel_timeout_start, as it acquires ch->timeout.lock raw spinlock, and then calls functions that acquire ch->ch_timedout_lock regular spinlock. Bug 200484795 Change-Id: Iacc63195d8ee6a2d571c998da1b4b5d396f49439 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2004100 (cherry picked from commit aacc33bb47aa8019c1a20b867d3722c241f7f93a in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2017923 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract out timeout rewindingKonsta Holtta2019-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The channel timeout ends up in a strange state during timeout handling for a brief moment; it can become stopped and started again, and the timeout lock is released in the middle. Add a more explicit rewind function to reset the timeout to start if it's active. The active check allows to use this from gk20a_channel_timeout_restart_all_channels(), so that's also modified. Also replace the return statements with more readable control flow in gk20a_channel_timeout_handler(). Bug 200484795 Change-Id: Ia7d67242dfc149ace1f4f841a837e90b6c985308 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1989327 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit 8979a97af3dbb65904f9db8a22a6a168a3f41447 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2017922 Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename dma map/umap interfacesPreetham Chandru R2019-02-14
| | | | | | | | | | | | | | | | On Desktop verion, map is called nvidia_p2p_dma_map_pages and umap is called nvidia_p2p_dma_umap_pages. So renamed these two apis to match the desktop version. Bug 200438879 Change-Id: I66301c48b832dfed8c3950678f473c2f82b8761a Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2014940 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check ch_timedout for poll/restartSeema Khowala2019-02-13
| | | | | | | | | | | | | | | | | | | | | | | | poll_timeouts and timeout_restart_all_channels should only handle channels that have not been recovered/aborted. Check ch_timedout status of the channel to make sure channel is still alive to be used. A channel reference could still be available even if it is recovered but not closed. Bug 2404865 Change-Id: I016c8b9952ef1d4c349c2a2a2ca55cb81326d380 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929339 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit def687d4dfbc92dbc8a13781f8cee606eab4f3f3 in rel-32) Reviewed-on: https://git-master.nvidia.com/r/2016995 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do not suspend/resume recovered channelSeema Khowala2019-02-13
| | | | | | | | | | | | | | | | | | | | | | Already torn down channels should not be suspended or resumed. A channel reference could still be available even if it is recovered but not closed. Use ch_timedout status to check if channel is already recovered/aborted. Bug 2404865 Change-Id: I718eab6032ee94a9322da7a239a978b388de2b01 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929338 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 88cff206ae31999240945a870683e8a10be584d7 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2016994 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename has_timedout and make it thread safeSeema Khowala2019-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently has_timedout variable is protected by wmb at places where it is being set and there is no correspoding rmb whenever has_timedout variable is read. This is prone to errors for concurrent execution. This change is supposed to fix this issue. Rename has_timedout variable of channel struct to ch_timedout. Also to avoid rmb every time ch_timedout is read, ch_timedout_spinlock is added to protect ch_timedout variable for taking care of concurrent execution. Bug 2404865 Bug 2092051 Change-Id: I0bee9f50af0a48720aa8b54cbc3af97ef9f6df00 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1930935 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 1f54ea09e3445d9ca3cf7a69b4967849cc9defc8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2016975 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace input param chid with pointer to channelDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | preempt_channel needs to use the channel to pass it to other public functions, get access to a tsg etc. This qualifies it to take a pointer to a channel as an input parameter instead of a chid. Increment the channel ref counter using the function gk20a_channel_from_id in functions where we get the chid from the h/w registers directly. Once the prempt_channel function call is done, use a gk20a_channel_put on the referenced channel. Jira NVGPU-1461 Change-Id: I6c87c8104cfcb418d468c8c590087fd4aeabf4bd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1963200 (cherry picked from commit 9abe9fe062367902ede7721cff55396859f8e4e8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013728 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace input param chid with pointer to channelDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | | gk20a_fifo_recover_channel takes a reference to the channel via its chid before passing the channel pointer to other public functions such as gk20a_channel_abort and gk20a_fifo_error_ch. This qualifies the gk20a_fifo_recover_channel to take a pointer to a channel instead of only chid. Jira NVGPU-1461 Change-Id: I338a12a05e5ccee785a202fea7848db5201a3a39 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1963199 (cherry picked from commit 99acb8011a8627a2433d31e6e0c8ab833ab3317d in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013727 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace input parameter tsgid with pointer to struct tsg_gk20aDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The function gk20a_fifo_recover_tsg has to pass a valid struct tsg to other functions from within. This qualifies it to have a pointer to struct tsg_gk20a as an input parameter. Tsg specific parts of the gk20a_fifo_preempt_timeout_rc are now moved into another function gk20a_fifo_preempt_timeout_rc_tsg that takes a tsg as an input and passes it to gk20a_fifo_recover_tsg. The pointer to a tsg is also used to enumerate channels from within. The function gk20a_fifo_preempt_timeout_rc now contains only channel specific code. Jira NVGPU-1461 Change-Id: Ice0a9921567841fb5586a7e4e010c442ca6cf172 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1961675 (cherry picked from commit e19cea7ab3ef688186222dec940c2396536408ce in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013726 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace input parameter tsgid with pointer to struct tsg_gk20aDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | gv11b_fifo_preempt_tsg needs to access the runlist_id of the tsg as well as pass the tsg pointer to other public functions such as gk20a_fifo_disable_tsg_sched. This qualifies the preempt_tsg to use a pointer to a struct tsg_gk20a instead of just using the tsgid. Jira NVGPU-1461 Change-Id: I01fbd2370b5746c2a597a0351e0301b0f7d25175 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1959068 (cherry picked from commit 1e78d47f15ff050edbb10a88550012178d353288 in rel-32) Reviewed-on: https://git-master.nvidia.com/r/2013725 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace tsgid input variable with pointer to a struct tsg_gk20aDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | | replace tsgid with a pointer to a struct tsg_gk20a in the function gk20a_fifo_tsg_abort(). gk20a_fifo_tsg_abort needs to enumerate through all the channels within the tsg as well as pass the tsg pointer to other functions, qualifying the need to use a pointer instead as an input parameter. Jira NVGPU-1461 Change-Id: I59cec05d5d778f733d0c3e9ffadf46e74e249080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1956567 (cherry picked from commit e5bebd880f28fe719c5e01e165fb189e7cafee01 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013724 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: delete raw chid lookupKonsta Holtta2019-02-05
| | | | | | | | | | | | | | | | This (dangerous) array lookup with no channel references is now unused. Jira NVGPU-1460 Change-Id: Ic6bdbcf19fc8996bc6ff02a40afe3224bdd5bc27 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1955402 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 4a53854a92e7c841fa3cb58da062fa756ae7b5c7 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008517 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: store ch ptr in gr isr dataKonsta Holtta2019-02-05
| | | | | | | | | | | | | | | | | | | | Store a channel pointer that is either NULL or a referenced channel to avoid confusion about channel ownership. A pure channel ID is dangerous. Jira NVGPU-1460 Change-Id: I6f7b4f80cf39abc290ce9153ec6bf5b62918da97 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1955401 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 4e6d9afab87fce6b0a5c18b51d174ec7f800b19c in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008516 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add safe channel id lookupKonsta Holtta2019-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gk20a_channel_from_id() to retrieve a channel, given a raw channel ID, with a reference taken (or NULL if the channel was dead). This makes it harder to mistakenly use a channel that's dead and thus uncovers bugs sooner. Convert code to use the new lookup when applicable; work remains to convert complex uses where a ref should have been taken but hasn't. The channel ID is also validated against FIFO_INVAL_CHANNEL_ID; NULL is returned for such IDs. This is often useful and does not hurt when unnecessary. However, this does not prevent the case where a channel would be closed and reopened again when someone would hold a stale channel number. In all such conditions the caller should hold a reference already. The only conditions where a channel can be safely looked up by an id and used without taking a ref are when initializing or deinitializing the list of channels. Jira NVGPU-1460 Change-Id: I0a30968d17c1e0784d315a676bbe69c03a73481c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1955400 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 7df3d587502c2de997dfbe8ea8ddc114d0a0481e in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008515 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: channel: make chid u32Philip Elcan2019-02-05
| | | | | | | | | | | | | | | | | | The chid member of the channel_gk20a struct was being used as a unsigned value. By being declared as an int, it was causing MISRA 10.3 violations for implicit assignment of different types. JIRA NVGPU-647 Change-Id: I7477fad6f0c837cf7ede1dba803158b1dda717af Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1918470 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 1c7bb9b538200a11aa3ef31d72038d8ba820dfca in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008514 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make tsgid a consistent typePhilip Elcan2019-02-05
| | | | | | | | | | | | | | | | | | Different units were declaring tsgid as int or u32. This makes everyone use u32. This change resolves MISRA 10.3 violations for implicit assingment to different types. JIRA NVGPU-647 Change-Id: I78660e737acb0dad76dd538e5dd37f4527cf5acd Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1918469 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit f5cac144a04a3ef83762ecb2e3f405196beffd68 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008513 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix double handling in timeoutKonsta Holtta2019-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The context switch timeout works by triggering a hardware timeout at 10 Hz. When handling these, we check whether a channel has actually timed out. Currently the timeout limit can be shorter than the 10 Hz interval which always causes us to recover a channel but would also cause detection of progress if there was any in the interval. Handling both situations at the same time would reuse the channel pointer local to the function after a loop has finished and would cause memory corruption. Fix this by making the two branches mutually exclusive, and move the recover case to happen first because that's how our tests assume things to work. Jira NVGPU-967 Bug 2502074 Change-Id: I26aa0fa7fd80ab42a9a1a93a6cca2cd29c9d3f3f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1932449 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 8ac9a53d816a3d012a6948a9a96ac6db699c662di in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/1997597 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: clear priv intr in log_pending_intrsSeema Khowala2019-02-02
| | | | | | | | | | | | | | | | | | | | | Clear pending priv interrupt in log_pending_intrs. Priv ring errors have not been cleaned up in gm20b. It is ok to just clear it. Bug 200477291 Bug 200486293 Change-Id: I850a261828a9d49b6b4a82d75f5347acbc17b0fe Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2008818 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allocate ctxsw buffers once onlyPeter Daifuku2019-01-31
| | | | | | | | | | | | | | | | | In *_set_ctxsw_preemption_mode, only allocate buffers the first time through. Bug 200418468 Change-Id: I22d06463416615b9a9d671c32b6fe76b602a2623 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2004301 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvgpu locks to vanilla Linux locksPreetham Chandru Ramchandra2019-01-22
| | | | | | | | | | | | | | | | | | | | | Replace nvgpu locks to vanilla Linux locks. For the custom kernel driver when they include nv-p2p.h, nvgpu/linux/lock.h will not be available because nvgpu/linux/lock.h is not copied to /usr/src/kernel_header_file. Bug 200438879 Change-Id: I55b52c6f791970650388b7d51c4d30b5fe75bbb8 Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1997950 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit eb887094e4f4446e6eed9c17e88f4a36ac5ae972) Reviewed-on: https://git-master.nvidia.com/r/2000831
* gpu: nvgpu: move nv-p2p.h to include/linuxPreetham Chandru Ramchandra2019-01-22
| | | | | | | | | | | | | | | | | Move nv-p2p.h to include/linux so that it is available to external kernel modules to be used. Bug 200438879 Change-Id: I40707fe9f798b3ccf077dbdc942f8d6fc9019458 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1986646 (cherry picked from commit cfe4a2e5e87560519aedb92e2d12e39e09473a54) Reviewed-on: https://git-master.nvidia.com/r/2000830 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle timestamp buffer full ctxsw_intr0Seema Khowala2018-12-29
| | | | | | | | | | | | | | | | | | | | | | | | If enabled, fecs trace updating happens from ucode side even when there is no fecs trace dumper application to consume it. Due to this, trace buffer will get eventually full and ucode will trigger ctxsw_intr0. Reset fecs_trace buffer to handle timestamp buffer full ctxsw_intr0. Bug 2361571 Bug 200472922 Change-Id: Ia26a17635fc6bd6e8663b8af983acc91839ecfcd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1965370 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit 790ba095543b33f4cc3a145559ad31a1e9f99d98) Reviewed-on: https://git-master.nvidia.com/r/1979746 GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
* gpu: nvgpu: add handling for ctxsw_intr0Seema Khowala2018-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | ctxsw_intr0 is triggered by ucode even if it is not enabled by driver. Add handling for processing ctxsw_intr0. fecs mailbox(6) is used to report fecs/gpccs misc error codes. Also dump falcon stats for unhandled fecs intr. Bug 2361571 Bug 200472922 Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1966984 (cherry picked from commit 2c379cad0f6a01d07102898b362735a574f3aea8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/1979745 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: clear all handled fifo interruptsSeema Khowala2018-12-29
| | | | | | | | | | | | | | | | | | | | Issue is that local variable clear_intr is reset if fifo intr handler happens to handle interrupts handled by fifo_error_isr. This fix is to take care of clearing all handled fifo interrupts. Bug 2361571 Change-Id: Ic8fe2294cfb25c58925942750a81c104ec9747de Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1960330 (cherry picked from commit 1195239d1c624e600ec4152374c493e887a90774 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/1979744 GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unnecessary error print of falcon queueMahantesh Kumbar2018-12-26
| | | | | | | | | | | | | | | | | | | | | | | | | -For queue full there is pmu_dbg message & returned with EAGAIN error to end caller for retry, so intermediate error message is not correct print for queue full. Bug 200477085 Bug 200477931 Bug 200475876 Change-Id: I1109f15d0815f4ab2d8f8ca303db447d856f372c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> (cherry picked from commit I263f66f7a8d8f1b98985f32f9daa49b09309c359) Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1979935 Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
* nvgpu: pmu: cleanup init thread on destroyPeter Daifuku2018-12-15
| | | | | | | | | | | | | | | | | | | | | | | | In nvgpu_kill_task_pg_init(), call nvgpu_thread_join() if the init thread is no longer running in order to reclaim thread resources. Bug 2452799 JIRA ESRM-437 Change-Id: Id9c67f689027f00039ac2df226ee9c28ad89dd1d Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1967983 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1970058 Reviewed-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Tested-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com>
* gpu: nvgpu: vgpu: Get channel referenceDeepak2018-12-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - In vGPU code path, function vgpu_channel_abort_cleanup() does not obtain channel reference before using the channel structure (channel_gk20a) - vgpu_channel_abort_cleanup() is called by vgpu_intr_thread() which runs commands obtained from interrupt queue from RM server. - If there is a scenario where gk20a_channel_release() function runs before guest receives notification from RM server to abort channel cleanup, channel gets freed before vgpu_channel_abort_cleanup() runs. - However, because vgpu_channel_abort_cleanup() does not take explicit reference to the channel, it ends up accessing structures (such as ch->g) which are set to NULL and thus we end up in a crash. - This patch explicitly takes reference of channel before vgpu_channel_abort_cleanup() is called. - If gk20a_channel_release() runs before vgpu_channel_abort_cleanup() and ends up freeing channel, we dont get reference to freed channel in vgpu_channel_abort_cleanup() and thus we return from function rather than continuing with freed channel as was the case previously. Bug 200453473 JIRA EVLR-3411 Change-Id: I311043b2231336616b28246531cf8a0dc151b0cd Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1932028 (cherry picked from commit b91228e506c14f04945e35b5c996f711bb30a155) Reviewed-on: https://git-master.nvidia.com/r/1970807 Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Tested-by: Karl Ding <kding@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: RDMA implementationPreetham Chandru R2018-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | This change adds RDMA supports for tegra iGPU. 1. Cuda Process allocates the memory and passes the VA and size to the custom kernel driver. 2. The custom kernel driver maps the user allocated buf and does the DMA to/from it. 3. Only supports iGPU + cudaHostAlloc sysmem 4. Works only for a given process. 5. Address should be sysmem page aligned and size should be multiple of sysmem page size. 6. The custom kernel driver must register a free_callback when get_page() function is called. Bug 200438879 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I43ec45734eb46d30341d0701550206c16e051106 Reviewed-on: https://git-master.nvidia.com/r/1953780 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable/clear PMU IRQs on power offSagar Kamble2018-11-20
| | | | | | | | | | | | | | | | | | | | | | While tearing down PMU state during power off, nvgpu doesn't disable the PMU interrupts. Disable them unconditionally. Bug 200457485 Change-Id: Ia2462d879c1e7bbb4b5e8295ce211c38567c13e5 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1939025 Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1951361 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com>
* gpu: nvgpu: Add NVGPU_SUPPORT_GET_GPU_LOADThomas Steinle2018-11-20
| | | | | | | | | | | | | | | | | | Add a flag to show if NVGPU_GPU_IOCTL_GET_GPU_LOAD is supported Bug 200421190 Change-Id: I59200b1a3dbbcc0d731d1e77597e163c61417a96 Signed-off-by: Thomas Steinle <tsteinle@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1919448 (cherry picked from commit 7cb9e3cc14d3cec7e4685bd56728dc0e61b1b700) Reviewed-on: https://git-master.nvidia.com/r/1944689 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix comment in priv_cmd_buf allocationAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | Update the comment to fix obvious issues and describe the new allocation logic. Bug 2327792 Change-Id: Ica0dd4159467e3023cc487a2bf9f525db3ad76e6 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1831096 (cherry picked from commit c64f9432b13d47a791220578e823efcae4fe2a80) Reviewed-on: https://git-master.nvidia.com/r/1949221 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make priv_cmd_buf honor num_in_flight jobsAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | | | | If num_in_flight jobs is set use that to determine the proper size of the priv_cmd_buf. If num_in_flight is not set then use the original logic: the priv_cmd_buf is sized based on a worst case assumption for the GPFIFO. Also clean up MISRA issues. Bug 2327792 Change-Id: Ie192caeb6cc48fdcac57e5cbb71c534aeaf46011 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1831095 (cherry picked from commit b9ec592f1d3ce23db736ff9c36eab994fc86ed46) Reviewed-on: https://git-master.nvidia.com/r/1949220 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use deterministic flag to decide pre-allocAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | | | | Instead of using num_inflight_jobs to determine whether to pre-alloc resources for a channel use the c->deterministic flag and the number of inflight jobs field. Non-determinsitic channels do not require pre-alloced resources and deterministic channels with 0 in flight jobs (i.e no kernel job tracking, AKA fast path sumits) also do not require pre-alloced resources. Bug 2327792 Change-Id: I7e8eb0478c22e005ca2c46c555415afa0ded0be1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850123 (cherry picked from commit 05ec7b80ebeabbc27d369ebd88dfe511c30d1bad) Reviewed-on: https://git-master.nvidia.com/r/1949219 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: re-initialize fw pointer when failed to load fwVince Hsu2018-11-07
| | | | | | | | | | | | | | | | | | When ACR and PMU BL fail to boot, the firmware are releasd, but the firmware pointers are not re-initialized. That causes later invalid pointer usage. Fix that by setting them as NULL. Bug 200462464 Change-Id: Iacdf4b3c7f7144a77f595c77e6f5a29d35505672 Signed-off-by: Vince Hsu <vinceh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1941671 (cherry picked from commit 3a87a0c99819d9b00d4b7e414ec0ecfeaade961c) Reviewed-on: https://git-master.nvidia.com/r/1942950 GVS: Gerrit_Virtual_Submit Reviewed-by: Siddardha Naraharisetti <siddardhan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix deadlock when ACR boot failsVince Hsu2018-11-07
| | | | | | | | | | | | | | | | | | | The tpc_pg_lock is not released properly when ACR fails to boot, so the subsequent runtime PM resume operation will block. And it in turn also causes shutdown block due to pending runtime PM operations. Bug 200462464 Change-Id: Ia28ac11e8a7bbd826cf5f90ba8f90b29d2a55baa Signed-off-by: Vince Hsu <vinceh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1941670 (cherry picked from commit 0bda191d7b9c01a22b91feb523134b845ee7523b) Reviewed-on: https://git-master.nvidia.com/r/1942949 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Siddardha Naraharisetti <siddardhan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add reboot handlerKary Jin2018-10-29
| | | | | | | | | | | | | | | | | | | Add a reboot handler to make sure that nvgpu does not try to busy the GPU if the system is going down. If the system is going down then any number of subsystems nvgpu depends on may already have been deinitialized. Bug 200333709 Bug 200454316 Change-Id: I2ceaf7ca4fb88643310874b5b26937ef44c6e3dd Signed-off-by: Kary Jin <karyj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1927018 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Define functions static if DEBUG_FS=nNicolin Chen2018-10-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When turning off CONFIG_DEBUG_FS, there are build errors: drivers/gpu/nvgpu/os/linux/os_ops_gp106.o: In function `nvgpu_fecs_trace_init_debugfs': os_ops_gp106.c:(.text+0x8): multiple definition of `nvgpu_fecs_trace_init_debugfs' drivers/gpu/nvgpu/os/linux/os_ops_gp10b.o:os_ops_gp10b.c:(.text+0x0): first defined here drivers/gpu/nvgpu/os/linux/os_ops_gv100.o: In function `gp106_therm_init_debugfs': os_ops_gv100.c:(.text+0x0): multiple definition of `gp106_therm_init_debugfs' drivers/gpu/nvgpu/os/linux/os_ops_gp106.o:os_ops_gp106.c:(.text+0x0): first defined here drivers/gpu/nvgpu/os/linux/os_ops_tu104.o: In function `gv100_clk_init_debugfs': os_ops_tu104.c:(.text+0x0): multiple definition of `gv100_clk_init_debugfs' drivers/gpu/nvgpu/os/linux/os_ops_gv100.o:os_ops_gv100.c:(.text+0x10): first defined here This is because those functions aren't marked as static. So this patch just simply fixes the bug. Bug 2284925 Change-Id: I1da39345c653dfb50c509adb0c822b4657646c56 Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929355 (cherry picked from commit 0fd9c84f870731705d6fdbf83d8e94519ff9d3bd) Reviewed-on: https://git-master.nvidia.com/r/1933889 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL-ify pmm type broadcast valuesmatthewb2018-10-11
| | | | | | | | | | | | | | | | | | | | The PMM type-specific broadcast->unicast expansion calculation was using incorrect values. This caused the invalid register accesses to be generated. This change HAL-ifies the values, so that the expansion will be performed correctly. Bug 200454109 Change-Id: I96c15de27b5e16e4db2e788fd98e6bf7d6e7d564 Signed-off-by: Matthew Braun <matthewb@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1921717 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update all ctx headers in the tsg when update hwpm modeRichard Zhao2018-10-11
| | | | | | | | | | | | | | | | | | | | FECS could use any ctx headers for context switch, so needs to update all ctx headers in the same tsg with hwpm buffer address. Bug 2404093 Bug 200454109 Change-Id: I99e74cd8c768c06c3d215779db899a1318522db0 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1917756 (cherry picked from commit f447a8d279b0d0abc8e2d3eb6f0596ea5cd87cbf) Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1920608 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix update hwpm ctxsw mode"Richard Zhao2018-10-11
| | | | | | | | | | | | | | | | | | | | | The fix is incorrect. hwpm ctxsw mode should always in gr ctx. This reverts commit 8f30251c67811834f9d93b50ce3e97fe3aa18051. Bug 2404093 Bug 200454109 Change-Id: I8fae2c379b051a3f48fe9e886e3b2348bb94b935 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1917755 (cherry picked from commit 70248d531479fac7946ae296f926518fcc5677a0) Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1920607 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: Add mockio unit test to tmakeNicolas Benech2018-09-29
| | | | | | | | | | | | | | MockIO unit test went in before the tmake changes. Now adding tmake files so that it builds for target. Change-Id: I9f08076a46f8f6487342553999d43279fb74cabb Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1851219 Reviewed-by: Philip Elcan <pelcan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove VPR HALs from dGPUsDeepak Nibade2018-09-29
| | | | | | | | | | | | | | | | | | | | gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers. Split this into two different HALs gops.fb.dump_vpr_info() and gops.fb.dump_wpr_info() Also unset HALs accessing VPR registers on dGPUs We don't support VPR on dGPUs Remove fb_mmu_vpr_info_r() register and all its accessors from dGPU headers Bug 2173122 Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850947 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove big page setting on pascal+Deepak Nibade2018-09-29
| | | | | | | | | | | | | | | | | | | | | We don't support big page size beginning Pascal, so set HAL gops.fb.set_mmu_page_size() to NULL on all those platforms Also remove these accessors from corresponding platforms fb_mmu_ctrl_use_pdb_big_page_size_v() fb_mmu_ctrl_use_pdb_big_page_size_true_f() fb_mmu_ctrl_use_pdb_big_page_size_false_f() Bug 2173122 Change-Id: I7353412860a7a6f8a993ca9184a0dc3ca9d749af Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850946 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unused accessorsDeepak Nibade2018-09-29
| | | | | | | | | | | | | | | | | | | Remove these unused accessors fb_mmu_ctrl_vm_pg_size_f() fb_mmu_ctrl_vm_pg_size_128kb_f() fb_mmu_ctrl_vm_pg_size_64kb_f() ram_rl_entry_tsg_timeslice_timeout_disable_v() Bug 2173122 Change-Id: I5b18ab502265ed4575fceb4bd5d0ab07dd3c12a8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850945 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support for clk.measure_freq for igpuPeter Daifuku2018-09-29
| | | | | | | | | | | | | | | | | | | | | Add support for the measure_freq clock op for igpu: - add nvgpu_clk_measure_freq(), which in turn calls the get_rate() clock op. - Initialize the measure_freq clock op to nvgpu_clk_measure_freq() for native linux and vgpu. JIRA ESRM-398 Change-Id: I8a3b2ee79e29e3491a16f55281494f05cd841b07 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850585 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do nothing on invalid tsg releaseKonsta Holtta2018-09-29
| | | | | | | | | | | | | If nvgpu_ioctl_tsg_open() fails, this file has no priv data yet on release(). In that case there is nothing to free so just return. Jira NVGPU-967 Change-Id: I02dd1bb12a27745a3b28aaa4a943d79d82b14d2c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1847592 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update PMU ucode version.Deepak2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | PMU ucode is updated to use acrlib from t19xbringup branch. We are seeing build issues due to incompatibility with acrlib from tegra_acr branch. CTX_DMA aperture to be used for loading LS falcons needed update in the local acrlib. Bug 2400729. Change-Id: Iad00a332acfac307c389bde504893a87abaf7460 Signed-off-by: Deepak <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1849182 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: SEC2 RTOS support s/w initMahantesh Kumbar2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_sec2 to hold members related to SEC2-RTOS ucode support in header file sec2.h -Created nvgpu_sec2 variable under struct gk20a. -Created NVGPU_SUPPORT_SEC2_RTOS enable flag to enable SEC2 RTOS support. -Defined method nvgpu_init_sec2_support() to init SEC2 RTOS support by performing s/w setup like mutex-init, sequence-init & add support for remove_support. -Defined method nvgpu_sec2_destroy() to deinit SEC2 RTOS support. -Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy() as part gk20a_finalize_poweron()/gk20a_prepare_poweroff() sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag -Assigned g->sec2->flcn to point to g->sec2_flcn to access falcon. -Made Makefile changes to include sec2.c to build JIRA NVGPUT-80 Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791955 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: SEC2 RTOS interface headersMahantesh Kumbar2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | -Created command/message nv_flcn_cmd/msg_sec2 data struct to communicate between nvgpu<->sec2-rtos in header file sec2_cmd_if.h -Created acr command/message nv_sec2_acr_cmd/msg to perform operation like bootstrap LSF flacon in header file sec2_if_acr.h -Created defines common SEC2 defines to use across multiple operation related to SEC2-RTOS in header file sec2_if_cmn.h -Created data struct sec2_init_msg_sec2_init to receive message from SEC2-RTOS to init queues, debug data in header file sec2_if_sec2.h JIRA NVGPUT-81 Change-Id: I4efbca20de7a2483d17de97841ada5336189e2b8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827806 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: Explicitly use signed typesAlex Waterman2018-09-27
| | | | | | | | | | | | | | | | | | | Explicitly use signed types in the sXX typedefs. C implementations are apparently free to use either signed or unsigned as the default for types like char. JIRA NVGPU-1234 Change-Id: I0a37025b42d0ecb42ca90f29d3c3b70cf8cc807d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1846179 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Philip Elcan <pelcan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 20:47:22 -0400