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* gpu: nvgpu: Fix offset units in PRAMIN codeAlex Waterman2017-08-14
| | | | | | | | | | | | | | | | | | The offset units in the nvgpu_pramin_access_batched() code changes midway through the function. In the first section it is treated as bytes but then in the while-loop iterating over the PRAMIN window and page_alloc_chunks it becomes an offset in words. This patch leaves the offset field in bytes and converts to words where needed. Change-Id: Iba964171679dfc27645238b297ed467a450b5cbc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537079 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix length passed to VIDMEM mapAlex Waterman2017-08-14
| | | | | | | | | | | | | | | | | | The call to __set_pd_level() for vidmem allocs had the wrong length being passed in. This was a silent error since the subsequent __set_pd_level() calls overwrote the bad mappings. However this caused significantly more PDE/PTE writes than necessary since each chunk could be mapped N times where N is the number of chunks in an SGL. Change-Id: Ied7247b70825dc91b9eea1c3350f4ef370ab1a52 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537078 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: shorten PTE debug printAlex Waterman2017-08-14
| | | | | | | | | | | | | If the debug message printed to the Linux kernel is too long then the end of the message gets truncated. This causes loss of valuable PTE information. Change-Id: I05e890819ec176c6aa909b04352e8a40f1936ecf Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537077 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: Fix up qos/sysfs limitsSai Gurrappadi2017-08-11
| | | | | | | | | | | | | | | | | | | | | | | | Userspace sysfs limits devfreq->{min|max}_freq and pmqos min/max limits are treated as the same priority. In case these two ranges don't intersect prefer the max_freq clamp over the min_freq clamp. This is done in order to ensure any thermal throttling isn't bypassed by a userspace sysfs write. MaxQ/MaxP configurations only care about the Fmax limit and not necessarily Fmin, so preferring max_freq over min_freq is consistent with what is required. Bug 1933216 Change-Id: Ie8685306f10dee0f8d340c4b8e0eae533dbfc6ac Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1535937 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Aaron Huang <aaronh@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: remove kind map inheritance"Sunny He2017-08-11
| | | | | | | | | | | | Conflicts with gv100 changes This reverts commit 83e49b39181a86d32f6350c65659b5892f8f7670. Change-Id: Ic5720fd3c214fa306645fb628a28ecf7d6d0c26d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537673 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* Revert "gpu: nvgpu: Reorg fb HAL initialization"Sunny He2017-08-11
| | | | | | | | | | | | Conflicts with gv100 changes This reverts commit 63b74d4b768e0c96367d4983fdd8f1db1d317d01. Change-Id: I5e6a1c93ff613daaa100dee436f4941af74f0ac4 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537671 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* Revert "gpu: nvgpu: Reorg mm HAL initialization"Sunny He2017-08-11
| | | | | | | | | | | | Conflicts with gv100 changes This reverts commit 8d63cd3995d4a650b478ad69d7e29ed2b1b2d927. Change-Id: Ie2f88d281b2b87a9a794d79164a61c4d883626b7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537668 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* gpu: nvgpu: Reorg mm HAL initializationSunny He2017-08-11
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I289284e6e528fc7951c959c8765ccf9349eec33b Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533351 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg fb HAL initializationSunny He2017-08-11
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ib746798b849810401c12abf5e9cce42d827c6fb1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533350 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove kind map inheritanceSunny He2017-08-11
| | | | | | | | | | | | | | | | | | | | Currently, the kind map initialization inherits from earlier chips' kind map definitions and simply adds on newly supported features. This is dangerous as changes in older architectures may affect newer architectures in unpredictable ways. This patch removes inheritance between subsequent architectures' kind map initializations. Jira NVGPU-74 Change-Id: I21951c0920f69ced73088cb6670ca1894159c7b9 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533349 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PG503 supportDavid Nieto2017-08-11
| | | | | | | | | | | | Adds basic PG503 support allowing devinit to complete. JIRA: EVLR-1693 Change-Id: Ice8a9ba18c8bba11f6bc174ba2c2d8802a738706 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1532746 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove railgate lock from gm20b_tegra_postscaleDeepak Nibade2017-08-11
| | | | | | | | | | | | | | | | | | | | | | | | In gm20b_tegra_postscale(), we use platform->railgate_lock to check if GPU is railgated or not But platform->railgate_lock was introduced only to prevent unrailgating in midst of gk20a_do_idle() sequence This lock is not the right way to check railgate status since it is still possible to railgate GPU with this lock being held Hence remove acquire/release of platform->railgate_lock from gm20b_tegra_postscale() Bug 1962265 Change-Id: I6208063de3fa77ed71e8fb0c011367fb66151193 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536573 (cherry picked from commit 68bce66be338e48f4921f645b10b3fa5994fe1d4) Reviewed-on: https://git-master.nvidia.com/r/1537297 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: fix pbdma_id searching when init engine infoRichard Zhao2017-08-11
| | | | | | | | | | | | | | The searching loop should break once find a match. Jira VFND-3797 Change-Id: I43ef553a3e90afb00ee9a4df7d269b7c6616b18e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1535304 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix debugfs to disable big pagesThomas Fleury2017-08-07
| | | | | | | | | | | | | | | | | | | | | After setting 'Y' in disable_bigpage, in native SMMU case, we could still see 64K GMMU pages beeing used. Fixed the following: - enforce disable_bigpage in nvgpu_vm_map - update GPU characteristics so that new clients know whether or not big pages are enabled. For instance this may affect how CUDA requests memory mapping. JIRA EVLR-1694 Change-Id: I62841096add3bd798c5c11090054f82c8a2be832 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1532429 Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Increase small page apertureAlex Waterman2017-08-07
| | | | | | | | | | | | | Increase the small page aperture to 56GB to facilitate easier fixed address mapping for userspace (primarily CUDA). Bug 200320732 Change-Id: I1f0aaa4f28c8a294cc880b35f26942b562396b48 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1502432 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove mm.get_iova_addrAlex Waterman2017-08-04
| | | | | | | | | | | | | | | | | | | | | | Remove the mm.get_iova_addr() HAL and replace it with a new HAL called mm.gpu_phys_addr(). This new HAL provides the real phys address that should be passed to the GPU from a physical address obtained from a scatter list. It also provides a mechanism by which the HAL code can add extra bits to a GPU physical address based on the attributes passed in. This is necessary during GMMU page table programming. Also remove the flags argument from the various address functions. This flag was used for adding an IO coherence bit to the GPU physical address which is not supported. JIRA NVGPU-30 Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530864 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Pass struct gk20a to gk20a_wait_for_idle()Terje Bergstrom2017-08-04
| | | | | | | | | | | | Pass struct gk20a pointer instead of struct device to gk20a_wait_for_idle(). The code is not Linux specific and does not need pointer to struct device. Change-Id: I2cafd6c7db019c9de76b6e68a1ae73f0b4cea37d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533173 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Remove unnecessary use of ACCESS_ONCE()Terje Bergstrom2017-08-04
| | | | | | | | | | | | | | | ACCESS_ONCE() is used for making sure that in a given place of code access a variable exactly once. It prevents compiler rearranging the read from happening earlier. Remove its use from cases where rearranging of the read does not create problems. Change-Id: I340f375e8fecc31f3a3fab543256069cb4c682dc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1531649 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Pass gk20a to XVE initTerje Bergstrom2017-08-04
| | | | | | | | | | | Pass gk20a pointer instead of struct device pointer to XVE init. Change-Id: I5f5efc1d09430a45a49321830b1d7f17c7a57e2f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528264 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move debugfs fields to os_linuxTerje Bergstrom2017-08-04
| | | | | | | | | | | | | Move all Linux specific debugfs dentry fields to struct nvgpu_os_linux. JIRA NVGPU-62 Change-Id: I615620005f5d042943dd2e478c1629bcc912c550 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528263 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make LTC disabling common codeTerje Bergstrom2017-08-04
| | | | | | | | | | | | | | | | | | Refactor the sync_debugfs LTC HAL op so that the logic to enable or disable LTC goes to common code nvgpu_ltc_sync_enabled() and the LTC HAL set_enabled only performs the hardware register access. Create a new common function nvgpu_init_ltc_support() to initialize the LTC software variable, and move hardware initialization of LTC to be called from it. JIRA NVGPU-62 Change-Id: Ib1cf4f5b83ca3dac08407464ed56a732e0a33923 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix warnings for GPUs with real vidmemPeter Daifuku2017-08-03
| | | | | | | | | | | | | | | | | | | | | Fix kernel warnings for GPUs with real vidmem: - dma.c: in nvgpu_dma_alloc_flags, ignore incoming flags when using vidmem, since anything but NVGPU_DMA_NO_KERNEL_MAPPING will end up generating kernel warnings, and the vidmem mapping functions ignore the other flags anyway. - gmmu.c: in __nvgpu_gmmu_update_page_table, use appropriate function for memory type to retrieve physical address Bug 1967748 Change-Id: I6fc01fd5f2c5cd7b81cba70ab59cc3c8fe4cda19 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530877 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move isr related fields from gk20aTerje Bergstrom2017-08-03
| | | | | | | | | | | | | | | | | Move fields in struct gk20a related to interrupt handling into Linux specific nvgpu_os_linux. At the same time move the counter logic from function in HAL into Linux specific code, and two Linux specific power management functions from generic gk20a.c to Linux specific module.c. JIRA NVGPU-123 Change-Id: I0a08fd2e81297c8dff7a85c263ded928496c4de0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528177 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Reorg clk HAL initializationSunny He2017-08-02
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the clk and clk_arb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I553353df836b187b8eac61e16b63080b570c96b8 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1511076 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg regops HAL initializationSunny He2017-08-02
| | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the regops sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7e2ccf158a8e7efa453a3326e86146660f18926f Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530135 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Tested-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use non-contig mem in pd_cacheAlex Waterman2017-07-31
| | | | | | | | | | | | | | | | | | | | | In the PD caching code use a non-contiguous DMA alloc for PAGE_SIZE and below allocations. There's no need for using the special contig pool of mem for these page sized allocs so wasting said mem can lead us to OOM problems pretty quickly (think large sparse textures, for example). Also turn several pd_dbg() statements for printing OOM errors into nvgpu_err()s since knowing exactly where an alloc fails is very convenient. Bug 200326705 Change-Id: Ib7c45020894d4bdd73cc92179ef707e472714d61 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527294 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support multiple sm for t19xSeema Khowala2017-07-28
| | | | | | | | | | | | Allocate memory for sm_to_cluster to support multiple sm Bug 1951026 Change-Id: I48256f097fbc95e4432950a7e8de62577819a025 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1515778 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: avoid possible ovrflw in dmabuf checkPeter Daifuku2017-07-28
| | | | | | | | | | | | | | | | | | | | In gk20a_vm_map_buffer, when checking dmabuf size, avoid possible overflow of buffer offset + buffer size Bug 1793926 Change-Id: Iaa85bbd2942546015a233f34388309c6ba01412c Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1488051 (cherry picked from commit 62346ede6c0863d36dc5d91527647130a13eff53) Reviewed-on: http://git-master/r/1501696 (cherry picked from commit 745c273ac80fad14f019b7c59bb797c4e22f4781) Reviewed-on: https://git-master.nvidia.com/r/1528182 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg therm HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the therm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic9d03304d3dcde0365cbf22af2dbe1e7eb0e04bb Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527422 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg pramin HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pramin sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I0c0aecfb8f5ea436ef353b874f5e36ff24ebd130 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527421 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg fecs_trace HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fecs_trace sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I84485ad64997270c6a0fce3c95dc9ceb0094cf6c Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527419 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg gr_ctx HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr_ctx sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I783d8e8919d8694ad2aa0d285e4c5a2b62580f48 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527417 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg ce2 HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ce2 sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7dfd5e8dcd4d6f3623d1b795b6b2e15ff356a13a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509632 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check for buffer overflow when mappingPeter Daifuku2017-07-27
| | | | | | | | | | | | | | | | | In gk20a_vm_map_buffer, return an error if the buffer size is less than offset + mapping size. Bug 1793926 Change-Id: I2209de6a6f2e2b3bd8830659208d6f88bbedc00d Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1484442 (cherry picked from commit 7e6a80cb4684a3e2534bc68cba4c1612a845a8f3) Reviewed-on: http://git-master/r/1488138 (cherry picked from commit 3331f6e47f1d214ad6aaf08ae3e7d241e31d6638) Reviewed-on: https://git-master.nvidia.com/r/1501677 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix gr ctx unmap logicAlex Waterman2017-07-27
| | | | | | | | | | | | | The GR context buffers were not being properly unmapped. The awkward VPR vs non-VPR context setup requires some extra checks when determining which nvgpu_mem is associated with what GPU VA (which are tracked separately in a different sized array). Change-Id: I4c7be1c5b7835aea4309a142df5b0bdfaae91e4c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1524689 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check for null priv in channel_releasePeter Daifuku2017-07-27
| | | | | | | | | | | | | | | | gk20a_channel_release can still get called even if the open_channel call failed (e.g., if we ran out of hw chids), in which case priv is null. Check for this case and return if null. Bug 1964531 Change-Id: I48bc88e4dbd88a1c30fc399de629d8f8b344cfd9 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1526544 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* nvgpu: linsim removalWilliam Pierce2017-07-26
| | | | | | | | | | | | | | | Removed multiple tegra_platform_is_linsim if statements because of linsim deprecation. Bug 1903831 Change-Id: I4985b0e56d26db4813e4f4235b25e5cff47745f8 Signed-off-by: William Pierce <wpierce@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1485033 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reset pm status on runtime_resume failSunny He2017-07-26
| | | | | | | | | | | | | | | | | | | | | | If an error occurs during an attempt to perform a runtime_resume, the runtime power management framework sets an error flag that prevents further attempts to resume until the error is cleared. nvgpu currently does not clear the flag, which causes nvgpu to lock up if an error occurs during runtime_resume. This change explicitly sets the device pm status to suspended on error, which clears the error flag so that subsequent attempts to resume will not be blocked. Bug 200324790 Change-Id: I3c875453670d3691ab01cff90ce31e797296662a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1526478 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove privsecurity flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Remove securegpccs flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace securegpccs boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_SECUREGPCCS Jira NVGPU-74 Change-Id: I46430f95063f617531cf0e5aba472051b41f4a9d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514060 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Remove pmupstate flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace pmupstate boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_PMU_PSTATE Jira NVGPU-74 Change-Id: I4e1ba922a48145b1cf3488b6f14fde78107adb5b Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Apply GM20B dfs_det_cal maskAlex Frid2017-07-25
| | | | | | | | | | | | | | | Applied dfs_det_cal field mask when updating DFS external calibration setting to prevent overflow for negative setting (not happening so far with ADC offset always below Vmin, but may be needed if/when ADC fusing changes). Change-Id: I94b415edec84111b957b73ccfc80c1a8640b8e3a Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1504242 (cherry picked from commit 9b8072ffcc02f6684a56609c25d1d77ed0852f7a) Reviewed-on: https://git-master.nvidia.com/r/1525831 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change GPCPLL rev C1 control settingsAlex Frid2017-07-25
| | | | | | | | | | | | | | | | Updated DFS control settings for GPCPLL revision C1 per characterization data. Bug 1942222 Change-Id: Iab5147e13ef70df980d36589328abafd8f5495b8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1502741 (cherry picked from commit 5ea62c9e264de86f6e5a40a7f31054ab31b3196f) Reviewed-on: https://git-master.nvidia.com/r/1525830 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Reorg fifo HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522553 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg priv_ring HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the priv_ring sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I9ebf27619f771262e5dc398b1200d6c19d6aef16 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514102 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg bus HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the bus sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If03303c34d91480d41fc29e66069efd43e970d75 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514660 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg css HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the css sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3bf696e13d359982c964c7bc470500a30555c034 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: support etpc addresses in ext bufferSeema Khowala2017-07-19
| | | | | | | | | | Bug 1960226 Change-Id: Ifdcdff803e96c59b2794170349ec4e2c00406706 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522445 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: support context regoptype for egpc/etpcSeema Khowala2017-07-19
| | | | | | | | | | | | | | | | - add is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops - add gr ops for decode and create egpc/etpc priv addr - add etpc as part of ctxsw_regs JIRA GPUT19X-49 Bug 200311674 Bug 1960226 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Change-Id: I9a8be1804a9354238de2441093b3b136321b7e53 Reviewed-on: https://git-master.nvidia.com/r/1522442 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ctxheader changes for t19xSeema Khowala2017-07-19
| | | | | | | | | | | | | JIRA GPUT19X-49 Bug 200311674 Bug 1960226 Change-Id: I913e0dd16c51db3f92cb44abaf3f3afa1ce46c0e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522444 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:15:41 -0500