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* gpu: nvgpu: GR and LTC HAL to use const structsTerje Bergstrom2015-03-18
| | | | | | | | | | | Convert GR and LTC HALs to use const structs, and initialize them with macros. Bug 1567274 Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590371
* Revert "gpu: nvgpu: Do not wait for FE GO_IDLE"Allen Yu2015-03-18
| | | | | | | | | | | | | This reverts commit ba69a53f2f9ec055d7e61a40352bb9e73ba136be as it's causing regression in boot stress. Bug 200049711 Change-Id: Iacdba4d1b3739fd60c5a289d30f076f60389e453 Signed-off-by: Allen Yu <alleny@nvidia.com> Reviewed-on: http://git-master/r/590634 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Support secure FECS recoveryVijayakumar2015-03-18
| | | | | | | | | | | | | When falcons are secured use PMU commands to reload FECS firmware. Bug 200042729 Change-Id: I09f2472b16dac6a510dba067bce3950075973d5f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552544 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Sync gk20a and gm20b headersTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Synchronize gk20a and gm20b headers. All registers which were added to gk20a are now added to gm20b, and some registers that are unused are removed. Bug 1567274 Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590313 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Enable clocks only if definedTerje Bergstrom2015-03-18
| | | | | | | | | | Enable clocks only if they are defined. This prevents panic in cases where clock does not need to be enabled explicitly. Bug 1567274 Change-Id: I7113c6d874b61acc2646effda9c02d3d1817c531 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Sanitize gk20a_gr_handle_notify_pendingSami Kiminki2015-03-18
| | | | | | | | | | | | | Sanitize cyclestats portion of gk20a_gr_handle_notify_pending() a bit and fix infinite loop and buffer overrun bugs in case of malformed cyclestate element headers. Also, convert WARN_ON:s to gk20a_err:s for malformed headers since they are userspace problems and not worth kernel stack traces. Bug 1566834 Change-Id: I69fbd85efdb042c5f0e745fac55eeff3aee0faa8 Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
* gpu: nvgpu: Split L2 size calculation per chipTerje Bergstrom2015-03-18
| | | | | | | | | | gk20a and gm20b calculate L2 size with different parameters. Split the function for calculating size so that it does not query GPU id. Bug 1567274 Change-Id: I09510c1bf0286c9df125d74e51df322c32bde646 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: create cde context dynamically as neededKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | When the preallocated buffer of cde contexts is full, allocate a new temporary one dynamically. This needs to create a totally new command buffer but fixes possible but rare lockups in case of circular dependencies. The temporary is deleted after the channel job has finished. Bug 200040211 Change-Id: Ic18d1441e8574a3e562a22f9b9dfec1acdf72b71 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/552036 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: add update callback to gk20a channelKonsta Holtta2015-03-18
| | | | | | | | | | | | Add support for a callback function with user data pointer to be scheduled from the end of gk20a_channel_update. The function and its private data are supplied when opening a new channel. Change-Id: Ib6b408855ea60d46a6a114a69c01904703019572 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/552014 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: find unused cde context instead of lruKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | When preparing a new job, loop initially through the small number of preallocated contexts and try to find one that is already finished, instead of blindly getting the next slot in lru order. If all have work to do, select next in lru order. This reduces the possibility of a deadlock between cde tasks. Bug 200040211 Change-Id: Ib695c0a8e1bcec095d50ec4f2522f3aad39ce97b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/552035 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Set page size for generic gpuTerje Bergstrom2015-03-18
| | | | | | | | | | Default page size was made configurable. Set the page size for generic GPU, too. Bug 1567274 Change-Id: I7aa2762e0f542ec7de68e588afb9c51a6443b44f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix build without Tegra clk frameworkTerje Bergstrom2015-03-18
| | | | | | | | | | | | Do not build clock code if TEGRA_CLK_FRAMEWORK is not defined. Also make GK20A_DEVFREQ depend on TEGRA_CLK_FRAMEWORK, and build scaling governor only if GK20A_DEVFREQ is enabled. Bug 1567274 Change-Id: I6ea1462e7a110fb46c9d66ceda71167cff19699e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/562475
* gpu: nvgpu: VM size should be u64Terje Bergstrom2015-03-18
| | | | | | | | | VM size should not depend on CPU architecture. It should be always u64. Change-Id: I81539807f6674877fd04f0079b2bec05b2a0640d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/562466
* gpu: nvgpu: Fix build break with no PM runtimeTerje Bergstrom2015-03-18
| | | | | | | | | | Bug 1567274 Change-Id: I6ca10e329a46edf859f5b22f18d0da9bc8f41cd6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/562474 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Add ioctl to create new TSGTerje Bergstrom2015-03-18
| | | | | | | | | Add ioctl to nvhost-ctrl to create a new TSG. Bug 200042993 Change-Id: Icdd0edb1d9e374740ace6da9eb3a10c57c62617a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: select ucode boot init by signatureKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | | | | Compute a signature checksum for ctxsw ucode boot section and determine the format of boot initialization data by it. This unifies gk20a and gk20b ucode segment loading a lot by separating the bootloader loading logic to separate functions. Note: Whenever the boot segment binary changes, its updated signature must be added here. Management of different bootloaders must be supported for repo-crossing staging issues. Bug 1519397 Change-Id: I96f9b905d3631dfdebf71ea3a652a0968615fd0a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/556679 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove get and put client routinesKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gk20a_get_client() and gk20a_put_client() routines are effectively dead code. The GPU has been using pm_runtime for reference counting whether the device should be turned on or off, and gk20a_get_client() and gk20a_put_client() have had no positive effect on the behaviour. In worst case these functions trigger some issues as they may trigger code paths that should not be run. There is also a race between get/put and busy/idle. This patch removes the functions and reworks as_gk20a.c to correctly use gk20a_busy()/gk20a_idle() where put/get was required. Additionally, finalize_poweron() is moved to gk20a_busy(), similarly as it was with gk20a_get_client(). If pm_runtime is not in use, the device is only powered on and never off. Currently this affects vgpu power management since it does not use pm_runtime yet. Bug 1562096 Change-Id: I3162655f83457e9caccd9264eed36b5d51e60c52 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/414998 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: allow building as a separate moduleKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | Include object files of gk20a, gm20b and vgpu in the same composite object nvgpu.o in the top-level makefile, and remove the old makefiles. This helps in building the driver as a separate module. Bug 1476801 Change-Id: I93531c0f1a20e46904a429e492f8ed32e4f0c4a1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/557971 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not wait for FE GO_IDLETerje Bergstrom2015-03-18
| | | | | | | | | | | We do not need to wait for FE GO_IDLE counter to go to zero between SW bundles. Bug 1560770 Change-Id: I4cf53ea4e64b7244c589409d66c67ce8afb4a8d5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/558305
* gpu: nvgpu: Protect GM20b clock init from div-by-0Alex Frid2015-03-18
| | | | | | | | | | | | Protected GM20b clock initialization from div-by-0 in case when safe fmax at Vmin is not known, and the respective interface returns zero. Change-Id: I2064a3182c93f283c7e85c247601203dd1f71af4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/559059 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* dvfs: tegra21: Rename thermal safe maximum frequencyAlex Frid2015-03-18
| | | | | | | | | | Renamed field and function operated on thermal safe maximum frequency to make it clear that it is fmax at Vmin (not global fmax). Change-Id: Ie2b5234e87dc5dc03ccdaeb2916f0b776e56b640 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/559058 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Do not init interrupt maskTerje Bergstrom2015-03-18
| | | | | | | | | | Interrupt mask init state is correct, so do not touch it. Bug 1567274 Change-Id: I70673e406944823bd1cbfeee93ec75ce1e1af5da Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/558292
* gpu: nvgpu: vgpu: Fix vgpu mm code build breakTerje Bergstrom2015-03-18
| | | | | | | | | | | | Some fields were moved to vm specific fields from global mm fields. Fix vgpu's mm code to follow that. Zero page is never allocated in vgpu, so don't free it. Change-Id: Ieabb33f1f004c9ffeeceabf61029b5bafc391889 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/559818 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: remove register from whitelistKirill Artamonov2015-03-18
| | | | | | | | | | | | | | | Userspace access to gr_pri_bes_crop_hww_esr removed on Tegra platform. Remove gr_pri_bes_crop_hww_esr register from gk20a whitelist. bug 1456562 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: Id9c3f85e39c970182283a0cdbb87ac5b6b83a534 Reviewed-on: http://git-master/r/553636 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cde: set err properly in oom conditionKonsta Holtta2015-03-18
| | | | | | | | | | | | When gk20a_gmmu_map runs out of memory, set the error code before returning early, so that caller knows about that cde load didn't succeed and wouldn't use the bad context. Change-Id: I1e166c78e39f07df941a29fc4e392a853d97a5c6 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/557273 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement 64k large page supportTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Implement support for 64kB large page size. Add an API to create an address space via IOCTL so that we can accept flags, and assign one flag for enabling 64kB large page size. Also adds APIs to set per-context large page size. This is possible only on Maxwell, so return error if caller tries to set large page size on Kepler. Default large page size is still 128kB. Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Common VM initializerTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | Merge initialization code from gk20a_init_system_vm(), gk20a_init_bar1_vm() and gk20a_vm_alloc_share() into gk20a_init_vm(). Remove redundant page size data, and move the page size fields to be VM specific. Bug 1558739 Bug 1560370 Change-Id: I4557d9e04d65ccb48fe1f2b116dd1bfa74cae98e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove unused symbolsTerje Bergstrom2015-03-18
| | | | | | | | | Remove unused symbols in platform file and gk20a.c. Bug 1558739 Change-Id: If160a75061ecb4ad9cbc4abfb9bc409457299738 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gk20a: Moved bind fecs to init_gr_supportMahantesh Kumbar2015-03-18
| | | | | | | | | | | | | | | -Moved bind fecs from work queue to init_gr_support. -It makes all CPU->FECS communication to happen before booting PMU, and after we boot PMU, only PMU talks to FECS. So it removes possibility to race between CPU and PMU talking to FECS. Bug 200032923 Change-Id: I01d6d7f61f5e3c0e788d9d77fcabe5a91fe86c84 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/559733
* gpu: nvgpu: gk20a: Fix non static symbolAmit Sharma2015-03-18
| | | | | | | | | | | | | Fixed sparse non static symbol warning by making the following symbol 'static': - to_gk20a_sync_pt - to_gk20a_timeline Bug 200032218 Change-Id: Ie0310116aa1500ae8e4838b8a9ad4943a61cfc24 Signed-off-by: Amit Sharma <amisharma@nvidia.com> Reviewed-on: http://git-master/r/552052 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Report error on failed mapSami Kiminki2015-03-18
| | | | | | | | | | | gk20a_vm_map_buffer() used to ignore silently map requests for non-dmabuf fd:s. Fix this by returning the error code from dma_buf_get(). Bug 1566862 Change-Id: If01b03f43b67b17d9fb997d914db871520f50c6e Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
* gpu: nvgpu: gm20b: write gpccs start only onceVijayakumar2015-03-18
| | | | | | | | | | | Writing start bit twice can confuse falcon and results in random behavior. Bug 200040021 Change-Id: I62eb8e4632ac4fc471d931155471084ee0f9d0a4 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: fix issue with rail gating ref countSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | gpu rail gating reference count is going wrong because "can_railgate" is set to false during probe(). For rail-gating to work no gpu re-work is needed and by default rail-gating is enabled with INT_MAX delay. Bug 200044987 Change-Id: I9367275cd18c34cb19a51193353585789ba44c03 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/556568 Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: send ELPG init cmd after GR is readyVijayakumar2015-03-18
| | | | | | | | | | | | bug 200040021 bug 200032923 Change-Id: I5aa7f4efb1b675e9a3faaf73a80452e55cded89e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Change-Id: Ic162902bd2f05abab9ebd37392ed56dc4c164ba8 Reviewed-on: http://git-master/r/539995 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: require mapped buffer be inside vaKonsta Holtta2015-03-18
| | | | | | | | | | When validating buffers to be mapped, check that the buffer end does not overflow over the virtual address node space. Bug 1562361 Change-Id: I3c78ec7380584ae55f1e6bf576f524abee846ddd Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: cde: CDE optimizationsJussi Rasanen2015-03-18
| | | | | | | | | | | | | | | | | -Change cde_buf to use writecombined cpu mapping. -Since reading writecombined cpu data is still slow, avoid reads in gk20a_replace_data by checking whether a patch overwrites a whole word. -Remove unused distinction between src and dst buffers in cde_convert. -Remove cde debug dump code as it causes a perf hit. Bug 1546619 Change-Id: Ibd45d9c3a3dd3936184c2a2a0ba29e919569b328 Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/553233 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Remove usage of KEPLER_C syncpt incrTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | Using KEPLER_C for doing sync point increment has side effects. It adds a SetObject method, which changes channel state that not all user space accounts for. Bug 1462255 Bug 1497928 Bug 1559462 Change-Id: I5c422ad8ca94fba15cad9bd232f7a10d94aa0973 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/554478 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: disable GK20A PMU supportHaley Teng2015-03-18
| | | | | | | | | | | | | | | | GK20A PMU is not supported in GPU client for virtualization. However, to make native case and virtualization case can share same defconfig and kernel image, we need to enable CONFIG_GK20A_PMU and CONFIG_GK20A_DEVFREQ in defconfig. This commit changes to detect if we should disable GK20A PMU support in run time. Bug 200041597 Change-Id: I292c647303ed57af6faa1c5671037ca27b48e31e Signed-off-by: Haley Teng <hteng@nvidia.com> Reviewed-on: http://git-master/r/553653 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu:gm20b: disable irqs when hs pmu executesVijayakumar2015-03-18
| | | | | | | | | | | | | bug 200040021 polling halt irq to check for hs bin completion keep irqs disabled to avoid executing irq handler Change-Id: Ic245d89580444dcbf1cf5ec34bfe0f8b0c5bbc0f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/554659 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Override GM20b RAM SVOP PDP fusesAlex Frid2015-03-18
| | | | | | | | | | | | | | | Override GM20b RAM SVOP PDP fuses with 0x2 setting during clock initialization. Bug 1550997 Change-Id: I9a873b892a2db4af384a9a7af4470562cdcb1572 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499554 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GM20b RAM SVOP PDP fuse registersAlex Frid2015-03-18
| | | | | | | | | | | | Bug 1550997 Change-Id: I25551fdcb9f7d43dc8631305b784aa9c04040139 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Improve error handing in fifoTerje Bergstrom2015-03-18
| | | | | | | | | When initializing fifo, we ignore several error conditions. Add checks for them. Change-Id: Id67f3ea51e3d4444b61a3be19553a5541b1d1e3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/553269
* gpu: nvgpu: dump falcon stats in mmu fault handlerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | If engine status is in context switch in the fifo mmu fault handler, dump falcon stats and gr stats for each engine. Bug 1544766 Change-Id: Idfa9772b7e67072941144ac3bdd73e791fdc2b23 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/553205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: fix build breakAingara Paramakuru2015-03-18
| | | | | | | | | | | | | Switch struct definitions to use nvgpu version instead of nvhost one. Bug 1509608 Change-Id: Id8c1b0c198536766f0399437bdf2c35c6a6bfe85 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/554027 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: calculate zcull_sm_num_rcp using tpc_countDavid Li2015-03-18
| | | | | | | | | | | | old value is for 1 SMs so on gm20b with 2 SMs it resulted in half zcull coverage bug 1553171 Change-Id: I269f9a333a059b2ef533672df63ccaa90b2d00c7 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/500517 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix gpu identification for 3demcSamuel Russell2015-03-18
| | | | | | | | | | | | | | Modify GPU detection in 3demc-bw-ratio to use the SOC Id. Bug 1364894 Change-Id: If52e8c5153e76b29d67d28c52303b095df2e8bf0 Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/542770 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add no-op stubs for vgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | Implement empty or -ENOSYS functions for vgpu if CONFIG_TEGRA_GR_VIRTUALIZATION is not enabled, and remove ifdefs around the calling code. Change-Id: Idc75c9bc486d661786bc222bd9e0380aa7766e78 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/552898 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: support new pmu ucode revisionVijayakumar2015-03-18
| | | | | | | | | | bug 200042729 Change-Id: Ic4b4fa4c25f4017a69355e7f03a3f25d4ce92cff Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552554 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not reset ctxsw & wait for fe_giTerje Bergstrom2015-03-18
| | | | | | | | | | | | | At this stage, ctxsw is always in reset state, because we're powering GPU up, or we have reset the whole GR partition. Remove the code to invoke a second reset. Fix waiting for FE idle. We should wait after each bundle, and break if any iteration fails. Change-Id: I0846f67c6d860a485dea62ff870deafe55a47365 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/552799
* gpu: nvgpu: Update GM20b GPCPLL NA mode settingsAlex Frid2015-03-18
| | | | | | | | | | | | | - Updated DFS_COEFF slope/intercept parameters - Specified VCO control gain - Increased safe DVFS margin to 10% Bug 1555318 Change-Id: I619704b7ba029d77ea1019a86003c3e8d80d04d8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552446 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:06:55 -0500