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* gpu: nvgpu: Fix call to wrong free functionAlex Waterman2017-02-10
| | | | | | | | | | | | | | Fix a mistake in which the wrong free call is used. Bug 1799159 Bug 1823380 Change-Id: I3b60949cabbdb6b4d193c6687657cad606462687 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1283142 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Make sure struct is specifiedAlex Waterman2017-02-10
| | | | | | | | | | | | | | | | Make sure that struct class is at least forward declared so that inclusing nvgpu_common.h can be done from anywhere with no dependencies. Bug 1799159 Bug 1823380 Change-Id: Id8feaa5fd456f7a6e12ed85360d5df28f308faa4 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1283141 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: move pmuif/* to drivers/gpu/nvgpu/include/nvgpuMahantesh Kumbar2017-02-10
| | | | | | | | | | | | | | | | | | Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder to support cross platform feature implementation. Made changes to files which accessed “include pmuif/*” to reflect pmuif/* movement changes. Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files. Jira NVGPU-19 Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1299823 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use upstream function to get chipidShardar Shariff Md2017-02-10
| | | | | | | | | | | | | | Use upstream function tegra_get_chip_id and chip id macros, as downstream function tegra_get_chipid() and chip_id macros is going to be deprecated. This is done as a part to removing duplicate code. Change-Id: I846384955e983a36af0b3501d2b23c47e1d0798c Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1299873 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete PMU fecs override interfaceMahantesh Kumbar2017-02-09
| | | | | | | | | | | | | | | | | | Deleted PMU fecs override interface from pmu_api.h header file as feature not used anymore & its dependent code too. Deleted file pmu_api.h as file dont have any interfaces left inside Jira NVGPU-19 Change-Id: I490cf67ae60ce2f1de37da063199ee04835b940d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297370 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU ACR interface header reorgMahantesh Kumbar2017-02-09
| | | | | | | | | | | | | | | | | Moved ACR interface from pmu_api.h to gpmuif_acr.h header file gpmuif_acr.h - PMU Command/Message Interfaces for Access Control Region (ACR) Jira NVGPU-19 Change-Id: Ic37ff3f4ca069aa4bdd6729bbfccc00e15185b02 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297369 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU perfmon interface header reorgMahantesh Kumbar2017-02-09
| | | | | | | | | | | | | | | | | | Moved perfmon interface from pmu_api.h & pmu_gk20a.h to gpmuif_perfmon.h header files gpmuif_perfmon.h - PMU Command/Message Interfaces PERFMON Jira NVGPU-19 Change-Id: I983f89f0f6ec3b889d975178fb1405f166b7d1b9 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297262 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU PG interface headers reorgMahantesh Kumbar2017-02-09
| | | | | | | | | | | | | | | | | | | | | Moved Power Gating (PG) interface from pmu_api.h & pmu_gk20a.h to gpmuif_ap/pg header files. gpmuif_pg.h - PMU Command/Message Interfaces for power gating (PG) gpmuif_ap.h - PMU Command/Message Interfaces for Adaptive Power Jira NVGPU-19 Change-Id: I1eeee78bdf89d894f9a4731435cdb121f73b1e0f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297203 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: removed static keywordSeema Khowala2017-02-09
| | | | | | | | | | | | | | | Removed static keyword for t19x usage -int gp10b_tegra_get_clocks(struct device *dev); -int gp10b_tegra_reset_assert(struct device *dev); -int gp10b_tegra_reset_deassert(struct device *dev); JIRA GV11B-34 Change-Id: I0bcb02db431b3a11f1b0e40776698c5dd3a9703d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1296847 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable PCI MSI interruptsDavid Nieto2017-02-08
| | | | | | | | | | | | | | Use MSI interrupts instead of legacy on PCIe dGPUs to reduce latency and contention with other PCIe devices JIRA EVLR-986 Change-Id: I6cecc7e62e5797860d42a5bee21e8f4f664e1b18 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1291758 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: Use T186 POWER DOMAIN macrosLaxman Dewangan2017-02-08
| | | | | | | | | | | | | | | | | | The driver file gp10b/platform_gp10b_tegra.c is compiled for T186 SOCs and hence use the T186 power domain macros directly instead of legacy TEGRA_POWERGATE_* macros. This helps in kernel unification to not define the TEGRA_POWERGATE_* bug 200257351 Change-Id: I955c5dd11e6deaaf537377beb6e67a58ab7787ab Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1300524 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gk20a: Remove inclusion of unused headerLaxman Dewangan2017-02-08
| | | | | | | | | | | | | | | The driver file includes <linux/tegra-powergate.h> but does not use anything from this header. Remove this unnecessarily inclusion of header file. bug 200257351 Change-Id: Idc9c79bfdcad0081b1121ec746fcc7a70306adf5 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1300555 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix broken dev-kernel TOTMahantesh Kumbar2017-02-08
| | | | | | | | | | | | | pmu_common.h still referred in gpmuifpmgr.h file causing TOT build failure Jira NVGPU-19 Change-Id: Ie387cdd2f3d2294b0b6b390abfcb2d89dbd322fb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1301218 Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
* gpu: nvgpu: Falcon-controller interface updateMahantesh Kumbar2017-02-08
| | | | | | | | | | | | | | | Moved falcon-controller common interface code from pmu_common.h to flcnif_cmn.h file. Interfaces are common for falcons irrespective of F/W on falcon controllers Jira NVGPU-19 Change-Id: Iad11b2fade8cf6716888773b2b1c23919cbcc07b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1296695 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU interface headers reorganizationMahantesh Kumbar2017-02-08
| | | | | | | | | | | | | | | | | | | | | Moved PMU/Falcon interface which are present in pmu_gk20a.h & pmu_common.h to new files as per feature nvgpu_gpmu_cmdif.h - Top-level header-file that defines the command/message interfaces used to communicate with PMU gpmuif_pmu.h - PMU Command/Message init interfaces gpmuif_cmn.h - Common definitions used by interfaces Jira NVGPU-19 Change-Id: Id8ea6075e4dbba7697036951dcb85487eb861710 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1296415 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add support for EMC freq scalingSrikar Srimath Tirumala2017-02-07
| | | | | | | | | | | | | | | | Add support to do EMC frequency scaling via bwmgr on T210 K4.4. Bug 200267304 Change-Id: Ib01f1a256cfceefc5551e128b7ba8953fafe21d3 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1285001 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
* gpu: nvgpu: implement chip specific init_elcg_modeseshendra Gadagottu2017-02-07
| | | | | | | | | | | | | Added function pointer to implement chip specific init_elcg mode and updated this pointer for legacy chips. JIRA GV11B-58 Change-Id: I3fff4f771eaa5dad98a3d8166c9127ecd6b745e4 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1300120 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix more pmu circular dependenciesAlex Waterman2017-02-07
| | | | | | | | | | | | | | | | Similar to patch 67fc4629892ab60d6335752b93d883ef690f1ea4 fix more circular dependencies arising from #include'ing gk20a.h for no apparent reason. Bug 200192125 Coverity ID 2011397 Coverity ID 2011398 Change-Id: I75bcb3e4e66b680498b0e20d645ab9543aae6697 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1296947 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove ref count from as_shareAlex Waterman2017-02-07
| | | | | | | | | | | | | | | | | Remove the broke ref counting from as_share. The ref-count is incremented for every bind channel but never decremented. This results in VMs never being freed. Bug 1846718 Change-Id: I6253b3eab7c7471d3ed6feddb3705c49a8704bed Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1296900 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Simplify ref-counting on VMsAlex Waterman2017-02-07
| | | | | | | | | | | | | | | | | | | | Simplify ref-counting on VMs: take a ref when a VM is bound to a channel and drop a ref when a channel is freed. Previously ref-counts were scattered over the driver. Also the CE and CDE code would bind channels with custom rolled code. This was because the gk20a_vm_bind_channel() function took an as_share as the VM argument (the VM was then inferred from that as_share). However, it is trivial to abtract that bit out and allow a central bind channel function that just takes a VM and a channel. Bug 1846718 Change-Id: I156aab259f6c7a2fa338408c6c4a3a464cd44a0c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1261886 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not skip errors in gk20a_init_sw_bundleTerje Bergstrom2017-02-07
| | | | | | | | | | | | | | | | | gk20a_init_sw_bundle() has a couple of places where it continues even despite an error is returned. Also it does not check the return value from gops->gr.init_sw_veid_bundle(). Add an error goto label which restores pipeline state. Add gotos to that label for all error cases. Coverity ID 490376 Change-Id: I65338272d2817fa831370c8f070019debbfcd673 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300098 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove self-include of boardobjgrp_e255.hTerje Bergstrom2017-02-06
| | | | | | | | | | | | boardobjgrp_e255.h #includes itself. Remove the recursion. Coverity ID 490376 Change-Id: Ia0bb047cacd0d87f6e2d258ee83d216feb91eaff Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300091 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Make context mapping non-cacheablePeter Boonstoppel2017-02-06
| | | | | | | | | | | | | | | | | | Changes to the context header after the context has been loaded may not be visible to the GPU when mapped as cacheable memory. Examples include updating the preemption modes or boosted_ctx bits at runtime. This patch changes the mapping to non-cacheable. Bug 1819874 Bug 1852094 Bug 200265538 Change-Id: I3b9e87adeaf32e337ec48e01631ad9dea61cc7da Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1297601 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "Revert "nvgpu: gp10b:remove EMC floor when GPU Fmin""Cyril Raju2017-02-06
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 74948b73e3667 ("Revert "nvgpu: gp10b: remove EMC floor when GPU Fmin"") The orginal patch caused instability in GVS and was reverted for unknown reasons.This reverts the revert. Revert patch : http://git-master/r/#/c/1291512/ Original patch : http://git-master/r/#/c/1284572/ Bug 1864117 Bug 1863013 Change-Id: Iaeef74296d0df4bb63d02d567e0d4be63688643a Signed-off-by: Cyril Raju <craju@nvidia.com> Reviewed-on: http://git-master/r/1296294 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add capability for FECS tracingThomas Fleury2017-01-31
| | | | | | | | | | | | | FECS tracing is not supported yet on some platforms (e.g. GM20B), so we need a flag to determine when to run automated tests. Jira EVLR-992 Change-Id: I01a5b2f78612363de44c1f2c17cebaded696f423 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1293350 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: empty FECS buffer on trace enableThomas Fleury2017-01-31
| | | | | | | | | | | | | | | | | | Currently, when reading from ctxsw device node, we are collecting traces that occurred before enabling tracing. This is not wanted, and makes testing unpredicatable. This change drops existing data in FECS ring buffer when enabling traces, as currently done on vm-server side. Jira EVLR-991 Change-Id: Idd2544d4667396f90778b7be82bdf73d1f8b8dc8 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1293303 Reviewed-by: Vishnu Reddy Mandalapu <vmandalapu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: prepare MCLK/GPCLK enumeration changeThomas Fleury2017-01-31
| | | | | | | | | | | | | | | | | | GPC2CLK has been replaced with GPCCLK on user API. Remove related definition from kernel API. GPCLCK and MCLK are currently assigned EQU values in kernel API. We want to move to a simple enumeration as used in nvrm_gpu. During the transition, an alias value will be defined for each clock, and kernel will accept both. Jira DNVGPU-210 Jira DNVGPU-211 Change-Id: I944fe78be9f810279f7a69964be7cda9b9c8d40d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1292593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable PG419 SKU610 probingThomas Fleury2017-01-31
| | | | | | | | | | | | Add PG419 SKU610 compatible device for PCI enumeration Jira DNVGPU-213 Change-Id: Ib2361fa8007b56d852b2e02d27f1c05540f34924 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1285107 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add flag for over power monitoringThomas Fleury2017-01-31
| | | | | | | | | | | | | | | | On PG418, we hard code SW threshold table for over power monitoring. On PG419, there is a dedicated INA for over power monitoring. It is programmed in VBIOS devinit. Added a platform flag to indicate if devinit has already taken care of programming. Jira DNVGPU-206 Change-Id: I28e70ac5621b692864a24e0eadb6d24b9957c0af Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1291813 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Conditional address space unificationAlex Waterman2017-01-31
| | | | | | | | | | | | | | | | Allow platforms to choose whether or not to have unified GPU VA spaces. This is useful for the dGPU where having a unified address space has no problems. On iGPUs testing issues is getting in the way of enabling this feature. Bug 1396644 Bug 1729947 Change-Id: I65985f1f9a818f4b06219715cc09619911e4824b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1265303 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove separate fixed address VMAAlex Waterman2017-01-31
| | | | | | | | | | | | | | Remove the special VMA that could be used for allocating fixed addresses. This feature was never used and is not worth maintaining. Bug 1396644 Bug 1729947 Change-Id: I06f92caa01623535516935acc03ce38dbdb0e318 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1265302 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Cleanup gk20a_init_vm()Alex Waterman2017-01-31
| | | | | | | | | | | | | | | | Cleanup and simplify the gk20a_init_vm() function to ease the implementation of a platform dependent address space unification decision. Bug 1396644 Bug 1729947 Change-Id: Id8487d0e3d3c65e3357e3528063fb17c8a85f7da Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1265301 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Unify the small and large page address spacesAlex Waterman2017-01-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The basic structure of this patch is to make the small page allocator and the large page allocator into pointers (where they used to be just structs). Then assign each of those pointers to the same actual allocator since the buddy allocator has supported mixed page sizes since its inception. For the rest of the driver some changes had to be made in order to actually support mixed pages in a single address space. 1. Unifying the allocation page size determination Since the allocation and map operations happen at distinct times both mapping and allocation of GVA space must agree on page size. This is because the allocation has to separate allocations into separate PDEs to avoid the necessity of supporting mixed PDEs. To this end a function __get_pte_size() was introduced which is used both by the balloc code and the core GPU MM code. It determines page size based only on the length of the mapping/ allocation. 2. Fixed address allocation + page size Similar to regular mappings/GVA allocations fixed address mapping page size determination had to be modified. In the past the address of the mapping determined page size since the address space split was by address (low addresses were small pages, high addresses large pages). Since that is no longer the case the page size field in the reserve memory ioctl is now honored by the mapping code. When, for instance, CUDA makes a memory reservation it specifies small or large pages. When CUDA requests mappings to be made within that address range the page size is then looked up in the reserved memory struct. Fixed address reservations were also modified to now always allocate at a PDE granularity (64M or 128M depending on large page size. This prevents non-fixed allocations from ending up in the same PDE and causing kernel panics or GMMU faults. 3. The rest... The rest of the changes are just by products of the above. Lots of places required minor updates to use a pointer to the GVA allocator struct instead of the struct itself. Lastly, this change is not truly complete. More work remains to be done in order to fully remove the notion that there was such a thing as separate address spaces for different page sizes. Basically after this patch what remains is cleanup and proper documentation. Bug 1396644 Bug 1729947 Change-Id: If51ab396a37ba16c69e434adb47edeef083dce57 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1265300 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use map_offset for PTE size computationAlex Waterman2017-01-31
| | | | | | | | | | | | | | | | | | | | | | Make sure that map_offset is set to the fixed map address or 0) before determining PTE size. Then use map_offset instead of offset_align for computing the PTE size since offset_align could be either an alignment ora fixed mapping offset. Also is the minimum of the buffer size and the buffer alignment for computing page size. This is necessary is the GMMU is doing page gathering (i.e the buffer does not appear as a continguous IOMMU range to the GPU). Is such cases a large page sized buffer may be made up of a bunch of discontiguous 4k pages. Bug 1396644 Bug 1729947 Change-Id: I6464ee6a4ccab2495ccb31cd1ddf1db467d2b215 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1271359 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix priv ring error detectionTerje Bergstrom2017-01-31
| | | | | | | | | | | | | | | | | | | | | Use hardware headers instead of hardcoded register numbers in priv ring. This required updating the priv ring headers to add all the registers and fields needed. Incidentally this also gets rid of a lot of GPC priv ring registers as they're not used in our code. Also delete duplicate prints for the same information. We were dumping GPC error also in gk20a_pbus_isr(), and we dumped master information twice. Dump status of each GPC separately instead of supporting only GPC0. Change-Id: Ic50817ecc50892618fa27947fa83b05148b2cd6a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1295481 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: Prune clock gating listTerje Bergstrom2017-01-31
| | | | | | | | | | | | Prune from clock gating list the entries that target units that do not exist on gp106. Change-Id: I192219a24d8e67de7c1fc25276dfcccbe041a05f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294819 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: Clear timer registers on bus intrTerje Bergstrom2017-01-31
| | | | | | | | | | | | | Clear error address and code from timer registers. This allows following errors to report correctly. Change-Id: I9845ce77347ea7b9231e33f4164098cbb8694ba3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: Reset priv ring properly on errorTerje Bergstrom2017-01-31
| | | | | | | | | | | | | | | | We did not follow the proper sequence to reset priv ring on error. Instead we just re-enabled priv ring, which does not reset anything. Rename the gk20a_reset_priv_ring() to gk20a_enable_priv_ring() to indicate its proper use. Add another gk20a_reset_priv_ring() which actually resets priv ring properly. Change-Id: Ied74465b1215daa447a565b7e9cafef7fbe67d1b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294681 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Propagate pmu initialization failuresDavid Nieto2017-01-31
| | | | | | | | | | | | | | | | | During testing it was detected that a failure in loading the firmware for the driver would not propagate, allowing some function pointers to be left unitialized. This would cause a kernel-crash later on. Bug 1866370 Change-Id: I66056a1d99229d10635293d4c1685f596f197255 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1295376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enb TEGRA_USE_NA_GPCPLL for T210 K4.4Srikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | | T210 K4.4 uses common clock framework instead of Tegra Clock Framework. Fix the config dependency to address this. Bug 200233943 Change-Id: I2ed61153ca9475f895593ca7c22fd9cdcf6f3534 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1266180 Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix DEVFREQ init on T210 K4.4Srikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | | | Devfreq and gpcclk require GPU v/f tables for registering correctly. Fix this by deferring the nvgpu_probe if GPU-DVFS is not completely initialized. Change applicable to kernels with Common Clock Framework enabled. Bug 200233943 Change-Id: I82dadc1b0970d47e839d6bec935330966402e93b Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280832 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow defer probing to workSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | | Platform probe can return a EDEFER_PROBE, perform user init only if platform probe is successful so that all the device objects are created only once. Bug 200233943 Change-Id: If6f41af13c29d070743896f26e6650228153027b Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280831 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use gm20b.gbus instead of gpcclkSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | | DVFS constraints for GPU are applied on gbus not on gpcclk. Make T210 K4.4 use gm20b.gbus to change the GPU clk rates and use its parent clock gbus while querrying DVFS constraints for the GPU. Bug 200233943 Change-Id: I2bad3266d6b8f8f3806a0d4249d9b40308c2ee6a Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1275926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gm20b round rate opsSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | Make the clk_round_rate ops consider the max rate supported by DVFS while calculating the max frequency. Bug 200233943 Change-Id: Ib36a40a29cb16231dd1442aa652a20819e0f4016 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1281552 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gpcclk sw init to probe timeSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | | Move the sw initialization of gpcclk to probe time so that gpcclk is ready to use before first rail ungate. Change is applicable only for platforms with CCF enabled. Bug 200233943 Change-Id: I7b322215041c0b88e9e2a37567af408fbbc31dc1 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280830 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add missing headerSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | Allow NA_GPCPLL to be enabled on T210 K4.4 Bug 200233943 Change-Id: I5ea0b9d1de51b510f5c6671339dee2953bf1ec80 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280829 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix round_rate ops for CCF"Srikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | This reverts commit 34d8421ab4e9ecd0af09f7fefe71b9a1d8781061. Bug 200233943 Change-Id: Id03b7922c955d252aff54e6bbd8163926bdc65fb Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280828 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix gpcclk for K4.4"Srikar Srimath Tirumala2017-01-30
| | | | | | | | | | This reverts commit a918003694984b6fca9e6b6c07fd7cdf3503055e. Change-Id: Idf39cc0946c5c4df82c7c4b6afa225b1f8d5a923 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280827 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Base channel watchdog on gp_getTerje Bergstrom2017-01-30
| | | | | | | | | | | | | | | | | | Instead of checking if a job is complete, only check that channel is making progress by checking its gp_get is advancing. This will make the watchdog conservative. Previously a whole job had x seconds to complete. Now channel has x seconds to get host to consume each push buffer segment. Bug 1861838 Bug 200273419 Bug 200263100 Change-Id: I70adc1f50301bce8db7dac675771c251c0f11b70 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294850 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: add disable_syncpoints debugfs nodeKonsta Holtta2017-01-27
| | | | | | | | | | | | | | | | | | To test semaphore-related bugs with igpus, add a debugfs node called "disable_syncpoints" to override the "has_syncpoints" platform flag. This makes job synchronization use semaphores, for example. NVGPU_GPU_FLAGS_HAS_SYNCPOINTS is still reported in gpu characteristics if the platform supports that, because it is filled in during boot. Jira NVGPU-18 Change-Id: I58c815f896a6054df472f571012c239f1478bf07 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1293972 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 20:39:22 -0400