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* gpu: nvgpu: Add support for FECS ctxsw tracingAnton Vorontsov2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bug 1648908 This commit adds support for FECS ctxsw tracing. Code is compiled conditionnaly under CONFIG_GK20_CTXSW_TRACE. This feature requires an updated FECS ucode that writes one record to a ring buffer on each context switch. On RM/Kernel side, the GPU driver reads records from the master ring buffer and generates trace entries into a user-facing VM ring buffer. For each record in the master ring buffer, RM/Kernel has to retrieve the vmid+pid of the user process that submitted related work. Features currently implemented: - master ring buffer allocation - debugfs to dump master ring buffer - FECS record per context switch (with both current and new contexts) - dedicated device for ctxsw tracing (access to VM ring buffer) - SOF generation (and access to PTIMER) - VM ring buffer allocation, and reconfiguration - enable/disable tracing at user level - event-based trace filtering - context_ptr to vmid+pid mapping - read system call for ctxsw dev - mmap system call for ctxsw dev (direct access to VM ring buffer) - poll system call for ctxsw dev - save/restore register on ELPG/CG6 - separate user ring from FECS ring handling Features requiring ucode changes: - enable/disable tracing at FECS level - actual busy time on engine (bug 1642354) - master ring buffer threshold interrupt (P1) - API for GPU to CPU timestamp conversion (P1) - vmid/pid/uid based filtering (P1) Change-Id: I8e39c648221ee0fa09d5df8524b03dca83fe24f3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1022737 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add support to set channel timesliceAingara Paramakuru2016-03-22
| | | | | | | | | | | | | | | As part of improving GPU scheduling, userspace can now set a channel's timeslice, within reasonable limits imposed by the kernel driver. JIRA VFND-1312 Bug 1729664 Change-Id: I4c3430c43437889b8685f12988d4b967bb7877bb Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1020917 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Provide cpu gpu time correlation via ioctlArul Sekar2016-03-22
| | | | | | | | | | | | | | | | | | | bug 1648908 Provides pairs of CPU and GPU timestamps that can be used for correlatiing the two timebases - IOCTL made available /dev/nvhost-ctrl-gpu Change-Id: I1458b9d33d794b1b02ec9fd29ed9426756b94bcd Signed-off-by: Arul Sekar <aruls@nvidia.com> Reviewed-on: http://git-master/r/1029732 Reviewed-by: Arun Gona <agona@nvidia.com> Tested-by: Arun Gona <agona@nvidia.com> Reviewed-on: http://git-master/r/1111715 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable semaphore acquire timeout only when timeouts_enabled is setRichard Zhao2016-03-22
| | | | | | | | | | Bug 1727687 Change-Id: I7a7a4a2011b029474122fdbfbeb02b6302a5902b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1011486 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable illegal comptag interruptTerje Bergstrom2016-03-22
| | | | | | | | | | | | | | Illegal comptag interrupt is triggered when a page is mapped with two different kinds with incompatible compression status. This can be intentional, so disable the interrupt. Change-Id: I84a212beac147991d09d2d381a9e770b1364f4d8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1029663 (cherry picked from commit 819607a768f9fccdd0b233d58bcf88b9eee4ee19) Reviewed-on: http://git-master/r/1031010 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Clear comptags for whole bufferTerje Bergstrom2016-03-22
| | | | | | | | | | | | Clear comptags for whole buffer when nvgpu sees the buffer for the first time. Change-Id: I67108ce0f0def46ddda1aa9b9bb5ea22549cce13 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1013517 (cherry picked from commit 544446aacdc695dc2e27c42a0086292cd69c2eee) Reviewed-on: http://git-master/r/1031009 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Make use of reset controller optionalTerje Bergstrom2016-03-16
| | | | | | | | | Reset controller is not enabled in all builds, so make its use optional. Change-Id: I88df11d0aae0552eb4c7f3acee5be70885ea2901 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1028348
* gpu: nvgpu: improve channel interleave supportAingara Paramakuru2016-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, only "high" priority bare channels were interleaved between all other bare channels and TSGs. This patch decouples priority from interleaving and introduces 3 levels for interleaving a bare channel or TSG: high, medium, and low. The levels define the number of times a channel or TSG will appear on a runlist (see nvgpu.h for details). By default, all bare channels and TSGs are set to interleave level low. Userspace can then request the interleave level to be increased via the CHANNEL_SET_RUNLIST_INTERLEAVE ioctl (TSG-specific ioctl will be added later). As timeslice settings will soon be coming from userspace, the default timeslice for "high" priority channels has been restored. JIRA VFND-1302 Bug 1729664 Change-Id: I178bc1cecda23f5002fec6d791e6dcaedfa05c0c Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1014962 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: validate wait notification offsetKonsta Holtta2016-03-15
| | | | | | | | | | | | | | | Make sure that the notification object fits within the supplied buffer. Bug 1739182 Change-Id: Ifb66f848e3758438f37645be6f534f5b60260214 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1026431 (cherry picked from commit 2484c47f123c717030aa00253446e8756e1a0807) Reviewed-on: http://git-master/r/1030875 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: validate error notifier offsetKonsta Holtta2016-03-15
| | | | | | | | | | | | | | | | Make sure that the notifier object fits within the supplied buffer. Bug 1739183 Bug 1739932 Change-Id: I713574ce797ffc23cec10b5114f469dbadc68f1e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1026410 (cherry picked from commit f476b93eb19b962b8760457102448bd533efc54d) Reviewed-on: http://git-master/r/1028737 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update slcg/blcg prod setiingsSeshendra Gadagottu2016-03-14
| | | | | | | | | | | | | | | | | | | Add following missing prod settings: blcg bus blcg ce slcg ce2 slcg chiplet slcg gr Bug 1689806 Change-Id: Ic7c9afdb1fc47ad71ca326384f5d2a4528121abe Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1030987 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix a sync_fence leakYunbo Wang2016-03-14
| | | | | | | | | | | | | | Fixes a bug where reference to sync_fence is not closed before return. Bug 200171146 Change-Id: If174eb124bd69692bab4cc8629a103517d7cfef1 Signed-off-by: Yunbo Wang <yunbow@nvidia.com> Reviewed-on: http://git-master/r/1029844 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Eric Miao <emiao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use include for importing T18x MakefileTerje Bergstrom2016-03-14
| | | | | | | | | | Refactor Makefile so that there is only one target. Bug 1476801 Change-Id: If0fe5f787214c9addd51295355e3ae5606e5e8fc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1028349
* gpu: nvgpu: fix Coverity issue of dereferencing NULL return valueDeepak Nibade2016-03-14
| | | | | | | | | | | Coverity id : 20300 Bug 1416640 Change-Id: I43fe2aecd3f1e10d00518c3f9bd19726c17ba778 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1028798 Reviewed-by: Puneet Saxena <puneets@nvidia.com>
* gpu: nvgpu: tegra: fix sparse errorsSeshendra Gadagottu2016-03-14
| | | | | | | | | | | | | | | | | Fixed following sparse errors: - therm_gm20b.c:68:6: warning: symbol 'gm20b_init_therm_ops' was not declared. Should it be static? - platform_gk20a_tegra.c:825:5: warning: symbol 'gk20a_set_clk_rate' was not declared. Should it be static? Bug 200067946 Change-Id: I485d5e76302fb294865854f314db2d27f71520f7 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1026685 GVS: Gerrit_Virtual_Submit Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Reset channel on SM exceptionTerje Bergstrom2016-03-08
| | | | | | | | | | | | | If we receive an exception without debugger attached, trigger a fault recovery. Change-Id: I8c02e37eb7fb0cba2fcb7afed7beb26b86f38d9e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1026003 (cherry picked from commit 526eef512eaed1c6472677eddec051541a939d63) Reviewed-on: http://git-master/r/1026002 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gk20a: FECS BL checksumSupriya2016-03-08
| | | | | | | | | | | | | | | | Update FECS BL checksum Bug 200149721 Change-Id: Icebcf9c0440e88f9018f514804b1e0eeaa7c89cb Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/826772 (cherry picked from commit 634363dc33bc23bf81cee319e68d6dbc8e29a53c) Reviewed-on: http://git-master/r/1026001 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use shift instead of div for comptagTerje Bergstrom2016-03-08
| | | | | | | | | | | | Use right shift instead of division for computing the ctag offset. Bug 1704834 Change-Id: Id57526a08bad34e41b2335a21e299d1c0a2ffba1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1024467 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: disable ELPG while accessing gr_gpcs_tpcs_sm_sch_macro_sched_rThomas Fleury2016-03-03
| | | | | | | | | | | | | | | | | | | | | | | | bug 200139995 Any GR register access should disable ELPG and clock gating before access and enable it back after it is done. Disable ELPG while tweaking perf parameters in gk20a_alloc_obj_ctx. Also output NV_PBUS_INTR_0 in case of interrupt (including fix to display correct value on pbus isr). Change-Id: I81d2eb4461e92fbb33db8554779f6566f6b002c1 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/835307 (cherry picked from commit 6acc35bd1bcc706fbde8d11521cf1d0f64a16fe4) Reviewed-on: http://git-master/r/921299 (cherry picked from commit 73afd520445bb1f4757fd167b38289143fd46d80) Reviewed-on: http://git-master/r/930040 (cherry picked from commit 7a784ebea0dd60a88469f51eaa61c33b356e499c) Reviewed-on: http://git-master/r/1023529 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: LRF, TEX, LTC, DRAM overrideSupriya2016-02-26
| | | | | | | | | | | | - Adding support for FECS mem overrides Bug 1699676 Change-Id: I6c9ddcd98d57b29059513ee508c6f92b194c4fc7 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/921253 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Enable ELPG when disabled due to resetMahantesh Kumbar2016-02-26
| | | | | | | | | | | | | | | | | Enable ELPG back whenever ELPG disable is done due to reset or recovery. Otherwise elpg_refcnt mismatch doesn't engage ELPG correctly Bug 200156347 Bug 1716764 Change-Id: I9284bb52b32fe911bb8eb260f138b616f4a564be Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1020617 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable use_full_comp_tag_line in gpc mmumheyer2016-02-24
| | | | | | | | | | | | | | | | Also GPC MMU needs to have its PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE control bit set. Bug 1730611 Signed-off-by: Mathias Heyer <mheyer@nvidia.com> Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Change-Id: I01e11de066ea5487bf1d9c8c8eddbf159e4882da Reviewed-on: http://git-master/r/1014881 (cherry picked from commit d1651bbebe1b3e46d2173dec1651b3d2f4307b40) Reviewed-on: http://git-master/r/1017459 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: post events on all channels of TSG.Ashutosh Jain2016-02-23
| | | | | | | | | | | | | | | | | | | Raise the SM exception event on dbg fds of all channels as userspace might have registered on only one of the channels. WAR till we fix Bug 200089620 Bug 1724367 Change-Id: I69c20ee9837927c116f350f4bdc70af5e90cd0a8 Signed-off-by: Ashutosh Jain <ashutoshj@nvidia.com> Reviewed-on: http://git-master/r/1012851 (cherry picked from commit 92f7086856bc9e23b39c5f3ceec3130b6407e0d1) Reviewed-on: http://git-master/r/1013813 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: always handle gr exceptionAdeel Raza2016-02-19
| | | | | | | | | | | | Always handle gr exception regardless of whether the SM debugger is attached or not. Bug 1699676 Change-Id: If98ab6948c42d3fb1e4f02d54db12745485b0607 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1013164 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add create_gr_sysfs() function pointerAdeel Raza2016-02-19
| | | | | | | | | | | | | Add create_gr_sysfs() function pointer for creating gr specific sysfs nodes. Bug 1699676 Change-Id: I0a14d3676ebfcd5adebce673e46bdaad8d6aecf7 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1008658 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: skip extracting kind from nvmapDeepak Nibade2016-02-16
| | | | | | | | | | | | | | | | | While mapping the buffer, if kind argument is -1, we extract kind value from nvmap but kind information from nvmap is going away and hence remove respective call to nvmap Bug 1616899 Change-Id: I2764655f60df691ac8a86484c6ec929d2b83b2e3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1012239 GVS: Gerrit_Virtual_Submit Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix read after freeDeepak Nibade2016-02-16
| | | | | | | | | | | | Fix coverity issue of "Read from pointer after free" Coverity id : 20418 Bug 200116059 Change-Id: Id7439986b4380ea427ffedf601455272c4c15a65 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1011296 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: check null when call clk_round_rateRichard Zhao2016-02-16
| | | | | | | | | | | Bug 1726406 Change-Id: Ia03b0a174e92b28c471164cefcde514e6db94bdf Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1002700 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: check timeout for tegra_gr_comm_recvRichard Zhao2016-02-12
| | | | | | | | | | | | | It's preparing for adding timeout in tegra_gr_comm_recv. Bug 1728199 Change-Id: I1e2f647736e4b4cd8c194af2b843e27264ddf4fc Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1011046 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: add characteristics flag NVGPU_GPU_FLAGS_SUPPORT_TSGRichard Zhao2016-02-11
| | | | | | | | | | | | | | | | | NVGPU_GPU_FLAGS_SUPPORT_TSG indicates both the kernel driver and device support time slice group (TSG). Bug 1617046 Bug 200155618 Change-Id: Ib3490a32b773222560c58f1fd6d32bffcb97d6cd Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1010173 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: fix sparse warningsRichard Zhao2016-02-05
| | | | | | | | | | Bug 200088648 Change-Id: I50ad4e75981d2c076a2b0ab14406b72ebabcf34f Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1000173 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: return error for handled intr onlyDeepak Nibade2016-02-05
| | | | | | | | | | | | | | | | | In gk20a_gr_handle_fecs_error(), we always return error value and that triggers recovery in each case Return error only if we need to trigger recovery (depending on case) Otherwise, clear the interrupt and return success Bug 200156699 Change-Id: I117f3702b751e8bbc1cd3834b1b72b6533e246f9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1001694 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable ctxsw_intr1 interruptDeepak Nibade2016-02-05
| | | | | | | | | | | | Enable NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR1 Bug 200156699 Change-Id: I170dd6998381897a4b4ca832774eb0f11f92fd86 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/935772 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: separate API to issue preemptDeepak Nibade2016-02-05
| | | | | | | | | | | | | | Export separate API gk20a_fifo_issue_preempt() to issue preempt request to a channel or TSG Bug 200156699 Change-Id: Ib3b097ef66a6411d75c1fe213cdbe8b1d08d3418 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/935771 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: IOCTL to set stop_trigger typeDeepak Nibade2016-02-05
| | | | | | | | | | | | | | | | | | Add IOCTL NVGPU_DBG_GPU_IOCTL_SET_NEXT_STOP_TRIGGER_TYPE to set next stop_trigger type (either single SM or broadcast to all SMs) Also, expose below APIs to check and clear broadcast flag: gk20a_dbg_gpu_broadcast_stop_trigger() gk20a_dbg_gpu_clear_broadcast_stop_trigger() Bug 200156699 Change-Id: I5e6cd4b84e601889fb172e0cdbb6bd5a0d366eab Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/925882 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move clean up of jobs to separate workerDeepak Nibade2016-02-05
| | | | | | | | | | | | | | | | | | | | | | | | We currently clean up the jobs in gk20a_channel_update() which is called from nvhost worker thread Instead of doing this, schedule another delayed worker thread clean_up_work to clean up the jobs (with delay of 1 jiffies) Keep update_gp_get() in channel_update() and not in delayed worker since this will help in better book keeping of gp_get Also, this scheduling will help delay job clean-up so that more number of jobs are batched for clean up and hence less time is consumed by worker Bug 1718092 Change-Id: If3b94b6aab93c92da4cf0d1c74aaba756f4cd838 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/931701 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cs_data should not be forgottenLeonid Moiseichuk2016-02-03
| | | | | | | | | | | | | | | | | | During poweron/off sequence cyclestats should not remove cs_data and produce leak. Bug 200144583 Change-Id: Ibe1ea7d41d5ba9f79a46ead788a84bed29f37ec6 Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com> Reviewed-on: http://git-master/r/999983 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1001882 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-02-03
| | | | | | | | | | | | | | fix below sparse warning : drivers/gpu/nvgpu/vgpu/vgpu.c:170:27: warning: Using plain integer as NULL pointer Bug 200088648 Change-Id: I5121932140f00cdffe129bb58059251612dce109 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1001516 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: add max freq to gpu characteristicsDeepak Nibade2016-02-02
| | | | | | | | | | Bug 200097029 Change-Id: Id63dad1629b1d1919cbbfb20b0cb85d4855f526d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1000724 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: SM/TEX exception handling supportAdeel Raza2016-01-29
| | | | | | | | | | | | | Add TEX exception handling support. Also make SM exception handler into a function pointer, which should allow different chips to implement their own SM exception handling routine. Bug 1635727 Bug 1637486 Change-Id: I429905726c1840c11e83780843d82729495dc6a5 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935329
* gpu: nvgpu: fix race condition with poweroffSeshendra Gadagottu2016-01-29
| | | | | | | | | | | | | | | | | When gpu rail-gating is enabled, it is possible that both rail gating code and system shudown can start executing gk20a_pm_prepare_poweroff() in parallel. To synchronize this execution, protect gk20a_pm_prepare_poweroff() with a mutex lock. Bug 200168805 Change-Id: I19536a43ed20c3e82b32c316922dc3e19e3f59bb Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/999548 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix wait for sm lock down.Ashutosh Jain2016-01-29
| | | | | | | | | | | | | | | | | | global_esr and warp_esr are edge-triggered and are cleared in kernel isr so skip checking them when wait_for_pause is called from UMD via ioctl. Bug 1619430 Change-Id: I2ae54f23ba5c8bfaab35a476f88ccca0bbb10202 Signed-off-by: Ashutosh Jain <ashutoshj@nvidia.com> Reviewed-on: http://git-master/r/935808 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Cory Perry <cperry@nvidia.com> Tested-by: Cory Perry <cperry@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Increase semaphore countAlex Waterman2016-01-27
| | | | | | | | | | | | | | | | | | | Increase the semaphore count per channel. Some channels were running out of semaphores. The original limit was 255 (256 fits in 1 page, but the 0th semaphore is used to return error codes from the allocator). Easy fix was to simply increase the number of semaphores each channel is allocated to 1024. Bug 1604892 Change-Id: I163e24b8d42a3dc1bb9b418dadc0c8532aff9adb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/935911 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Fix semaphore race conditionAlex Waterman2016-01-27
| | | | | | | | | | | | | | | | | | | | | | A race condition existed in gk20a_channel_semaphore_wait_fd(). In some instances the semaphore underlying the sync_fence being waited on would have already signaled. This would cause the subsequent sync_fence_wait_async() call to return 1 and do nothing. Normally, the sync_fence_wait_async() call would release the newly created semaphore but in the above case that would not happen and hang any channel waiting on that semaphore. To fix this problem if sync_fence_wait_async() returns 1 immediately release the newly created semaphore. Bug 1604892 Change-Id: I1f5e811695bb099f71b7762835aba4a7e27362ec Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/935910 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Fix gk20a_sync_pt_has_signaled()Alex Waterman2016-01-27
| | | | | | | | | | | | | | | | | | Fix a reentrancy problem in gk20a_sync_pt_has_signaled() where one thread could clear a pointer before another thread tried to access it. A spinlock was added to the gk20a_sync_pt struct which is used to ensure that the underyling gk20a_sync_pt data is accessed in a sane manner. Bug 1604892 Change-Id: I270d89def7b986405a3167285d51ceda950c7b82 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/935909 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: set set_sm_debug_mode() for gm20bDeepak Nibade2016-01-27
| | | | | | | | | | | | | | | Set function pointer gops->gr.set_sm_debug_mode() for gm20b Bug 200168107 Change-Id: I40eebbc55b0f82f793fcea90245ae6dad0f5779c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/935773 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add support for therm gate ctrlSeshendra Gadagottu2016-01-27
| | | | | | | | | | | | | During gpu init, therm gate control is required to add delay cycles before clock gating. Bug 1717152 Change-Id: Ifabc428cf7b49e49964dc994eba2c38af4aa1a91 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/936443 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add channel_set_priority supportRichard Zhao2016-01-25
| | | | | | | | | | | | | | | - add gops.fifo.channel_set_priority and move current code as native callback. - implement the callback for vgpu Bug 1701079 Change-Id: If1cd13ea4478d11d578da2f682598e0c4522bcaf Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/932829 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: let gk20a_fifo_preempt call gops callbacksRichard Zhao2016-01-22
| | | | | | | | | | | | | | | It fixed vgpu regression that vgpu tried to call native channel preemption function. Bug 1617046 Change-Id: Ia5a5486d8b95a34ca6ecc75f8d3b5fea76919405 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/935897 Tested-by: Damian Halas <dhalas@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: pmu version updateMahantesh Kumbar2016-01-21
| | | | | | | | | | | | | | | | | | | | | | - ucode CL http://git-master/r/#/c/935012/ - EXTERR exception for ZBC L2 regsiters access during ELPG entry/exit. FIX : ZBC L2 is not part of GR, so ZBC L2 rigsters save/restore not required for ELPG entry/exit, P4 CL 20360931 - 10 msec as GR_FECS_SUBMIT_METHOD_TIMEOUT_US, P4 CL 20313730 - keep disabled ELCG till Clear DAT_RESTORE interrupt at ELPG exit path, P4 CL 20313676 Bug 1712507 Bug 200166877 Change-Id: I2c9843cfd18cd3b513ee6587d1a79e7034b19cae Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/935019 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 20:23:34 -0400