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* gpu: nvgpu: secure boot flag, default disabledMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | - set "privsecurity" to 1 to enable secure boot else set to 0. Bug 200085428 Change-Id: Ia4bf214f4a4bb2573c8869ea2182bbe680f67782 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/729101 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b:inherit gm20b acr init wpr funcMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | -method gm20b_pmu_init_acr() used for gp10b acr init wpr region Bug 200085428 Change-Id: I897aa42b0a8ef7478d4b3f64fe1834532d35b303 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/732213 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Implement new page table formatTerje Bergstrom2016-12-27
| | | | | | | | | Implement the 5-level Pascal page table format. It is enabled only for simulation. Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/682114
* gpu: nvgpu: set zbc format field properlyKonsta Holtta2016-12-27
| | | | | | | | | | | | | Add a missing bitmask for clearing existing bits before setting a new value, and shift the value the correct amount. Also format register needs to be rounded down. Bug 200087330 Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/726265
* gpu: nvgpu: gp10b: fix sparse warnings of static symbolDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | Fix sparse warnings of below type by making necessary symbols static: warning: symbol '<symbol>' was not declared. Should it be static? Bug 200088648 Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/728012 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: gp10b: Fix include pathAlex Van Brunt2016-12-27
| | | | | | | | | | Remove the requirement that srcdir is called kernel. Change-Id: I9379ef530ac34009bd0461a29d65d6d707bc8014 Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/728153 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Define compressible page sizeTerje Bergstrom2016-12-27
| | | | | | | | | | | gp10b can compress 4k pages. Bug 1605769 Change-Id: I15cf4b9ead0fefdfc430cfc4919dcb16721f5cb2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725794 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Correct steady state CB sizeTerje Bergstrom2016-12-27
| | | | | | | | | | Program steady state CB size to be the HW default. Bug 1626065 Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725106
* gpu: nvgpu: gp10b: Program stream id to LTCTerje Bergstrom2016-12-27
| | | | | | | | | | | Program a constant stream id 31 to LTC. Bug 1610019 Change-Id: I9b5fb794b5ea8da0fba67a2376126d89e056f955 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/724348 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Regenerate HW headersTerje Bergstrom2016-12-27
| | | | | | Change-Id: Id1954b6e96dbc75ab217a4b36a11a0457f9ceef1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/722845
* gpu: nvgpu: add get_iova_addr() for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | Add platform specific gp10b_mm_iova_addr() to get iova/phys address for gp10b If SMMU is not enabled and IO coherence flag is set, set 34th bit in the physical address and return the physical address If SMMU is enabled, return the iova address Bug 1605653 Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713106 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Do not clear compbit store sizeTerje Bergstrom2016-12-27
| | | | | | | | | Do not clear compbit store size if max size is zero. It's already zero at this point. Change-Id: I70d99cfe459fae27d8c1be4aa569ac0717a454d7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720599
* gpu: nvgpu: zbc: disable activity only from ioctlKonsta Holtta2016-12-27
| | | | | | | | | | | | | | Move the fifo engine activity disabling and wait-for-idle from the lowest-level functions higher, into the ioctl path of zbc operations, so that the sw initialization path wouldn't call them. During the init path, the disable isn't necessary, and the code path could result in a deadlock in the fifo runlist mutex. Change-Id: I56e73204e288331165358fc9856390f1eb724488 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715196 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: accessor for memfmt exceptionDeepak Nibade2016-12-27
| | | | | | | | | | | | Add accessor for NV_PGRAPH_EXCEPTION_MEMFMT Bug 200078514 Change-Id: Ibf4ce91dfac12d7f6cffb7c65873696e080ff1a5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/714167 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use mem_desc for buffersTerje Bergstrom2016-12-27
| | | | | | Change-Id: Ia986125bf1a6e06121291f6dde24e580f0a1b61f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712836
* gpu: nvgpu: gp10b: Fix offset for preemption ptrTerje Bergstrom2016-12-27
| | | | | | | | | | Offset for preemption pointer was calculated incorrectly. Bug 1617214 Change-Id: I9c1a9ae24dcd523f4ae17eae0a5b07831839fadb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/716528
* gpu: nvgpu: gp10b: Use gp10b version of phys bitsTerje Bergstrom2016-12-27
| | | | | | | | Use gp10b version of get_physical_addr_bits. Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/714402
* gpu: nvgpu: add exception registers to dumpDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | Add below exception registers to GR dump : NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN Bug 200078514 Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/712481 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix swdx_rm_spill size and pointerKirill Artamonov2016-12-27
| | | | | | | | | | | | | Fixed incorrectly encoded pointer and size. bug 1525327 bug 1581799 Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/713209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add replayable pagefault bufferSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for replayable fault buffer and enable it. Bug 1587836 Change-Id: Iee4ba42ab175c0d72d2c041fdb3ac9d845358847 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/661668 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: support for replayable faultsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | Add support for enabling replayable faults during channel instance block binding. Also fixed register programing sequence for setting channel pbdma timeout. Bug 1587825 Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681703 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: setup mm hw initSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for gp10b specific mm hw init. Bug 1587825 Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update fb headersSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Update fb header with new mmu invalidate fields. Bug 1587836 Change-Id: I33a30dc742f35d325c528a9bc73fea8cfc21e856 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/680800 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update headersSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Sync with latest hw includes and generated header files. Bug 1587825 Change-Id: I165b541e3215245eb43614e34670093b8420a7df Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/709881 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ce interrupt supportSam Payne2016-12-27
| | | | | | | | | | | | | ce interrupts use different register mapping and format from gk20a and gm20b. Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/681646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add ELPG_ENABLE registerTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I8b2272641c7f406cec9bb2649846e4b4b195e21a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/708720 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b specific LTC ISRTerje Bergstrom2016-12-27
| | | | | | | | | | | LTC interrupt register got moved, so use the new offset. Bug 1587638 Change-Id: I3dbd44d92f2bcb3634c21ed46870ec1620d936cf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709571 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Set correct PBDMA signatureTerje Bergstrom2016-12-27
| | | | | | | | | GPFIFO class was set to Maxwell class number. Also implement the PBDMA signature HAL. Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/672921
* gpu: nvgpu: gp10b: Enable warnings as errorsTerje Bergstrom2016-12-27
| | | | | | Change-Id: I86de27309ebecd038a7b32c6f86d87ce0156eb14 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709867
* gpu: nvgpu: reg with FECS HALT methodSupriya2016-12-27
| | | | | | | | Change-Id: Ia196b98c79a71c9545e555260660e274982455a3 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/709279 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: dump GR status registersDeepak Nibade2016-12-27
| | | | | | | | | | | | | Add function pointer gr_gp10b_dump_gr_status_regs() which will enable dumping GR status registers for gp10b Bug 200062436 Change-Id: Iaecc2f9c9364232079bb03e114f68550bd035372 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/678832 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: use tight loop for fecs methodVijayakumar2016-12-27
| | | | | | | | | | | bug 200078367 Change-Id: I9a68e988fa7921276e334c75afa5ee4b15aab464 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/707313 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: headers for linsim CL 34116551Peng Du2016-12-27
| | | | | | | | | Change-Id: Ia8760772b0135813475f96a786484d7caef3759d Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/677464 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: gp10b: Enable debug spewTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I58811bbce0e39b85074f3aa9022a730f696e407e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/679704 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: enable CDE for t18xJussi Rasanen2016-12-27
| | | | | | | | | | | | Mark CDE as supported on t18x. Change-Id: I03c23178712b9018137edddfa8e1ff3a2ad9106c Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/672384 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: read gobs_per_comptagline_per_sliceJussi Rasanen2016-12-27
| | | | | | | | | | | | Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE during t18x ltc init and store it for use in CDE code. Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441 Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/673150 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Compression page size to 64kTerje Bergstrom2016-12-27
| | | | | | | | | Define compression page size for gp10b to be 64k. We also need to copy some LTC initialization code from gm20b to gp10b. Change-Id: I0235c32cdb1486a23d33eb98ebbc79c97a3c32d4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/677837
* gpu: nvgpu: gp10b: Add Bar2 supportSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | Add bar2 support for gp10b and set-up bar2 binding. Bug 1587825 Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/659236 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable replayable fault interruptSeshendra Gadagottu2016-12-27
| | | | | | | | | | Bug 1587825 Change-Id: I6df2f870b4488bb3d5ada52b4819f6f80624becd Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/659092 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: headers for linsim CL 34000094Adeel Raza2016-12-27
| | | | | | | | Change-Id: I43380fda328414e96601e1c03c3e0ec28c0b4871 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/666905 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update headersSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Update replayable page fault fifo, interrupt and bar2 block headers. Bug 1587825 Change-Id: Ifa0d3b640bdd5f3f6fbc7826c1d1edba494340df Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/661117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Enable cycling through ctx binsTerje Bergstrom2016-12-27
| | | | | | | | | | | Remove hard coded NETB for gp10b. This enables cycling through available firmware files. Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/676557 Reviewed-by: Peng Du <pdu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Default page size 64kBTerje Bergstrom2016-12-27
| | | | | | | | | | Set default big page size to 64kB. Bug 1592495 Change-Id: Id23dac012cde75f2809a49779e1a1cee879d08a0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/671705
* gpu: nvgpu: gp10b: Fix L2 size calculationTerje Bergstrom2016-12-27
| | | | | | | | | | L2 size is expressed in kB, so add a multiplier. Bug 1592495 Change-Id: I4c10034cd21bf874c84c96f1adc25261b195063d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/671704
* gpu: nvgpu: gp10b: Enable CILP mode for computeTerje Bergstrom2016-12-27
| | | | | | | | | | | Allow enabling CILP for compute. Set CTA by default. Bug 1517461 Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/661298 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Handle MC pmu interruptsMahantesh Kumbar2016-12-27
| | | | | | | | | | - Made changes to MC to get pmu interrrupts Change-Id: I07aaec8392b1fbb34ae727bc7547a571aaeeb814 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/661212 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gp10b: gpmu elpg supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | Temporally used gm20b elpg sequencing values for gp10b elpg. Bug 1525971 Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/662517 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement gp10b context creationTerje Bergstrom2016-12-27
| | | | | | | | | | | Implement context creation for gp10b. GfxP contexts need per channel buffers. Bug 1517461 Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660236
* gpu: nvgpu: gp10b: Correct SMMU bit numberTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Bit 36 is the correct bit to indicate SMMU translation. Bug 1580756 Change-Id: I761e70265d5981b07940f1d43716416829993827 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/658827 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
* gpu: nvgpu: gp10b: Change order of alpha & betaTerje Bergstrom2016-12-27
| | | | | | | | | Change order of alpha & attribute buffers in CB. The new order follows RM. Change-Id: I2b24daa46055b3bd667a1026c282f74d56882623 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657907
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-29 20:58:49 -0400