| Commit message (Collapse) | Author | Age |
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RXDET is supported only on nvlink 2.2 devices and forward.
Add HAL to run RXDET selectively based on chip. RXDET needs to be
done after the links are out of reset but before any other link
level initialization.
minion_send_cmd is also made non-static to support RXDET
functionality.
JIRA NVLINK-160
Change-Id: Ic65b8dbc7281743f62072089ff3c805521ac9b38
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729525
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We receive bundle with address and 64 bit values from ucode on some platforms
This patch adds the support to handle 64 bit values
Add struct av64_gk20a to store an address and corresponding 64 bit value
Add struct av64_list_gk20a to store count and list of av64_gk20a
Add API alloc_av64_list_gk20a() to allocate the list that supports 64bit
values
In gr_gk20a_init_ctx_vars_fw(), if we see NETLIST_REGIONID_SW_BUNDLE64_INIT,
load the bundle64 state into above local structures
Add new HAL gops.gr.init_sw_bundle64() and call it from gk20a_init_sw_bundle()
if defined
Also load the bundle for simulation cases in gr_gk20a_init_ctx_vars_sim()
Jira NVGPUT-96
Change-Id: I1ab7fb37ff91c5fbd968c93d714725b01fd4f59b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1736450
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This change is required to keep enable USERMODE on QNX as part of gpu
characteristics unification.
Jira VQRM-3996
Change-Id: I9881c8d3a2dfcadf618a56deee847cd9b575ed7b
Signed-off-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1735573
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gk20a_gr_isr(), we handle various errors including GPC/TPC errors.
And then if BPT errors are pending we call gk20a_gr_post_bpt_events() at the
end and pass channel pointer to it
gk20a_gr_post_bpt_events() extracts TSG pointer based on ch->tsgid
But in some race conditions it is possible that we clear the error and trigger
recovery and as a result channel is unbounded from TSG and closed by user space
before calling gk20a_gr_post_bpt_events()
And in that case the code above results in getting incorrect TSG pointer and
hence crashes as below
Unable to handle kernel paging request at virtual address ffffff8012000c08
...
[<ffffff8008081f84>] el1_da+0x24/0xb4
[<ffffff80086e72e0>] gk20a_tsg_get_event_data_from_id+0x30/0xb0
[<ffffff80086e7560>] gk20a_tsg_event_id_post_event+0x50/0xc8
[<ffffff800872922c>] gk20a_gr_isr+0x27c/0x12e0
To fix this extract the TSG pointer before handling all the errors and pass
this pointer to gk20a_gr_post_bpt_events() will post the events if they are
enabled and if TSG is still open
Bug 200404720
Change-Id: I4861c72e338a2cec96f31cb9488af665c5f2be39
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1735415
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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vgpu needs to free the va range besides unmap the syncpt buffer.
Jira VFND-4870
Change-Id: Ia9edb687b66db6da8529bf256d348999e24a0bc3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1693094
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gpu_init_hal(), call NVGPU_NEXT_2_INIT_HAL() if we detect chip
NVGPU_GPUID_NEXT_2
Jira NVGPUT-95
Change-Id: Ie1121591e53a1587766ea03bb62d0aae01d9ccbf
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1734099
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Add g->fifo_eng_timeout_us to define engine timeout in microseconds.
It is initialized with GRFIFO_TIMEOUT_CHECK_PERIOD_US. In RM server
case, it can be overriden with value defined in device tree.
Jira EVLR-2674
Change-Id: I69ac2ce779fe575566c8ba48e8cd2d0e6b2d93cf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1728391
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On GV100, we could not enable reflck repeater at source of PLL
which is shared by link 0/1. So we do not allow link 0 and 1 to
be used on GV100. This refclk repeater is present only on GV100.
Remove the check as we currently use link3 on GV100 and do not
plan to use any other link.
JIRA NVLINK-162
Change-Id: I9ffcc0b20d084a208271d2c594ec64b5bafaabfb
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1734538
GVS: Gerrit_Virtual_Submit
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CAU (Counter Aggregation Unit) registers might be split out from SMPC registers
and moved into their own list on some platforms
In gr_gk20a_init_ctx_vars_fw() add support to check if pm_cau list is available
If list is available, count will be set to non-zero here
In add_ctxsw_buffer_map_entries_gpcs(), parse the pm_cau list if count is
non-zero
Bug 2139870
Change-Id: Ia630e7d03481a6f927c6739d28ebfe49f221326f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1733208
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Support NVC3C0_SET_SHADER_CUT_COLLECTOR s/w method for compute
class. This is needed to enable/disable SHADER_CUT_COLLECTOR_STATE.
Bug 2108381
Bug 2099681
Change-Id: I228dcc55b6df605aeeee094f872157023e3c783c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730634
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Wei Sun <wsun@nvidia.com>
Tested-by: Wei Sun <wsun@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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These macros are sometimes defined by the std library headers.
So when they are defined #undef them and use our own version.
Also explicitly include types.h from gmmu.c since it uses the min
and max macros.
JIRA NVGPU-525
Change-Id: I905ff23ef7a4a96467be59c4a124cb09b63f1f96
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721015
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This function was added for Linux but not for posix. Thankfully the
implementation for posix is trivial: just return false.
JIRA NVGPU-525
Change-Id: Ib5af66dedeabb754ce36cbf6f0351e4af3926c52
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730742
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Removed the reference for $NVGPU/drivers/gpu/nvgpu/common
from Makefile and fixed the include path for the
clockgating headers in HAL files.
Change-Id: I34c179866d28c932501b38184ec18d20dce81480
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730759
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Fixing RM server crash when handles ctxsw timeout. RM server needs to
call its own HAL of .check_tsg_ctxsw_timeout.
Jira EVLR-2691
Change-Id: Ibbc09cbcda39d44dc2a721c9b270d065e13fa9e2
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729900
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add gk20a_fifo_profile_snapshot() to store the submit time in a
profiling entry that was acquired from gk20a_fifo_profile_acquire().
Also get rid of ifdef CONFIG_DEBUG_FS by stubbing the acquire and free
functions when debugfs is not enabled. This reduces some cyclomatic
complexity in the submit path.
Jira NVGPU-708
Change-Id: I39829a6475cfe3aa582620219e420bde62228e52
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729545
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gk20a_mm_debugfs_init() used to initialize one mm-specific debugfs knob,
but now that there aren't any, delete the function and the related
files.
Change-Id: Ic3177945bbab501c506b5199b44c87450df75452
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729530
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Change-Id: I36f2d13ed3797719137c670afef9b644d48ea16e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1727485
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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These intrinsics will be fast for the given platform that the
compiler is targeting. This also reduces complexity in the
code.
Change-Id: I6cfb761d6f881056446fa9a5de53dca50ed93c34
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1727383
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move implementation of bus HAL to common/bus.
Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726337
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The headers use u32 and bool but do not include <nvgpu/types.h>.
Moving around header includes exposed this issue in the cascade
builds.
This patch fixes the problem in all clock gating headers to
avoid this being a concern in the future.
Change-Id: Id56074df393d95bf65baf4062ac811d80d87e96b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729748
Reviewed-by: Bo Yan <byan@nvidia.com>
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The QNX compiler seems to automatically link against this library
and as such the extra -lpthread is not necessary. Instead it
causes a link failure since the pthread library is not present.
JIRA NVGPU-525
Change-Id: Id5a6fcdffb067ed961665a3ee44a9d44301b725b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722157
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Integrity already typedefs these and complains if you override them
even with the same underlying type.
Since we only use these in the regops_gk20a.h header file (outside of
the Linux specific code, that is) this patch just changes the __uXX to
uXX. With that we can delete the now unnecessary __uXX defs.
JIRA NVGPU-525
Change-Id: I01dd2723b68db2170449342f73c711ee5a589adb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721186
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Without this the default fall back includes are the rmos
headers which are obviously not present for the POSUX build.
Change-Id: Iaf7d459e09c62dd57c5b33e21934e40f5780840a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1727427
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Instead of referencing the header from $NVGPU/drivers/gpu/nvgpu/common
reference it from $NVGPU/drivers/gpu/nvgpu. This makes the POSIX
compilation happy since we don't do a -Idrivers/gpu/nvgpu/common.
Not sure exactly why the regular kernbel build does this but it
probably should not.
Change-Id: I00aee373b651e3b7710669fa04c5b75fc1c814d9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1727426
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The number of samples has to be at least the number of percentile ranges
(here 20) for the reporting to work as expected and also to not cause
negative indices in reading the sorted profile data. If there are not
enough samples, just report all zeroes.
Change-Id: Ie893859d95074f5ceabf6abe873941873668861d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721892
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add below two new HALs
gops.fb.enable_hub_intr() to enable hub interrupts
gops.fb.disable_hub_intr() to disable hub interrupts
Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs
Call the HALs everywhere instead of calling the APIs directly
Jira NVGPUT-44
Change-Id: Id299c6d228733ed365a71be6b180186776cc1306
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1725977
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Export below APIs in fb_gv11b.h
gv11b_fb_handle_dropped_mmu_fault()
gv11b_fb_handle_other_fault_notify()
gv11b_fb_handle_mmu_nonreplay_replay_fault()
gv11b_fb_handle_nonreplay_fault_overflow()
gv11b_fb_handle_replay_fault_overflow()
gv11b_handle_l2tlb_ecc_isr()
gv11b_handle_hubtlb_ecc_isr()
gv11b_handle_fillunit_ecc_isr()
Jira NVGPUT-44
Change-Id: Ib50e3f3c2f698d486ffe718ebf4a651ccfe8cd93
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1725976
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Regenerated the gating_reglist.c files for various
chips after fixing the script for MISRA C-2012
violations
Rule 15.5: Multiple points of exit detected
Rule 15.6: "if" body without compound statement
Rule 10.3: Implicit conversions of 64bit to 32bit int
Rule 7.2: Const must be declared with "U"
Rule 5.7: Tags with name xxx already declared
Add preprocessor conditional gaurds in
gating_reglist header files
JIRA NVGPU-671
JIRA NVGPU-656
JIRA NVGPU-688
JIRA NVGPU-686
JIRA NVGPU-644
Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This variable is never used. So remove it.
JIRA NVGPU-525
Change-Id: I7ace77ffe1c2da58d8d9cee3bbbcf8361886bddf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724094
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Before passing in an unsigned value to abs() cast the result
of the subtraction to signed.
In Linux this happens automatically but on non-Linux platforms
abs() does not necessarily do this. clang flags this case as
a pointless operation: abs(x) obviously must equal x for any
unsigned x.
This change should hopefully preserve the Linux behavior but
avoid the compiler warning from clang.
JIRA NVGPU-525
Change-Id: I71320964c0922f1e4890c8b25d801f17e54ed3c0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724093
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The forced PRAMIN reads and writes for sysmem buffers haven't worked in
a while since the PRAMIN access code was refactored to work with
vidmem-only sgt allocs. This feature was only ever meant for testing and
debugging PRAMIN access and early dGPU support, but that is stable
enough now so just delete the broken feature instead of fixing it.
Change-Id: Ib31dae4550f3b6fea3c426a2e4ad126864bf85d2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1723725
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Replace Linux-specific and dubious sched_clock() with common
nvgpu_current_time_ns(). sched_clock() used also nanoseconds.
Jira NVGPU-708
Change-Id: I70f992fe42cc9c3ffed374fdebd582867475e84f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1723202
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add an abstraction over a monotonic system clock in nanosecond units.
Use ktime_get() for the Linux implementation, similarly to
nvgpu_current_time_ms().
Jira NVGPU-708
Change-Id: I3165c20abf2652f1a1fa04e66c04cd34a8fe6dcc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1723201
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Populate gpu rev as 0xa2 for gv11b with t194 A02 soc.
Bug 2053668
Change-Id: I22a2bc7026162e34e9a605dfda3d83fa989b5248
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1713096
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Wei Sun <wsun@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Only for T194 A01 version following invalidates are disabled:
-CBM alpha and beta invalidations for L2
-SCC pagepool invalidates
-SWDX spill buffer invalidates
Bug 2053668
Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680500
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Use the nvgpu/types.h instead of linux/types.h in the clock
gating sources
Jira VQRM-3700
Change-Id: Ib399cc4367c77f0d08454aa7639bb619367f673b
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726782
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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On Tegra platforms that have clock management under BPMP, and do not
support Tegra DVFS, GPU driver cannot access Fmax@Vmin (get interface
always returns "0"). Added such access through BPMP DVFS shim driver.
Bug 2045903
Change-Id: I0222f2e2917cda15d18ea3296dd1fe53b2ea6b45
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added QNX specific include in the common
sim.h
Forward declared "platform_device".
JIRA VQRM-3836
Change-Id: I6e965ccc41df2445b36111d88e9cebf9866dd877
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1725686
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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As part of the MISRA fixes, moving all the
gating_reglist files to common/clock_gating dir,
the new directory structure suggested to follow.
Removed unused gating_reglist files for gk20a
JIRA NVGPU-646
Change-Id: I388855befcf991ee68eeffed10fe9ac456210649
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722330
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The bug was exposed when enable CONFIG_DEBUG_SPINLOCK.
Jira VFND-4943
Change-Id: I01720f93fe6de9b85987d490df852c8d1c8fb1c2
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703656
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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vgpu needs to call nvgpu_init_ltc_support to floor sweep and
set ltc_count.
And set gops.ltc.set_enabled to null as guest is not allowed to change
ltc settings.
Jira VQRM-2345
Change-Id: I83517d631aa947db4a0a4c312f0cecda9ba03973
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703626
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gv100 cannot use idle filter values defined for
gp106 since values are different. Also gv100 cannot
use gv11b idle filter values since prod values are
different between gv100 and gv11b. Finally since
PROD values match with POR INIT values, there
is no need to init idle filters for gv100.
Bug 2115080
Change-Id: I9e7cfbde364d993ae04d80af14650739f32345cc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724060
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Release runlist_lock before issuing runlist update timeout
recovery.
Bug 2115080
Change-Id: I22cd0dd8ab6828412fcc98f587e4a5cdce907651
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722308
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-timeouts will be enabled only when timeouts_disabled_refcount
will reach 0
-timeouts_enabled debugfs will change from u32 type to file type
to avoid race enabling/disabling timeout from debugfs and ioctl
-unify setting timeouts_enabled from debugfs and ioctl
Bug 1982434
Change-Id: I54bab778f1ae533872146dfb8d80deafd2a685c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588690
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Code related to MC module is updated for handling
MISRA violations
Rule 10.1: Operands shalln't be an inappropriate
essential type.
Rule 10.3: Value of expression shalln't be assigned
to an object with a narrow essential type.
Rule 10.4: Both operands in an operator shall have
the same essential type.
Rule 14.4: Controlling if statement shall have
essentially Boolean type.
Rule 15.6: Enclose if() sequences with braces.
JIRA NVGPU-646
JIRA NVGPU-659
JIRA NVGPU-671
Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1720926
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For CDE work a sync fence is always requested, but kernel does not need
it and submit flags from userspace will be passed to the submit function
in cde path so a sync fence will get created if necessary. To reduce
some complexity, remove the explicit boolean in favor of just
NVGPU_SUBMIT_FLAGS_SYNC_FENCE.
Jira NVGPU-705
Change-Id: I8aac85288513ed7cc640acd021d892cee86f41d8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721785
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add below new HALs for bios operations
gops.bios.devinit()
gops.bios.preos()
gops.bios.verify_devinit()
Export existing APIs gp106_bios_devinit() and gp106_bios_preos() and set them
to above HALs on gp106 and gv100
And call new HALs from gp106_bios_init() if supported instead of directly
calling APIs
Jira NVGPUT-48
Change-Id: Ic89f1c86cf6e3e0785b3663fe733b201d6f2f773
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708382
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The mechanism of posting events to userspace is OS specific.
In linux this works through poll fd, wherein we can make use
of nvgpu_cond variables to poll and trigger the corresponding
wait_queue.
The post event functionality on QNX doesn't work on poll though.
It uses iofunc_notify_trigger to post the events to the calling
process. As such QNX can't work with nvgpu_cond's.
To overcome this issue, it is proposed to create OS specific
interface function for posting clk arb events. Linux can call
nvgpu_cond based implementation, which makes sense since these
are already initialized and poll'ed in Linux specific code only.
QNX can implement this interface to call iofunc_notify_*
functions, as per its need.
Jira VQRM-3741
Change-Id: I7d9f71dae2ae7f6a09cd56662003fd1b7e50324c
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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With the removal of rcu locks and using spinlocks in place,
the usage of xchg for atomic pointer swap is unneccesary.
A few places already have barriers in place before changing
the pointer values, so a simple pointer assignment would do.
Jira VQRM-3741
Change-Id: I03296202b273b5175f166ab3e094c0e4de910eb8
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709655
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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currently clk arbiter is using the Linux specific
sched_clock() api for retrieving current timestamp.
Instead use the OS agnostic nvgpu_hr_timestamp().
Jira VQRM-3741
Change-Id: I315ca16327b30db06c39046af1eb05249d1a97ca
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709654
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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