summaryrefslogtreecommitdiffstats
path: root/drivers/gpu
Commit message (Collapse)AuthorAge
* gpu: nvgpu: gv11b: abstract away dma alloc attrsKonsta Holtta2017-03-21
| | | | | | | | | | | | | | Don't use gk20a_gmmu_free_attr because the attrs are embedded in struct mem_desc now. Bug 1853519 Change-Id: Iaa4309d4c2cd334346e09c4fbf15ce826f2ff640 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321314 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: implement is_preempt_pendingSeema Khowala2017-03-21
| | | | | | | | | | | | | | | | | | | preempt completion should be decided based on pbdma and engine status. preempt_pending field is no longer used to detect if preempt finished. add a new function to to be used for preeempting ch and tsg during recovery. If preempt timeouts while in recovery, do not issue recovery. JIRA GPUT19X-7 Change-Id: I0d69d12ee6a118f6628b33be5ba387c72983b32a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1309850 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: init intr_0_error_mask fifo opsSeema Khowala2017-03-20
| | | | | | | | | | | mmu fault is now part of hub interrupt Change-Id: I9ce523d5f11955ac9552510d154eaa2f17a6cbf6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313484 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix stall interrupt enablementSeema Khowala2017-03-14
| | | | | | | | | | | | | Currently priv, pbus and ltc interrupts are enabled as non-stall but being handled in stall isr. Fix is to configure them as stall interrupt. Change-Id: I86adc04f480d5f4befe7e9255b582ce13fa4efc1 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1319018 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add tpc floor sweeping codeseshendra Gadagottu2017-03-14
| | | | | | | | | | | | | | Added TPC floor sweeping code for gv11b. JIRA GV11B-73 Change-Id: Ib0d05e2d606fe13dff119948fbc9022e8af0fa7f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1315257 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: gv11b: support debug dumpSeema Khowala2017-03-09
| | | | | | | | | | | | | | Added dump for pbdma, engine status, channel status and ramfc JIRA GV11B-45 Change-Id: I25442932c61310005fea481455f68ba10c361381 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1302425 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: ltc related changesseshendra Gadagottu2017-03-08
| | | | | | | | | | | | | | | | | | There is no peermem access for gv11b nvlink. So no need to enable peermem access through l2. Implemented gv11b specific ltc_cbc_fix_config function to read correct num_active_ltcs. JIRA GV11B-71 Change-Id: I348ce3bbf42e864341494e386b6f33478badb3a8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1315148 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: trigger mmu fault is not supportedSeema Khowala2017-03-08
| | | | | | | | | | | | | For gv11b fifo recovery, triggering fake mmu fault is not required. JIRA GV11B-7 Change-Id: I6c8c9672085dbbbd77e0d991d840c4cc75c2ab43 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313496 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init is_fault_engine_subid_gpc opsSeema Khowala2017-03-07
| | | | | | | | | | | | | *client_type_gpc_v moved from fifo to gmmu JIRA GV11B-7 Change-Id: Icd28a2ac8c0d0ae212cfca9410dfe781972367df Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313435 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: init fifo ops for device_info_fault_idSeema Khowala2017-03-02
| | | | | | | | | | | | | | | generated hw header for top_device_info_data_fault_id_enum_v is different between legacy chips and t19x JIRA GV11B-7 Change-Id: Ia765be740c419c5b2a61b03104b264c51f1e797e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313383 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: handle l2 related changesseshendra Gadagottu2017-03-02
| | | | | | | | | | | | | | | | | | | Implemented gv11b specific l2 state init and Configured ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info: - cbc_num_active_ltcs is read only for gv11b, so did not write any data to that field. - enforced serilized access to l2 from sysmem and peermem. - nvlink connected peer trafic sent through l2 JIRA GV11B-71 Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1312831 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add gr ops for load tpc maskSeema Khowala2017-03-02
| | | | | | | | | | | | | gr_fe_tpc_fs_r addr is different for t19x Change-Id: Ibae4b7224ffbd4d8366890cd05649b1b66e22f02 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1310327 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update headersSeema Khowala2017-03-01
| | | | | | | | | | | | | | generate headers for pri ring, pbdma intr and gmmu with updated reg generator JIRA GV11B-47 JIRA GV11B-7 Change-Id: Id198fb338c03acc52c523754cfd07db01ff9bffd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1312756 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: reading max veid numberseshendra Gadagottu2017-02-27
| | | | | | | | | | | | | | | | To get maximum number of subctx, sw should read NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of LITTER_NUM_SUBCTX. JIRA GV11B-72 Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1309591 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Use secure PMU reset for GV11B.Deepak Goyal2017-02-24
| | | | | | | | | | | | | | | PMU reset for GV11B is PRIV protected. gp106_pmu_reset() also uses the same register to reset PMU, therefore used same function for gv11b. Change-Id: I633a96256598e73ed02cbdfe0afdb9fba8b76afd Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1303740 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Organize semaphore_gk20a.[ch]Alex Waterman2017-02-13
| | | | | | | | | | | | | t19x version. Bug 1799159 Change-Id: I5e4c2a5341909d2e366ebc15adb4cdce70d695c7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1303264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: gv11b: Remove syncpt protection supportSeema Khowala2017-02-13
| | | | | | | | | | | | | | | In gv11b sync point support is moved to a shim outside of GPU, and gv11b does not support sync points anymore. Remove use of the sync point protection. JIRA GV11B-47 JIRA GV11B-2 Change-Id: I70f3d2ce0cfe016453efe03f2bbf64c59baeb154 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1300964 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b : enable resetSeema Khowala2017-02-09
| | | | | | | | | | | | | | Init below fields in t19x_gpu_tegra_platform -reset_assert = gp10b_tegra_reset_assert -reset_deassert = gp10b_tegra_reset_deassert JIRA GV11B-34 Change-Id: I69cff5621d7fa7de830567f4cce87f79934809e2 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1296909 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b : init gpu clocksSeema Khowala2017-02-09
| | | | | | | | | | | | | | gp10b_tegra_get_clocks called from gv11b_tegra_probe. Also gv11b_tegra_probe is called from nvgpu_probe via function ptr platform->probe JIRA GV11B-34 Change-Id: I782286e191eef84ce41bc65440fbe5ae00995af3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1296840 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gpu: gv11b: Remove inclusion of unused headerLaxman Dewangan2017-02-08
| | | | | | | | | | | | | | | | The driver file includes <linux/tegra-powergate.h> but does not use anything from this header. Remove this unnecessarily inclusion of header file. bug 200257351 Change-Id: Ibbc3c382c31a8c566ed4018fd36d1ffed08bf29e Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1300556 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: chip specific init_elcg_modeseshendra Gadagottu2017-02-07
| | | | | | | | | | | | | | | | | Added thermal registers for gv11b. Implemented chip specific init_elcg_mode. In thermal control register, engine power auto control config is removed and added new field for engine holdoff enable signal. JIRA GV11B-58 Change-Id: I412d9a232800d25efbdb0a40f14949d3f085fb0e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1300119 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: pmu: Assign pmu_queue_get_head/tail ops.Deepak Goyal2017-01-31
| | | | | | | | | | | | | | pmu_get_queue_head/tail & pmu_get_queue_head/tail_size ops are defined for gv11b chip. JIRA GV11B-30 Change-Id: Iae139732d9f68f93e3c197469c04ccd3f0d63ce7 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1285749 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: add regops whitelistsseshendra Gadagottu2017-01-27
| | | | | | | | | | | | Add regops whitelists for gv11b. JIRA GV11B-35 Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1295401 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update zcull and pm pointersseshendra Gadagottu2017-01-27
| | | | | | | | | | | | | | | | | | Update zcull and perfmon buffer pointers in context header. For gv11b maximum 49 bits gpu va possible. But, zcull and perfmon buffer pointers uses maximum 41 bit va address (258 bytes aligned). To accommodate this, high pointer registers needs to be updated in context header. JIRA GV11B-48 Change-Id: Ibe62b6bfedd32c4f3721e4d19d96cce58ef0f366 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1291852 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: gv11b: update clock gating prod settingsseshendra Gadagottu2017-01-27
| | | | | | | | | | | | | Update clock gating setting till HW CL#37750038 JIRA GV11B-15 Change-Id: I98c4a157df979c944122f4a7b05e3e692a28fe2f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1294824 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: HW header update for VoltaAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: restore golden contextseshendra Gadagottu2017-01-20
| | | | | | | | | | | | | | | | Restore golden context correctly with subcontext header. Increase subctx header size to hold complete golden context. Also fill function pointer for freeing context header. Bug 1834201 Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1282440 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Ied87164ea1de793d97a4cc6a754150164af04698 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: sw methods for shader exceptionseshendra Gadagottu2017-01-18
| | | | | | | | | | | | | Added proper sw methods handling of shader execptions for gv11b. Bug 1834201 Change-Id: I3f3a45beed777cc4af59368dccd9dc7bb8181c37 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1283729 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timer API in gv11b's wait_idle()Alex Waterman2017-01-18
| | | | | | | | | | | | | | | | The interface for wait_idle() was changed for gk20a, etc, so this change is necessary to update the wait_idle function for gv11b. Similarly for wait_fe() - this needs to no longer use an end_jiffie argument. Bug 1799159 Change-Id: I192159feffda5476269194e7d6ef15b5fe3055bd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280459 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Support Stencil ZBCSeema Khowala2017-01-18
| | | | | | | | | | | | | | | | | | | | | | | | | Pre-GP10X All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds). Clears for these kinds typically happen in two phases, depth phase and stencil phase. The depth clears can be compressed or ZBC-ed, whereas the stencil part is always uncompressed. Stencil ZBC in GP10X For GP10X both the depth and the stencil data for these packed kinds can be ZBC cleared. A given tile will be a cross product of the following states for depth and stencil. Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0, ZBC index 1 Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2 JIRA GV11B-9 Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1235520 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: gv11b: support for multiple runlistsseshendra Gadagottu2017-01-16
| | | | | | | | | | | | | Add support for multiple runlists in gv11b. Bug 1834201 Change-Id: I5a4cb92643626675314b4b61df330cde06e22c9f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1285044 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: hw header for CL 37750038 and mmu faultSeema Khowala2017-01-12
| | | | | | | | | | JIRA GV11B-7 Change-Id: I32428e6b91050ad3f697eb80e2aabda2cc1bfda4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1249339 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gv11b: Add non secure PMU bootstrap().Deepak Goyal2017-01-05
| | | | | | | | | | | | | | pmu_bootstrap() does not support gv11b PMU non-secure boot. gv11b_pmu_bootstrap function is added with the updated/new args. JIRA GV11B-30 Change-Id: I42c1a7bd77d75c6e59ee4cc695cc879ce7cec095 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1259271 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: hw header update for CL37750038Seema Khowala2017-01-02
| | | | | | | | | | Change-Id: I7ca3d9968dc37b6514a08d3f49b6d2353e11671d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1277786 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add clock gating prod settingsseshendra Gadagottu2016-12-21
| | | | | | | | | | JIRA GV11B-15 Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1266705 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: legacy support with subcontextseshendra Gadagottu2016-12-20
| | | | | | | | | | | | | | | | | gv11b needs atleast one subcontext to submit work. To support legacy in gv11b, currently main context is always copied into subcontext0 (veid0) during channel commit instance. As part of channel commit instance, veid0 for that channel is created and relevant pdb and context info copied to vedi0. JIRA GV11B-21 Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1231169 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: hw header update for CL37510769Seema Khowala2016-12-05
| | | | | | | | | | | Change-Id: Ie25197e9bc08088ff837677d72fa8c28828f0bf4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1263414 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix sparse warningseshendra Gadagottu2016-11-30
| | | | | | | | | | | | | | | | | Fix following sparse warning by making function as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/gr_gv11b.c:1529:5: warning: symbol 'gr_gv11b_setup_rop_mapping' was not declared. Should it be static? Bug 200088648 Change-Id: Idd388170f35e7e6cd7559d8aab8968f7e8e545c6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1261891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: implement mm_setup_hwseshendra Gadagottu2016-11-29
| | | | | | | | | | | | | Reuse gk20a_mm_setup_hw for gv11b. JIRA GV11B-21 Change-Id: I5141dbb8088799a8bd5df55469bc371b63497e96 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254939 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set ce context validseshendra Gadagottu2016-11-21
| | | | | | | | | | | | | | | Set copy engine context valid for channel loaded on pbdma. JIRA GV11B-21 Change-Id: I74445dcefe38b52723705c185e6a37c9f56ac2bf Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254916 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: chip specific init_inst_blockseshendra Gadagottu2016-11-21
| | | | | | | | | | | | | Remove va limits for inst block in gv11b. JIRA GV11B-21 Change-Id: I5338e2d64b3bbebeb5e309d63db3e8360ae05723 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254880 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: support for new littler valuesseshendra Gadagottu2016-11-17
| | | | | | | | | | | | | | | | | Add support for new litter values: GPU_LIT_NUM_SUBCTX GPU_LIT_NUM_SM_PER_TPC Also updated get_litter_value api to use int instead of enum type. JIRA GV11B-21 Change-Id: Ide06245d03743e2d757d27d045701beb25b6707b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254857 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: use fuse control read/write APIs for K4.4Shardar Shariff Md2016-11-11
| | | | | | | | | | | | | | Use fuse control read/write APIs when accessing fuse control registers for Kernel version 4.4 Bug 200243956 Change-Id: I3d78ec2733b5f56615fa0b588664570c85557e63 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245826 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: hw headers for mmu faultSeema Khowala2016-11-07
| | | | | | | | | | JIRA GV11B-7 Change-Id: Ib50c4266a1a9d05b98bf4cbef663b534289055ed Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1249156 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: hw headers for mmu faultSeema Khowala2016-11-03
| | | | | | | | | | | | | JIRA GV11B-7 Change-Id: I9d1a530c668cc3b9e27a6efb4761f68916e85b43 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1246513 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: smid programmingseshendra Gadagottu2016-11-03
| | | | | | | | | | | | | | gv11b specific smid table init, smid numbering and smid programing. JIRA GV11B-21 Change-Id: I3a0f8355f2cd90ab1518cd8a5642a0e84202bdf8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1227096 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add dbg_session_opsseshendra Gadagottu2016-11-01
| | | | | | | | | | | JIRA GV11B-21 Change-Id: Ib9c099fb0f9cf910bd5abfc9fd6010803b52c9f8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1244768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: commit global timesliceseshendra Gadagottu2016-11-01
| | | | | | | | | | | | | | | Implement chip specific commit_global_timeslice function. JIRA GV11B-21 Change-Id: I4f852913cb181f62063084c4e118d97148f99056 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243947 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: pmu HAL updateseshendra Gadagottu2016-11-01
| | | | | | | | | | | | | | | | | Update pmu HAL to have function for is_pmu_supported(). At this moment pmu support is disabled for gv11b. JIRA GV11B-21 Change-Id: I1790e6e4dc80e0761df78e6092da2b6ca0e39d64 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243919 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 08:32:54 -0500