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* gpu: nvgpu; pmu version updateMahantesh Kumbar2016-06-06
| | | | | | | | | | | | | | | | | - P4 CL 20527959 - pmu version update for idle slowdown ucode CL http://git-master/r/#/c/1029404/ - configure LDIV slowdown factor to BY16 using linear slowdown NV_THERM_FPDIV_BY16-0x1e value Bug 200144583 Change-Id: Id15441a88ca980ab3f4f8a70e86cae5e59976829 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1159232 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix calculation of timeoutTerje Bergstrom2016-06-05
| | | | | | | | | | | Fix calculation of timeout in multiple places. The #defines GR_IDLE_CHECK_DEFAULT and GR_IDLE_CHECK_MAX are meant to be used only for defining the frequency of checking for timeout. Using them for actual timeouts makes the timeout really short. Change-Id: I3d0f8cbc91d619be8e5a9168ee1ab1d6298f129b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1158269
* gpu: nvgpu: enable gm204/gm206 GPMU secure bootMahantesh Kumbar2016-06-05
| | | | | | | | | | | | enable gm204/gm206 GPMU secure boot & build. JIRA DNVGPU-11 Change-Id: I3502d227d0baad9e3a27f46d1d6b0d2a83503b6c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1156331 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU support for gm204/gm206Mahantesh Kumbar2016-06-05
| | | | | | | | | | | | | | Adding PMU modules to boot & comunicate with PMU F/W JIRA DNVGPU-11 Change-Id: I5afc9209f70fc13376268f9c94daef6b75527c71 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1156028 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU interface's for gm204/gm206Mahantesh Kumbar2016-06-05
| | | | | | | | | | | | | | Adding PMU interface's to support gm206/gm204 JIRA DNVGPU-11 Change-Id: I55671239cdb44804e7dd740d5e22a54e668005f4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1155940 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add gm204/gm206 ACR BL supoortMahantesh Kumbar2016-06-05
| | | | | | | | | | | | Update ACR BL desc & support for ACR boot. JIRA DNVGPU-10 Change-Id: Iced2e10695439b2e1b47835f5c3c8a5d274e4b1e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1155027 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add context reset at golden context initTerje Bergstrom2016-06-04
| | | | | | | | | | | | | | | | | | Part of golden context initialization is in powerup sequence, and part done as part of first channel creation. The sequence is missing a context reset, which causes initialization of golden context to fail on dGPU. Just moving the code to golden context initialization does not work, because iGPU can be rail gated, and part of the sequence is required in GPU boot. Thus a part of context initialization is replicated to golden context init after a context reset. Change-Id: Ife1b167447018317d3a692b706880e0eda073e43 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1130698
* gpu: nvgpu: WPR & PMU interface updateMahantesh Kumbar2016-06-04
| | | | | | | | | | | | | Update WPR interface & PMU interface to support latest ACR/PMU ucode versions Change-Id: I4d1bd7a5c43751e96c1db58832cd316006d56954 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1158070 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct config for t19xSeshendra Gadagottu2016-06-03
| | | | | | | | | | | | | | | Use TEGRA_19x_GPU config instead of ARCH_TEGRA_19x_SOC for t19x functionality. This config will defined only when gpu repository for t19x is available. Bug 1757988 Change-Id: I53421f31cbed49a2fb24085c150599c78b8158c0 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1158183 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: source t19x specific KconfigSeshendra Gadagottu2016-06-02
| | | | | | | | | | Bug 1757988 Change-Id: I3efc3368cadd83c8334868d19c63f464e4925b27 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1157319 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add t19x functionality conditionallySeshendra Gadagottu2016-06-02
| | | | | | | | | | | | | | Include t19x functionality only when config TEGRA_T19x_GPU is enabled. Bug 1757988 Change-Id: I049f134d92c4ffdeeed2bc513579f7d9d396ff41 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1155297 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: include makefiles conditionallySeshendra Gadagottu2016-06-01
| | | | | | | | | | | | | | Include chip specific makefiles, only if they are present in current source tree. Bug 1757988 Change-Id: I60a468bce6e0d20459aa643ccbce9bacbcd163bf Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1154761 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix TSG abort sequenceDeepak Nibade2016-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_fifo_abort_tsg(), we loop through channels of TSG and call gk20a_channel_abort() for each channel This is incorrect since we disable and preempt each channel separately, whereas we should disable all channels at once and use TSG specific API to preempt TSG Fix this with below sequence : - gk20a_disable_tsg() to disable all channels - preempt tsg if required - for each channel in TSG - set has_timedout flag - call gk20a_channel_abort_clean_up() to clean up channel state Also, separate out common gk20a_channel_abort_clean_up() API which can be called from both channel and TSG abort routines In gk20a_channel_abort(), call gk20a_fifo_abort_tsg() if the channel is part of TSG Add new argument "preempt" to gk20a_fifo_abort_tsg() and preempt TSG if flag is set Bug 200205041 Change-Id: I4eff5394d26fbb53996f2d30b35140b75450f338 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157190 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct APIs for disable and preemptDeepak Nibade2016-06-01
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_ctx_zcull_setup(), gr_gk20a_update_smpc_ctxsw_mode(), and in gk20a_channel_suspend(), we call channel specific APIs to disable/preempt/enable channel But we do not consider TSGs in this case Hence use correct (below) APIs in above functions which will handle channel or TSG internally : gk20a_disable_channel_tsg() gk20a_fifo_preempt() gk20a_enable_channel_tsg() Bug 200205041 Change-Id: Ieed378dac4ad2322b35f9102706176ec326d386c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157189 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update HAL of ACR BLMahantesh Kumbar2016-06-01
| | | | | | | | | | | | | -update HAL of ACR BL which can support gm204/gm206 and DMATRFBASE method to global JIRA DNVGPU-10 Change-Id: I56fc7ce040dadb6473f6f375ee6ce90783a046ad Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1154954 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fixing sparse error/warningMahantesh Kumbar2016-06-01
| | | | | | | | | | | | | | | | | - nvgpu/gm20b/acr_gm20b.c:88:6: warning: symbol 'gm20b_wpr_info' was not declared. Should it be static? - nvgpu/gm20b/acr_gm20b.c:1052:5: warning: symbol 'gm20b_bootstrap_hs_flcn' was not declared. Should it be static? Bug 200067946 Change-Id: I600f06055bd896a88eed5f5549310aa057f86e19 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1156054 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix pid retrieval on tsg resetThomas Fleury2016-05-31
| | | | | | | | | | | | | | | | | | | On engine reset, an event is generate for FECS trace. In case a TSG context is currentlu loaded on GR engine, we retrieve the pid of the TSG from the first channel in the ch_list. Fixed invalid invocation of list_entry that led to crash. Bug 200193891 Change-Id: I79358bbb6685748cde68396ce220ab7b660d414d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1154811 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix timeout on FECS trace flushThomas Fleury2016-05-31
| | | | | | | | | | | | | | | When resetting GR engine flush FECS trace before halting the pipeline. Otherwise FECS remains in sideband method processing loop, and we get a timeout on FECS trace flush Bug 200193891 Change-Id: I137ea20eb1fb4ef6d618cd01cd3c096471eb8fb0 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1155240 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix bug in CHANNEL_FORCE_RESETAingara Paramakuru2016-05-31
| | | | | | | | | | | | | Channels belonging to a TSG did not have their error notifier set correctly. This was due to using an incorrect TSG id. Bug 1617046 Change-Id: Icb6911c7d79a9d02d7713bb47a7cbb24c3098dc1 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1155293 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Free unbound channelsTerje Bergstrom2016-05-31
| | | | | | | | | | | If a channel cannot be allocated a GPFIFO, its status will remain unbound. We still need to free the channel when the fd gets closed. Bug 1769481 Change-Id: I8a9170f431cfa98dcf9e3cbc082393f02d2203db Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1154725
* nvgpu: vgpu: add tsg set interleave supportRichard Zhao2016-05-31
| | | | | | | | | | | | | | | | added a new cmd to support setting tsg interleave level. Bug 1702773 VFND-1492 Change-Id: Idd9b9c59180b156293ddfc4e2b879d0ea6908388 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1145024 (cherry picked from commit 0929ff1089fbc331b07e17073a46fda4086ae785) Reviewed-on: http://git-master/r/1150706 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add tsg set timeslice supportRichard Zhao2016-05-31
| | | | | | | | | | | | | | Bug 1702773 JIRA VFND-1496 Change-Id: Ice570df78d974fa59f2a932caf0e6249b13493a1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144929 (cherry picked from commit 8b6ec996f3773e497a040a8fe4148e01e8dc35fa) Reviewed-on: http://git-master/r/1150705 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add tsg support for vgpuRichard Zhao2016-05-31
| | | | | | | | | | | | | | | | | | - make tsg_gk20a.c call HAL for enable/disable channels - add preempt_tsg HAL callbacks - add tsg bind/unbind channel HAL callbacks - add according tsg callbacks for vgpu Bug 1702773 JIRA VFND-1003 Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144932 (cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7) Reviewed-on: http://git-master/r/1126942 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: manage gr_ctx as independent resourceRichard Zhao2016-05-31
| | | | | | | | | | | | | | | gr_ctx will managed as independent resource in RM server and vgpu can get a gr_ctx handle. Bug 1702773 Change-Id: I87251af61711f0d7997ce90df8a3de196a9b481a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144931 (cherry picked from commit 2efbd143adaf60570121f1c212dc6b6f3d5a1661) Reviewed-on: http://git-master/r/1150704 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add notifier for pbcrc mismatchDeepak Nibade2016-05-31
| | | | | | | | | | | | | | | | | | Add below notifier for pbcrc mismatch NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH And use this notifier value when we have pbdma pbcrc interrupt pending Bug 200179981 Change-Id: I289351e990afb0a4e002902881b99023530f6443 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1156210 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: disable/preempt TSG for hwpm updateDeepak Nibade2016-05-30
| | | | | | | | | | | | | | | | | To update hwpm, we currently disable/preempt only one channel without considering if channel could be part of a TSG Hence, use proper APIs to disable/preempt/enable which will internally handle channel/TSG case Bug 200203191 Change-Id: I329a3c02d635265775f2081abba8e047f491fe7d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1155838 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-05-30
| | | | | | | | | | | | | | Fix below sparse warning : $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pci.c:145:14: warning: symbol 'nvgpu_pci_class' was not declared. Should it be static? Bug 200088648 Change-Id: Ia3e8f1ae426fa72254b5204da0f6f85502b4670c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1155981 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Add device_info_data supportLakshmanan M2016-05-27
| | | | | | | | | | | | | Added device_info_data parsing support for maxwell GPU series. JIRA DNVGPU-26 Change-Id: I06dbec6056d4c26501e607c2c3d67ef468d206f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151602 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use correct IO register pointerTerje Bergstrom2016-05-27
| | | | | | | | | | | | | Use correct IO register pointer in cyclestats code. The code used reg_mem which is not supposed to be used. It is defined only on iGPU. Change-Id: I03cdaf5d2add2bf2c7cc6d7b3c41ac3be0f9a768 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1154708 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: align DMA base in chip HAL methodMahantesh Kumbar2016-05-27
| | | | | | | | | | | | | | | align DMA base in chip HAL method instead in generic method. Bug N/A Change-Id: I47a250380e083f393677b65c13d0c2c894214ca7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1154909 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ELPG init based on flagMahantesh Kumbar2016-05-26
| | | | | | | | | | | | flag helps to enable/disable ELPG init in SW Bug N/A Change-Id: I73eb592b789c2c29db8a75018cbd1617dcf16df8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1152430 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move & rename acr_gm20b to acr_descMahantesh Kumbar2016-05-26
| | | | | | | | | | | | | acr_gm20b renamed to acr_desc to support multiple gpu chips JIRA DNVGPU-10 Change-Id: Ib3b38d5845043f026ddc365a682b7bb454463326 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1152401 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: secure boot HAL updateMahantesh Kumbar2016-05-26
| | | | | | | | | | | | | Updated/added secure boot HAL with methods required to support multiple GPU chips. JIRA DNVGPU-10 Change-Id: I343b289f2236fd6a6b0ecf9115367ce19990e7d5 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1151784 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Validate regops num_ops argumentTerje Bergstrom2016-05-26
| | | | | | | | | | | | Check that num_ops is not too big. We have a hard limit of 1 page allocated for the operations. Bug 200192125 Change-Id: I724039c9dd6e0e93d9df0f5b3a797158fdb5e687 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1132965 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Use kernel bitmap ops for perfmon idsTerje Bergstrom2016-05-26
| | | | | | | | | | Bug 200192125 Change-Id: I44418fbbe393d5b9463dc3c9e62f3673da2a06c5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1132967 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: reorder disable_irqSeshendra Gadagottu2016-05-25
| | | | | | | | | | | | Disable irqs before suspending gpu sub-units. This is to prevent potential races between irq threads and suspend routines. Change-Id: Icc60f517db8ae8129bcf10be53d37d34b6d9242c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1152844 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not reallocate pes_tpc_mask arrayTerje Bergstrom2016-05-25
| | | | | | | | | We allocated a new pes_tpc_mask for each PES on each GPC. This causes us to forget masks for all GPCs but the last one. Change-Id: I825788ad75333d4aecd93c78d1b277c0d9d65f15 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1152703
* gpu: nvgpu: Validate perfmon id countTerje Bergstrom2016-05-25
| | | | | | | | | | | Add a check against a too big perfmon id count. Bug 200192125 Coverity ID 24285 Change-Id: I9b17081a1ea7243e6b57c0a95c59913cd8daf98b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1132966
* gpu: nvgpu: Move PCI devnodes to own directoryTerje Bergstrom2016-05-25
| | | | | | | | | | | | | | | | | | To be able to scan, PCI devnodes need to be in a directory with read permission. By default /dev is read protected by SELinux policy. Move the devnodes to their own directory so that reading this one directory can be allowed. At the same time rename the nodes to start with string "card-". JIRA DNVGPU-54 Change-Id: I0df4ced08afd1f3a468e983d07395ffcb8050365 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1152745 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: change kernel pathPritesh Raithatha2016-05-25
| | | | | | | | | | | | | All kernel versions are getting moved inside $TOP/kernel folder. Changing kernel paths accordingly. Bug 200190733 Change-Id: I0ed2aa6d4ae75e6fc2c3adf4ae541ecb5f4fb9a9 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/1143380 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sridhar Lavu <slavu@nvidia.com>
* gpu:nvgpu:gm20b: update elpg prod settingsVijayakumar2016-05-24
| | | | | | | | | | | | | | | | | | | | | bug 1764398 PGSequencer settings use index to writ to PSORDER register setting. HW has implementation for 28 PSORDER (PSORDER0 - 27). Every write will auto increment index and index will wrap around after it reaches 27. In PROD settings we are writing enable for 0 to 27 and zero for 28 to 65. This overwrites enables written to 0 to 27. Effectively those partitions are never power gated. P4 SWCL# 20744424 Change-Id: I45826e98dd6a84e9c4fe119fbe7ca75acfd8a4ea Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1149055 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add PRAMIN support for mem accessorsKonsta Holtta2016-05-24
| | | | | | | | | | | | | | | | | | | | To support vidmem, implement a way to access buffers via the PRAMIN window instead of just kernel-mapped sysmem buffers for iGPU as of now. Depending on the buffer aperture, choose between the two access types in the buffer memory accessor functions. vmap()/vunmap() pairs are no-ops for buffers that can't be cpu-mapped. Two uses of DMA_ATTR_READ_ONLY are removed in the ucode loading path to support writing to them too via the indirection in addition to cpu. JIRA DNVGPU-23 Change-Id: I282dba6741c6b8224bc12e69c1fb3936bde7e6ed Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1141314 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: suppress prints in submit pathDeepak Nibade2016-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | When we run out of gpfifo space or private command buffer space, we have error spew like below : __gk20a_channel_syncpt_incr: not enough priv cmd buffer space gk20a_submit_channel_gpfifo: fail Dumping these prints to UART cause increase in submit latencies But on these failures, we return -ENOSPC to UMD and then UMD retries the submit, hence it might be unnecessary to dump these prints Hence, remove the error prints of insufficient space and use gk20a_dbg_fn() instead of gk20a_err() to print failure in gk20a_submit_channel_gpfifo() Bug 200202653 Change-Id: I49efd7c6c554dd4fbfa4e66d196eb352e69f92c6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1152378 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix compilation issuesSri Krishna chowdary2016-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | compiling kernel with clang pointed out below issues in nvgpu. Fixing them. gr_gk20a.c:1185:12: error: stack frame size of 3152 bytes in function 'gr_gk20a_setup_alpha_beta_tables' cde_gk20a.c:1376:22: error: duplicate 'const' declaration cde_gk20a.c:1377:22: error: duplicate 'const' declaration cde_gk20a.c:1378:22: error: duplicate 'const' declaration ctxsw_trace_gk20a.c:71:19: error: unused function 'ring_space' platform_gk20a_tegra.c:55:19: error: unused function 'pmc_read' platform_gk20a_tegra.c:60:20: error: unused function 'pmc_write' bug 1745660 Change-Id: I8cd4383cb898307bbeb162ca00b3e20d04de2c90 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/1150486 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add checks for tracing enabledTerje Bergstrom2016-05-23
| | | | | | | | | | | | Add checks for all ctxsw trace functions declared in header. This makes sure chips without tracing support continue to work. Change-Id: Ic658a00821b589a7b770c1fde52afede02dc1c9c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1151918 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add support for gm204 and gm206Terje Bergstrom2016-05-23
| | | | | | | | | | | Add support for chips gm204 and gm206. Adds also support for reading VBIOS and booting devinit and pre-os images on PMU. Change-Id: I4824b44245611e5379ace62793cc37158048f432 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120467 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gk20a: Do not program L2 interruptsTerje Bergstrom2016-05-23
| | | | | | | | | | | | | In gk20a L2 is off when we run L2 floorsweeping function, and the register accesses cause an error. Remove the code to disable L2 comptag interrupt on gk20a. Bug 1741521 Change-Id: I58ee425adf46e80ce4d045750190e930439d419b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1151323
* gpu: nvgpu: Disable big pages for dGPUsTerje Bergstrom2016-05-23
| | | | | | | | | | | | Big pages are not supported by all dGPUs on sysmem. Disable support for all dGPUs for now. Change-Id: I7bdcd9b18845c3d32d40e33220bf9afaf2d8c28e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1150547 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gk20a: fix elpg sysfs controlVijayakumar2016-05-23
| | | | | | | | | | | | | | | | | | bug 200200943 When we enable ELPG through sysfs there is a possibility of refcounting twice as enable ELPG function is done in scheduled work during rail gating exit and also called from sysfs write. Just updating elpg enable/disable flag is good enough as ELPG code uses it during rail gating exit Change-Id: Ibb267d4ce30b9848abcde29882b90d884ef213bb Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1149587 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
* gpu: nvgpu: update trace for sched paramsThomas Fleury2016-05-21
| | | | | | | | | | | | | | Use an inline function instead of a macro to "expand" all channel parameters. Jira EVLR-244 Jira EVLR-318 Change-Id: I4e8c5ee6bc9da36564af171be809f50dd2dfd439 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1150050 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 02:55:29 -0500