| Commit message (Collapse) | Author | Age |
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Make channel_gp10b_commit_userd global, so other
gpus can re-use that function.
JIRA GV11B-11
Change-Id: Ibe03063befc2da6c67822121f880a141cad46e84
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1237738
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We need to wait for scrubber to have finished before we can allow
any accesses to memory. Do the wait in place where on iGPU we would
do FB reset.
Bug 1799537
Bug 1815139
Change-Id: Ic92dee936388a13c4abf0b295fd99581522c430f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235541
(cherry picked from commit 1ef73ecb4e37da042e7117426ab2823b7f4528dc)
Reviewed-on: http://git-master/r/1239955
GVS: Gerrit_Virtual_Submit
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bug 200088648
sparse warning reported that the function was not
defined. This was due to a missing include
Change-Id: Ia6153a2f3348a86e78add95bcfff998505b47cdd
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1237845
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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* Parsing of shadow registers from VBIOS
* Partial devinit engine interpreter implementation
JIRA DNVGPU-117
Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1214956
Reviewed-on: http://git-master/r/1237293
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement gp10b and gp106 ELCG programming.
JIRA DNVGPU-74
Change-Id: Ic0349b948a2870e0d39e95ddd2f49231e7b4cbe0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1220431
(cherry picked from commit d6bc48647982babdf642ea6004d4208c5daa243f)
Reviewed-on: http://git-master/r/1239422
GVS: Gerrit_Virtual_Submit
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Bug 1826768
Change-Id: I8be2b9c074868206cb95b3bc84d66ea84683b19a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1237522
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Cory Perry <cperry@nvidia.com>
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Implement the basic code to swap between PCIe bus speeds for the GPU.
Other GPUs are not supported yet. Currently the following speeds can
be used:
Gen1 (2.5 MTPS)
Gen2 (5.0 MTPS)
gp106 on DPX2 does not support Gen3.
JIRA DNVGPU-89
Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499
Reviewed-on: http://git-master/r/1218177
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1227925
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The lowest page table level may hold very few entries for mappings of
large pages, but a new page is allocated for each list of entries at the
lowest level, wasting memory and performance. Compact these so that the
new "allocation" of ptes is appended at the end of the previous
allocation, if there is space.
Bug 1736604
Change-Id: I4c7c4cad9019de202325750aee6034076e7e61c2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1222810
(cherry picked from commit 97303ecc946c17150496486a2f52bd481311dbf7)
Reviewed-on: http://git-master/r/1234995
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added current temperature reading support for gp10x.
JIRA DNVGPU-48
Change-Id: I45959da28bbd207dcf899a9eb37900c69895cfc1
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1213717
(cherry picked from commit 805245889d1df8aefce277cff9ea31ea5fb4706b)
Reviewed-on: http://git-master/r/1234092
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Suppress error message when nvgpu tries to load VBIOS overlay, but
one is not found. This situation is normal. This is done by moving
gk20a_request_firmware() to be nvgpu generic function
nvgpu_request_firmware(), and adding a NO_WARN flag to
it.
Introduce also a NO_SOC flag to suppress attempt to load firmware
from SoC specific directory in addition to the chip specific
directory. Use it for dGPU firmware files.
Bug 200236777
Change-Id: I4666bee512ae0914ef92b75f068685cb2b503cc8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1223839
(cherry picked from commit e9ae74dfbde3c3d2b103e1927aa92ec7d97cd76d)
Reviewed-on: http://git-master/r/1233412
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Adds P5/P8 sequences and simple debugfs API to
change from P0->P5
JIRA DNVGPU-117
Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1208655
(cherry picked from commit dd410a86263e2407e043743945cf09a77910d745)
Reviewed-on: http://git-master/r/1231035
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Bootloader of PMU is changed & bootloader
takes params using flcn_bl_dmem_desc_v1
descriptor to boot PMU
JIRA DNVGPU-116
Change-Id: I005b615b2323678fa605d190c6b9b629976f0b74
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1212818
(cherry picked from commit 89976a03c13cce6bbba25c99270b0da4ca0f2441)
Reviewed-on: http://git-master/r/1223842
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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- Clocks params update as per r370
JIRA DNVGPU-116
Change-Id: I0aaa1e275aaa2027f2839f3fe24c9aee3e14fd8d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1212827
(cherry picked from commit 54df6ad9668d46dffb5b9d03265948a47611ff13)
Reviewed-on: http://git-master/r/1227288
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Update to sequencer script to support SKU without display.
Bug 200231242
Change-Id: Ibd983166be823370fc687eb2fe9bae3aa8c0dab7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1207096
(cherry picked from commit b573a627b3fe7697c90def46eaf83d755c5d2dee)
Reviewed-on: http://git-master/r/1227247
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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JIRA DNVGPU-72
JIRA DNVGPU-73
Change-Id: I4a979344649ced1bbf8df215c07a15b6149bba69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1215915
(cherry picked from commit d5f49042010a18e2885e1213b463cb067d765390)
Reviewed-on: http://git-master/r/1227267
GVS: Gerrit_Virtual_Submit
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Prune non-existing registers from mclk shadow register list.
Bug 1799537
Change-Id: I8034a1820ef21e550616a5135856b05c2f375d6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208018
(cherry picked from commit cb988bb28dd914ea291cedec799d055f3d71d877)
Reviewed-on: http://git-master/r/1227266
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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FB is enabled in devinit. Skip resetting it in GPU boot.
Bug 1799537
Change-Id: I0748127f0962e7d6d2bf0ecece6773fdf9c35bc8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208715
(cherry picked from commit ceafac52f5711bd987b746686f11b22807f74698)
Reviewed-on: http://git-master/r/1227265
GVS: Gerrit_Virtual_Submit
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* Removed unused registers from headers
* Added counter based MCLK
* Removed hardcoding
JIRA DNVGPU-98
Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1204019
(cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c)
Reviewed-on: http://git-master/r/1227264
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-42
Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1205850
(cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114)
Reviewed-on: http://git-master/r/1227257
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-88
Change-Id: Idecfff5a80fadde77887385491dd6b73b1956bac
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1202551
(cherry picked from commit 3bcf9bad93fb6fdd4b87430b346ea41533149108)
Reviewed-on: http://git-master/r/1223854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add the NVC097_SET_GO_IDLE_TIMEOUT SW method for GP106. This
enables booting the X server.
Bug 1732372
Bug 1792002
Change-Id: I73abaaea240039dc91c66e3862ec01a342db2fa9
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1200637
(cherry picked from commit 0d24a6f3d8e421ea5205279166c6dc2d0f15c6a0)
Reviewed-on: http://git-master/r/1223101
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use entry->mem for determining the target aperture bits of the memory
block represented by entry->mem in update_gmmu_pde0_locked(), instead of
pte->mem that holds the parent memory where this bit is written to.
Previously this has worked because all page tables have been in the same
aperture, but really large userspace allocations may push a part of them
suddendly to sysmem.
Bug 1809939
Change-Id: I3372487c6ae9793018ce44552ded3fb1ba4d145a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1218636
(cherry picked from commit a92596f6e8e621e51b6afae9ab7e62044d6311eb)
Reviewed-on: http://git-master/r/1220525
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For bar2 and pmu instance blocks, use gk20a_aperture_mask()
to select target address (i.e. if address is in sysmem or
vidmem) based on aperture
Also add target accessors for gr_fecs_new_ctx and
gr_fecs_arb_ctx_ptr
Jira DNVGPU-22
Change-Id: Ieaa80bd83a4191fe57b7fba6e0f9cdaeb195a077
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1216138
(cherry picked from commit 7a9f4175abc5dddf0879215de4637b7b6eb0ab7b)
Reviewed-on: http://git-master/r/1219712
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Skip LTCA initialization on dGPU.
Bug 1799537
Change-Id: Ieb4c72e2169dc6bee73306c9b1e6c80866167a1a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208714
(cherry picked from commit 9a8dc5fe96b29b8a67f8203f17126b0093721312)
Reviewed-on: http://git-master/r/1219164
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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tegra_fuse_readl() prototype is changed to match upstreamed
fuse driver, so change implementation accordingly.
Bug 200233653
Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1217376
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Update prod settings for slcg fifo.
Bug 1785549
Change-Id: I0371ef7aeacce5933e06dd36d1368ddc06154ff9
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1218109
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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CBC_BASE register is protected on Pascal dGPUs. Skip initializing it.
Bug 1799537
Change-Id: Ie4b0ac5a37c3c586d1b631ce38823d156b554e1e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208016
(cherry picked from commit 5f9dbca140573798bd05b5b27a7b6abe1871e90f)
Reviewed-on: http://git-master/r/1210289
Reviewed-by: Automatic_Commit_Validation_User
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JIRA DNVGPU-9
Change-Id: I22667acfadfcabf79af841ca5389e41d2ac34860
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1206478
(cherry picked from commit 098b932f7633a903c915b1257beb9304735b4113)
Reviewed-on: http://git-master/r/1210288
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We are using gp10b prod values for gp106, and they are incompatible.
Because of this we are accessing invalid registers.
Delete all prod vals for gp106 until we have generated new ones.
Bug 1799537
Change-Id: Id805e933bd19f6ccaf28274cd69140f9f93cd4ea
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208716
(cherry picked from commit 50d3ecfbfa42795d5eaa20c977cf83613498a804)
Reviewed-on: http://git-master/r/1217287
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add support for cyclestats snapshots in the virtual case
Bug 1700143
JIRA EVLR-278
Change-Id: I353efac6a17704c815a99745ac04d2c3d831351b
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1216644
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Since page tables could either reside either in sysmem
or vidmem, use gk20a_mem_get_base_addr() to get the
base address for buffer
This API will take care of returning proper base address
Jira DNVGPU-20
Change-Id: I3422b51c3ffb8fb86f1dc5095263fc8f19dae44d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1206407
(cherry picked from commit 3c4b22c35b2c4eec33234c2f8dccd9de9422d093)
Reviewed-on: http://git-master/r/1210962
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Jira DNVGPU-20
Change-Id: If917f97ee30f830b05467b15e1ae3f8be296d140
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1206406
(cherry picked from commit bc54e4c24d2f2671b412c79a0ff2944c9575f2a5)
Reviewed-on: http://git-master/r/1210961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use bootstrap allocator's base as base address for WPR
buffers
Jira DNVGPU-84
Change-Id: Ifaeef9f3aa562f9171dd073000c158b513567ede
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1201348
(cherry picked from commit 72f8e727e6f27f867043d024e3d07218359d5faf)
Reviewed-on: http://git-master/r/1210960
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Event notifications on TSGs should only be sent to the channel that caused the
event to happen in the first place, not evey channel in the tsg. Any more and
the debugger will not be able to tell what channel actually got the event.
Worse yet, if all the channels in a tsg are bound to the same debug session
(as is the case with cuda-gdb), then multiple nvgpu events for the same gpu
event will be triggered, causing events to be buffered and the client to get
out of sync.
One gpu exception, one nvgpu event per tsg.
Bug 1793988
Change-Id: Iee36c774f193554ffb9ab7c1650ee0610e476a99
Signed-off-by: Cory Perry <cperry@nvidia.com>
Reviewed-on: http://git-master/r/1194206
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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On dGPU devinit handles initializing thermals.
Bug 1799537
Change-Id: I12ade535d2ddb7fc406256e75f21a422195b36d5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208017
(cherry picked from commit 0e1327107c43dc9c2f5c5d9b79a54f27d2027e85)
Reviewed-on: http://git-master/r/1209122
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Unknown engine is expected, as we do not support all dGPU engines.
Remove the error spew.
JIRA DNVGPU-26
Change-Id: I3d43253b8cab4e51b426536e4899a62156d0da16
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1206465
(cherry picked from commit a3fa13f6be4ff60e90558326474af3d1b315aa43)
Reviewed-on: http://git-master/r/1208408
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Fix support for ppc_in_gpc_base
Add support for ppc_in_gpc_shared_base
Bug 1771830
Change-Id: I3c4576c4d9233ec05f9a52952f42e3226532ff5b
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1201509
(cherry picked from commit 8594628ad4cb90e3298b0d1a3f94aeb50d9c27ab)
Reviewed-on: http://git-master/r/1203183
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA VFND-2103
Change-Id: Ic11cff40e64849cb6abb193bec54d03857433416
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1185205
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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Receive hww_global_esr in gr_gp10b_handle_sm_exception() and
pass it to gr_gk20a_handle_sm_exception()
Bug 200209410
Change-Id: I467355aa57dd3cf03c4ea2134fbc8691f8e76369
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1194986
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move dbg_session_ops to gops for better code consistency
JIRA VFND-1905
Change-Id: I0ac10a69194c8ca485f361cd8cea61d8ab72145a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1192642
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x
family gr class (PASCAL_B and PASCAL_COMPUTE_B).
Bug 200221149
Change-Id: Ia8b781c5baedba660db5997f190a0b363286ed7f
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1193209
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Check for is_fmodel instead of check
for simualtion platforms.
Bug 1735760
Change-Id: I14e349088e9414a73353a94613fa031e63bfa31f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177200
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ayoosh Bansal <ayooshb@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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When gp10b added fuse override callback, tpc disable
fuse override was missed, which was added in gm20b file.
Bug 200220632
Change-Id: I49101a6691f86ccbca390c83f3bd4314eb1a9e36
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1185066
(cherry picked from commit 46f8b7c66d745e80e8c5fc80c19f759ffadf3308)
Reviewed-on: http://git-master/r/1189783
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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Use the tegra-path function to compute the path to the t18x project.
This allows the file to be unmodified if the nvmap project is collaped
into the main project.
Bug 1783210
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Change-Id: I04e8311fda5ba7984f0985c9abec63beb1b38c74
Reviewed-on: http://git-master/r/1177101
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-on: http://git-master/r/1178718
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/1189710
GVS: Gerrit_Virtual_Submit
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Bug 1783210
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Change-Id: I0ff8be222d18eb2fc81de1b22ae26bd4825e6c97
Reviewed-on: http://git-master/r/1175098
Reviewed-on: http://git-master/r/1178717
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/1183066
GVS: Gerrit_Virtual_Submit
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Fix support for ppc_in_gpc_base
Add support for ppc_in_gpc_shared_base
Bug 1771830
Change-Id: Icb0bdedbe78ec4246426789e62302118682ed20a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1158889
(cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433)
Reviewed-on: http://git-master/r/1164398
(cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a)
Reviewed-on: http://git-master/r/1181501
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-on: http://git-master/r/1189608
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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This reverts commit 3639659575e76f81e31c5c9f3aca8896c4ebcb69.
Change-Id: Ieb6a40e30128bb9c59f64f6e39bb026de9a30397
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/1189599
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Tested-by: Vladislav Buzov <vbuzov@nvidia.com>
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Fix support for ppc_in_gpc_base
Add support for ppc_in_gpc_shared_base
Bug 1771830
Change-Id: I1d04bfd20eac08a26986a2436524b97a008ed913
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1158889
(cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433)
Reviewed-on: http://git-master/r/1164398
(cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a)
Reviewed-on: http://git-master/r/1181501
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Added control flag for nvgpu infra to allow kernel to create privileged
CE channels for page migration and clearing support between sysmem
and videmem.
JIRA DNVGPU-53
Change-Id: I1fc35eea60af3d1ea9a0b5582011f20d58958ccb
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1173091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Unset get_phys_addr_bits as PCIe devices do not need
to care if SMMU is enabled or not.
Jira VFND-1965
Change-Id: Ice87ff06087ec6c0a123dcf054717eff80acc8f9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1183085
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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