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* gpu: nvgpu: check return value of mutex_init in nvgpu_allocatorDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in nvgpu_allocator - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I1522b53fb4126fdc2b24fda4b86b45987fe3d203 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317137 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in fecs_trace_gk20a.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in fecs_trace_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I1fe9dd31bbc084bf66dd73dd26b395d898fde9c4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317136 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in dbg_gpu_gk20a.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in dbg_gpu_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I153ef2dd17d0fe17b3f38f6fa7e165d1aeaa2a42 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317135 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in ctxsw_trace_gk20a.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in ctxsw_trace_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I7075c6f742dba7ad4c559fedb80a3a96e824db56 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317134 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in clk_arb.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in clk_arb.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I823888ec234ce5358187c449de8e6cabc5fc5503 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317133 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: fix suspending all SMsCory Perry2017-03-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_suspend_all_sms(), we currently loop over all GPCs and then loop over all TPCs in inner loop But this is incorrect and leads to SM with invalid GPC,TPC ids Fix this by looping over number of TPCs in each GPC in inner loop Also, fix gk20a_gr_wait_for_sm_lock_down() as per below - we right now wait infinitely for SM to lock down - restrict this wait with a timeout on silicon platforms - return ETIMEDOUT instead of EAGAIN - add more debug prints with additional data for SM lock down failures Bug 200258704 Change-Id: Id6fe32e579647fd8ac287a4b2ec80cbf98791e0d Signed-off-by: Cory Perry <cperry@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1316471 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refactor interrupt handlingDavid Nieto2017-03-14
| | | | | | | | | | | | | | | | | | | | | JIRA: EVLR-1004 (*) Refactor the non-stalling interrupt path to execute clear on the top half, so on dGPU case processing of stalling interrupts does not block non-stalling one. (*) Use a worker thread to do semaphore wakeups and allow batching of the non-stalling operations. (*) Fix a bug where some gpus will not properly track the completion of interrupts, preventing safe driver unloads Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1312796 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: debug dump enablement for t19xSeema Khowala2017-03-09
| | | | | | | | | | | | Fifo ops added for dumping channel & ramfc status and pbdma & engine status. Change-Id: Icc739f4f05f0864721954489517fefdfa2fa608a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1302369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add clear single SM error stateThomas Fleury2017-03-09
| | | | | | | | | | | | | | | | | | | | | | Add support for clearing single SM error state for CUDA debugger. In addition to clearing local copy of SM error state, vgpu_gr_clear_sm_error_state now sends a command to RM server (TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE), to clear global ESR and warp ESR. Bug 1791111 Change-Id: I3a1f0644787fd900ec59a0e7974037d46a603487 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1296311 (cherry picked from commit fd07e03c3d086f396e4d65575c576a4dd68c920a) Reviewed-on: http://git-master/r/1299060 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry <cperry@nvidia.com> Tested-by: Cory Perry <cperry@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: suspend/resume contextsThomas Fleury2017-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | Add ability to suspend/resume contexts for a debug session (NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS), in virtualized case: - added hal function to resume contexts. - added vgpu support for suspend contexts, i.e. build a list of channel ids, and send TEGRA_VGPU_CMD_SUSPEND_CONTEXTS - added vgpu support for resume contexts, i.e. build a list of channel ids, and send TEGRA_VGPU_CMD_RESUME_CONTEXTS Bug 1791111 Change-Id: Icc1c00d94a94dab6384ac263fb811c00fa4b07bf Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1294761 (cherry picked from commit d17a38eda312ffa92ce92e5bafc30727a8b76c4e) Reviewed-on: http://git-master/r/1299059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry <cperry@nvidia.com> Tested-by: Cory Perry <cperry@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add NVGPU_GPU_FLAGS_SUPPORT_MAP_COMPBITSRichard Zhao2017-03-08
| | | | | | | | | | | | | | native gpu driver supports map compbits but vgpu does not. Bug 1778448 Bug 200275051 JIRA VFND-3513 Change-Id: I433a6f8631b495875ba899af9609203ab36187ef Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1314065 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: remove cycle stats from characteristicsRichard Zhao2017-03-08
| | | | | | | | | | | | | | | vgpu does not support cycle stats. Bug 1781434 Bug 200275051 JIRA VFND-3513 Change-Id: Id1d566027913632fc8a4f0285609be5f56b26288 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1314064 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: in-kernel kickoff profilingDavid Nieto2017-03-07
| | | | | | | | | | | | | | | | | Add a debugfs interface to profile the kickoff ioctl it provides the probability distribution and separates the information between time spent in: the full ioctl, the kickoff function, the amount of time spent in job tracking and the amount of time doing pushbuffer copies JIRA: EVLR-1003 Change-Id: I9888b114c3fbced61b1cf134c79f7a8afce15f56 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1308997 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: drop 0x in front of timed out symbolKonsta Holtta2017-03-07
| | | | | | | | | | | | | | | The Linux timer code prints an error message containing the caller when a timeout happens. The caller is formatted as a function name instead of a pointer, so don't print 0x in front of it. Bug 1799159 Change-Id: I4f86d885aba78ca20ba025a91c8c940d3c927d58 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1315749 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add fifo ops for *client_type_gpc_vSeema Khowala2017-03-07
| | | | | | | | | | *client_type_gpc_v is different for t19x Change-Id: Ic8f8eff2d98138a877ef95c6f7f40226f0d61a61 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313436 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add pmu trace support for dgpusVijayakumar2017-03-07
| | | | | | | | | | | | | | | | | | | | | | | 1) Trace buffer allocation now calls generic gmmu alloc/map. so for dGPUs they are allocated in vidmem and iGPUs they are allocated in sysmem 2) Use pmu surface mechanism to setup trace buffer params as dGPU binaries follow falcon memory structure to get mem surface params 3) Fix minor coverity issue by removing unnecessary overwrite of count variable in trace print function JIRA DNVGPU-217 Coverity ID 2431386 Change-Id: I2ae49a4e0450481cde2a778447c270a796681dad Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1312404 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change stall intr handling orderSeema Khowala2017-03-07
| | | | | | | | | | | | | | | | | | | | -Handle pbus and priv stall interrupts first. In general critical interrupts should be handled before any other non critical ones. -Dump info enabled with gpu_dbg_intr if priv_ring interrupt is flagged by fmodel. JIRA NVGPU-25 Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1311273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable trace_printk use by defaultTerje Bergstrom2017-03-07
| | | | | | | | | | | | | | | trace_printk() does an extra stringify operation before calling do_trace_printk(). The string ends up unused. This has an impact to kernel even if we never end up using trace_printk(). Disable use of trace_printk() and introduce a Kconfig option for re-enabling it. Change-Id: I2e1014f5231f2089d7dc3cb2539e3eb5f4d58361 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1295298 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: kmem abstraction and trackingAlex Waterman2017-03-03
| | | | | | | | | | | | | | | | Implement kmem abstraction and tracking in nvgpu. The abstraction helps move nvgpu's core code away from being Linux dependent and allows kmem allocation tracking to be done for Linux and any other OS supported by nvgpu. Bug 1799159 Bug 1823380 Change-Id: Ieaae4ca1bbd1d4db4a1546616ab8b9fc53a4079d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1283828 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Give nvgpu_kalloc a less generic nameAlex Waterman2017-03-03
| | | | | | | | | | | | | | | | | | | | | | Change nvgpu_kalloc() to nvgpu_big_[mz]alloc(). This is necessary since the natural free function name for this is nvgpu_kfree() but that conflicts with nvgpu_k[mz]alloc() (implemented in a subsequent patch). This API exists becasue not all allocation sizes can be determined at compile time and in some cases sizes may vary across the system page size. Thus always using kmalloc() could lead to OOM errors due to fragmentation. But always using vmalloc() is wastful of memory for small allocations. This API tries to alleviate those problems. Bug 1799159 Bug 1823380 Change-Id: I49ec5292ce13bcdecf112afbb4a0cfffeeb5ecfc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1283827 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove nvgpu_gpuid_t18x.hAlex Waterman2017-03-02
| | | | | | | | | | | | | | | Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate the relevant definitions and defines into their expected places and make the code use the real defines. No longer is hiding t18x specific stuff necessary. Bug 1799159 Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1300976 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add and move FECS trace flagvishnu Reddy2017-03-02
| | | | | | | | | | | | | | | | Added fecs trace characteristic flag to vgpu to determine for platform support Also moved fecs flag from ctxsw init to fecs init for native linux. This makes flag init uniform across both platforms. JIRA EVLR-993 Change-Id: Id62f31954cb5d7028ef01a199548f5f908b51eb0 Signed-off-by: Vishnu Reddy Mandalapu <vmandalapu@nvidia.com> Reviewed-on: http://git-master/r/1305045 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add worker for watchdog and job cleanupKonsta Holtta2017-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a worker thread to replace the delayed works in channel watchdog and job cleanups. Watchdog runs by polling the channel states periodically, and job cleanup is performed on channels that are appended on a work queue consumed by the worker thread. Handling both of these two in the same thread makes it impossible for them to cause a deadlock, as has previously happened. The watchdog takes references to channels during checking and possibly recovering channels. Jobs in the cleanup queue have an additional reference taken which is released after the channel is processed. The worker is woken up from periodic sleep when channels are added to the queue. Currently, the queue is only used for job cleanups, but it is extendable for other per-channel works too. The worker can also process other periodic actions dependent on channels. Neither the semantics of timeout handling or of job cleanups are yet significantly changed - this patch only serializes them into one background thread. Each job that needs cleanup is tracked and holds a reference to its channel and a power reference, and timeouts can only be processed on channels that are tracked, so the thread will always be idle if the system is going to be suspended, so there is currently no need to explicitly suspend or stop it. Bug 1848834 Bug 1851689 Bug 1814773 Bug 200270332 Jira NVGPU-21 Change-Id: I355101802f50841ea9bd8042a017f91c931d2dc7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1297183 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use litter val for pbdma/eng *status__size*Seema Khowala2017-03-02
| | | | | | | | | | | | | | | fifo_pbdma_status__size_1_v() and fifo_engine_status__size_1_v() are not same for all gpus. Use litter value to calculate chip specific fifo*status__size_1(v) JIRA GV11B-45 Change-Id: I3d3d45bf79d15e14739fcc18cb1ca987669d5c11 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1312688 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Allow compute preemption mode on PASCAL_A classSandeep Shinde2017-03-02
| | | | | | | | | | | | | | | | | | Remove restriction of setting compute preemption mode for channels created with PASCAL_COMPUTE_A class only and allow it to be set for PASCAL_A class too. Also print compute preemption mode during channel closing. Bug 200284575 Change-Id: I2de3b3acda128e91caa2ab0fd341915ce6e6520b Signed-off-by: Sandeep Shinde <sashinde@nvidia.com> Reviewed-on: http://git-master/r/1313286 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Donghan Ryu <dryu@nvidia.com>
* gpu: nvgpu: Do not bind FECS trace on VPR channelsTerje Bergstrom2017-03-02
| | | | | | | | | | | | | | | | VPR channels can access VPR, and writing to FECS buffer outside of VPR causes a region violation. Bug 1877511 Change-Id: Ida466c81e928d1f67bf1b0e7dd6afb799c1ab2f6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1312759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Tested-by: Season Li <seasonl@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: check for pmu enableseshendra Gadagottu2017-03-02
| | | | | | | | | | | | Check for pmu enable, before calling pmu_destrory(). Change-Id: I64c5071ed69b6b50140e46da48a2b165c1f7ba02 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1313391 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add fifo ops for *data_fault_id_enum_vSeema Khowala2017-03-02
| | | | | | | | | | | | | generated hw header for top_device_info_data_fault_id_enum_v is different between legacy chips and t19x JIRA GV11B-7 Change-Id: I877e88a5b1b1f3f41bc72b895536f4a01b4fbd4e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: add gr ops for load tpc maskSeema Khowala2017-03-02
| | | | | | | | | | | | | gr_fe_tpc_fs_r addr is different for t19x Change-Id: I9868fcaf94d063753c4ecf1970b53374cb67b380 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1310326 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: optimize duplicate buffer lookup in case of fixed offsetsDeepak Nibade2017-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_vm_map_duplicate_locked(), we always do a linear search in rb-tree to find a duplicate entry of the buffer In case NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET is set, we first traverse whole rb-tree linearly and then compare offset_align with the address searched from rb-tree If size of rb-tree is very large this linear lookup takes upto 7mS and causes huge delays Hence in case of NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET, we can use offset_align to perform a binary search on rb-tree and then verify that dmabuf and kind match with the node obtained from the search This saves a lot of time per-lookup Bug 1874516 Change-Id: Ia4924b64d66e586c14341ae2e2283beac394bf6f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1309343 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove clock domain aliasesThomas Fleury2017-03-02
| | | | | | | | | | | | | | | | Remove MCLK and GPCCLK domain aliases, now that userspace has swithed to new enumerations. Jira DNVGPU-211 Change-Id: I2af2fd67dbed47088d7161ba0605e13dd7c674a5 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1292609 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: add pbdma and eng bitmask for runlistsSeema Khowala2017-02-27
| | | | | | | | | | | | | | | -Init pbdma and engine bit mask per runlist. -Organize debug info to print supported pbdma instances for particular runlist. JIRA GV11B-3 Change-Id: Ie34dd98ccbe2c779ca1c795855c2a7df4abd2715 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1309706 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ignore set preempt mode to defaultThomas Fleury2017-02-24
| | | | | | | | | | | | | | | | | | | In native case, attempting to set graphics/compute preempt mode to default is ignored if preemption mode has already been set for the context. In virtualized case an error is currently returned. Align behaviour for native and virtualized case, by ignoring such request. Bug 200186530 Change-Id: Ieb3a37107bdbd3284804ee9fd392786409224082 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1306506 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pmu: make gp106_pmu_reset() public.Deepak Goyal2017-02-24
| | | | | | | | | | | | | | secure PMU reset i.e. gp106_pmu_reset() is changed to a non-static function, so that it can be re-used outside gp106 scope. Change-Id: I7d4c4ec6ca1bd315bf8c681723fb350277103c3b Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1303758 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* nvgpu: gpu: pmu: Use pmu ops to call pmu_reset().Deepak Goyal2017-02-24
| | | | | | | | | | | In this patch hard coded function calls for PMU reset are replaced by PMU ops. Change-Id: I266c43e3540163a133895244dcf91169116812f5 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1303757 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ACR interface headers reorganizationMahantesh Kumbar2017-02-23
| | | | | | | | | | | | | | | | | | | | | | -Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to Its specific header files under “drivers/gpu/nvgpu/include/nvgpu/acr/” Folder. - nvgpu_acr.h - Top-level header-file which include ACR interfaces headers & defines required to communicate with ACR, including this header file is good to get access into ACR interface & made changes accordingly, -Deleted acr.h & acr_t18x.h as not required anymore & removed its include from dependent files. Jira NVGPU-19 Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1304748 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove use of DEFINE_MUTEX()Deepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | | | API DEFINE_MUTEX() is defined in Linux and might not be available in other OSs. Hence remove its usage from nvgpu Declare and explicitly initialize below mutexes for both nvgpu and vgpu g->mm.priv_lock g->mm.tlb_lock Jira NVGPU-13 Change-Id: If72885a6da0227a1552303206172f1f2b751471d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1298042 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use common nvgpu mutex/spinlock APIsDeepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using Linux APIs for mutex and spinlocks directly, use new APIs defined in <nvgpu/lock.h> Replace Linux specific mutex/spinlock declaration, init, lock, unlock APIs with new APIs e.g struct mutex is replaced by struct nvgpu_mutex and mutex_lock() is replaced by nvgpu_mutex_acquire() And also include <nvgpu/lock.h> instead of including <linux/mutex.h> and <linux/spinlock.h> Add explicit nvgpu/lock.h includes to below files to fix complilation failures. gk20a/platform_gk20a.h include/nvgpu/allocator.h Jira NVGPU-13 Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293187 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add mutex and spinlock abstraction filesDeepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | Add new abstraction file <nvgpu/lock.h> for all mutex, spinlock and raw_spinlock operations. Add linux specific file <nvgpu/lock_linux.h> which implements linux specific operations for above Jira NVGPU-13 Change-Id: Idab96aa8bf949d6a92ea0edc9f40e90fca401ea4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293186 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: remove use of mutex_is_locked()Deepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | | | mutex_is_locked() API is defined on Linux only and not on other OS like QNX. Hence remove use of this API for OS abstraction support to nvgpu. Instead of using mutex_is_locked(), use mutex_trylock() for same purpose Jira NVGPU-13 Change-Id: I542daf20a2294153da8e8bfe89e0dc0387297523 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1297184 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Disable IRQs only if enabledAlex Waterman2017-02-21
| | | | | | | | | | | | | | | | | In the PCI init/de-init code only disable IRQs if they were enabled. The enable happens in the common power_on code. The PCI routines could both be called without the common power_on code being called which causes an extra disable to happen. Bug 200275531 Change-Id: I43a8a9881f1e9ae254bf36230f29849df074657f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1301701 (cherry picked from commit cca70e9adccee1ef65a0a6d95a4494fc87500c17) Reviewed-on: http://git-master/r/1298954 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: assign ce_ctx->vm during ctx creationKonsta Holtta2017-02-21
| | | | | | | | | | | | | | | | | | Commit 7e403974d3584ab8880e42d422ee3afb7f49d6f3 ("gpu: nvgpu: Simplify ref-counting on VMs") accidentally broke the CE context creation while moving away from direct ch->vm assignments. ce_ctx->vm isn't part of that simplification, so initialize it because it's used elsewhere and were left NULL. Bug 1846718 Change-Id: I6219880227b881d2175005b7eaf6e6e08a6f888e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1306221 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Fix unicast register accesses for SMTerje Bergstrom2017-02-17
| | | | | | | | | | | | | | | | | In two places we used broadcast register as base, but added the unicast offset to it. This causes the write to go well beyond valid register range. Change the broadcast base to use unicast base instead in sequence to resume a single SM and to record error state of SM. Bug 200256272 Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c) Reviewed-on: http://git-master/r/1306331 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Prune gp106 clock gating listTerje Bergstrom2017-02-17
| | | | | | | | | | | | | Further prune registers that do not exist on gp106 that were not caught by previous patch. Bug 200256272 Change-Id: Ic8d6835d8726d850860d680dd1807e8020010a29 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry-picked from commit c1c9029b9b851652d7b62a96373d7c1636f3ad89) Reviewed-on: http://git-master/r/1306330 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Remove almost all gm204/gm206 supportTerje Bergstrom2017-02-17
| | | | | | | | | | | | Remove gm204/gm206 support. It was used only in the interim until Pascal cards were available, and we don't maintain that code anymore. This patch leaves only BIOS code. Change-Id: I215988603d4588ef710bdda6e47449e9235e78ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302224 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Generalize BIOS codeTerje Bergstrom2017-02-17
| | | | | | | | | | | | | | | | | | Most of BIOS parsing code is not specific to any particular GPU. Move most of the code to generic files, and leave only chip specific parts dealing with microcontroller boot into chip specific files. As most of the parsing is generic, they do not need to be called via HALs so remove the HALs and change the calls into direct function calls. All definitions meant to be used outside BIOS code itself are now in <nvgpu/bios.h> Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302222 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: set ch timeout value to 5sRichard Zhao2017-02-17
| | | | | | | | | | | | | | | It couldn't be zero, since it won't enable wdt. JIRA VFND-3450 Change-Id: I9f6ab37bd438923596406a085603c70dcb83d46a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1292715 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove ACR gm204/gm206 supportMahantesh Kumbar2017-02-15
| | | | | | | | | | | | | | | | - Remove ACR gm204/gm206 support as no more support required Maxwell dGPU. -Moved required ACR interface to gp106 from gm206 -Deleted acr_gm206.c/h files & removed its involvement from dependent files. Change-Id: I9cb7ce8f7ef8bb6fcc7515e644ffb11b774389f4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1304556 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove PMU gm204/gm206 supportMahantesh Kumbar2017-02-15
| | | | | | | | | | | | | | -Created new methods for PMU gp106 whichever dependent on gm206. -Deleted pmu_gm206.c/h files & removed its involvement from dependent files. Change-Id: Ic578da53bff362efb3e142962275227787206233 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1304492 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add NVGPU_IOCTL_CHANNEL_SET_BOOSTED_CTXPeter Boonstoppel2017-02-14
| | | | | | | | | | | | | | | | This ioctl can be used on gp10b to set a flag in the context header indicating this context should be run at elevated clock frequency. FECS ctxsw ucode will read this flag as part of the context switch and will request higher GPU clock frequencies from BPMP for the duration of the context execution. Bug 1819874 Change-Id: I84bf580923d95585095716d49cea24e58c9440ed Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1292746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 04:46:29 -0400