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* gpu: nvgpu: vgpu: set correct page size index for gp10bRichard Zhao2016-12-27
| | | | | | | | | | | | | | | VM server only know big page and small page, so convert gmmu_page_size_kernel to according page size index. JIRA VFND-890 Change-Id: Id1f932752b8ca33d14635ac9d71019364aa89dc4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/816359 (cherry picked from commit 5bfc4a2a55889f5457bd34aa06861c042ee67421) Reviewed-on: http://git-master/r/827131 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* Revert "gpu: nvgpu: gp10b: Implement sparse PDEs"Terje Bergstrom2016-12-27
| | | | | | | | | | | | | This reverts commit c2707054192b058eec24a52c7f586b030f9ff007. It introduces regression in T124. Bug 1702063 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Change-Id: I8516c0bfe129bb1ac3d7a1983846061df8ae967b Reviewed-on: http://git-master/r/830787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: set ptimer source frequencySeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | | Set platform data with ptimer source frequency. Removed ptimerscaling10x platform data, and use ptimer source frequency to calculate ptimerscaling factor. Reviewed-on: http://git-master/r/819031 (cherry picked from commit 6849603024943184b0463233bedd95934c353663) Change-Id: I14b0735fcb602cda2e692f6b842a5ecf469ab724 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/827301 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Implement sparse PDEsTerje Bergstrom2016-12-27
| | | | | | Change-Id: I260958d8dea1b445f91b8d15bf76d5321bdc76d1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/758653
* gpu: nvgpu: gp10b: update thermal programmingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | | | Add required fileds and values for thermal slow-down settings in thermal header file and corrected thermal register programming with correct values. Bug 1695567 Reviewed-on: http://git-master/r/822200 (cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981) Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/823013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: support to remove bar2 vmSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Implement function to support bar2 vm clean-up. Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/814573 Change-Id: If5d884e4e1ed87bec6284719d90e9e1963c69bed Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/815428 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable clock gating featuresSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | Enable clock gating power features: slcg, blcg and elcg Bug 200144583 Reviewed-on: http://git-master/r/821149 (cherry picked from commit 1980d443c64e6660e3cd41b8908964c07459dcce) Change-Id: I6ce813552fa57d0fd14dd7ed6a3d9864c88dc58b Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/818636 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add interface to alloc ctxsw buffersAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | | | gp10b introduces support for preemption (GfxP and CILP). Add a new interface to allow allocating buffers needed to support this functionality. Bug 1677153 Change-Id: I8578a7b0a4327f3496d852eeb8be5fc778e2c225 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/806963 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/817039 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Fix support for new color compression kindsSami Kiminki2016-12-27
| | | | | | | | | | | | | | Fix support for kinds C32_MS4_4CBRA and C64_MS4_4CBRA. They're both compressible and ZBC kinds, so mark them as such, too. Change-Id: Ide09ea79a885361ecfc3c188606799c6b2fbdd2e Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/816015 (cherry picked from commit 302b06b76aed5278286487225d6e7280b747d4b3) Reviewed-on: http://git-master/r/816014 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use PROD value for FE_GO_IDLE_TIMEOUTTerje Bergstrom2016-12-27
| | | | | | | | | Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value written in gk20a_init_gr_setup_hw() instead of hard coding here. Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/813959
* gpu: nvgpu: add h/w headers for pbdma_methodsDeepak Nibade2016-12-27
| | | | | | | | | | | Bug 200134238 Change-Id: I263a12b7a3a74d1ab07bca03d5dda685b1e4f22f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/815128 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: create fault buffer only onceSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Create only one instance of replayable fault buffer mapping. Change-Id: Id766298f338ce54cfca7510cbb9e4528ef1945a3 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/814615 (cherry picked from commit 422d2ced384220668347dc8422876d75f6e8807d) Reviewed-on: http://git-master/r/817696 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b non-secure gpmu hw initMahantesh Kumbar2016-12-27
| | | | | | | | | | call gp10b_init_pmu_setup_hw1 during non-secure boot only. Change-Id: Ia90474c7c04edd9be029d013f1da5f73de1b5326 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/815843 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Make CB size and default size sameTerje Bergstrom2016-12-27
| | | | | | | | | | | | | We used to allocate 1.5x buffer size. This leads to memory waste, as we do not set the CB size via SW methods anymore. Bug 1686189 Change-Id: I45cbdeadc154f59b65138f99f50a72d97511cb78 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801865 (cherry picked from commit 791f2fe03d16521206649ab90498443e91e284e2) Reviewed-on: http://git-master/r/815683
* gpu: nvgpu: gp10b: Fix beta CB sizingTerje Bergstrom2016-12-27
| | | | | | | | | | | | Handle beta CB sizing differences for GfxP versus WFI channels. Bug 1686189 Change-Id: Icc421eeb8305f7e4156a74c957662f19504ddad7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801533 (cherry picked from commit 95b9ae4e5f3c29fdb97567d846b9d2139f1a8ec4) Reviewed-on: http://git-master/r/815682
* gpu: nvgpu: gp10b: Report Pascal DMA copy classTerje Bergstrom2016-12-27
| | | | | | | | | | | | Announce supporting Pascal DMA copy class instead of Maxwell. Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/808140 (cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7) Reviewed-on: http://git-master/r/815679 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Fix spill buffer sizeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Spill buffer size is in chunks of 256B. Multiply the size by granularity to get the size in bytes. Bug 1686189 Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801344 (cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0) Reviewed-on: http://git-master/r/815680
* gpu: nvgpu: gp10b: Fix pagepool max sizeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | If pagepool size equals max we should use zero. Add the comparison to do that. Bug 1686189 Change-Id: I15bd43663550b1089a726c0256b89f849c193e21 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801526 (cherry picked from commit 9d89ea5ba345b19d2cff86130ba9d3c4c5f07e6e) Reviewed-on: http://git-master/r/815681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: enable dma for firmware loadingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | Bug 1692799 Change-Id: Idf825c954c646f649d85b8fa7f76b5b45150bfe5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/812442 (cherry picked from commit f72c0738238c3f9a034c6a8b064226f0d7d5dd63) Reviewed-on: http://git-master/r/813978 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu: gp10b: modify gpmu hw initSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | Modify gpmu hwinit to take gp10b specific register offsets in non-secure GPMU boot path. Bug 1685722 Change-Id: Id6696fb20c4fd40ee1b168c952a438771721c792 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/812271 (cherry picked from commit b9408892dd08beca5f4b2e056287a2bc28ccff0e) Reviewed-on: http://git-master/r/813979 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: set wdt timeout for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | set platform specific channel watchdog timeout to 5s for gp10b Bug 200133289 Change-Id: I4478463e22a8167c2fc1235dd9a80e069a27b47c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/811509 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: skip powergate if no BPMPMatt Craighead2016-12-27
| | | | | | | | | | | | | The powergating APIs only work if the BPMP is running. Skip these calls if it's not available, instead of relying on is_linsim, which doesn't work under all environments. Change-Id: I34325847b2ebf33c5db2f31111c57d22ed28ef53 Signed-off-by: Matt Craighead <mcraighead@nvidia.com> Reviewed-on: http://git-master/r/812415 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Force always SMMU bypassTerje Bergstrom2016-12-27
| | | | | | | | | | | | Bug 1688709 Change-Id: If778034225dabbd0f9e6ff843ea6f06011c432bd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/807030 (cherry picked from commit 32f03899ca689f6af12760afe04cf4c8e60ebba1) Reviewed-on: http://git-master/r/808243 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: update slcg xbar prod settingsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Bug 1689806 Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/806115 (cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd) Reviewed-on: http://git-master/r/805482 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu :nvgpu: gp10b: add ptimer scaling factor as 1xVijayakumar2016-12-27
| | | | | | | | | | | | | | | | bug 1603226 t18x fixes ptimer bug and ticks at 1ns. Change-Id: I590c94957c93adf70263f81a0cdfcb8dc913639e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/799989 (cherry picked from commit 44866e195113b0a44ed2513a81dcaaf079c2a5f1) Reviewed-on: http://git-master/r/707810 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix ctag computation overflow with 8GBJussi Rasanen2016-12-27
| | | | | | | | | | | | | Bug 1689976 Change-Id: Ibf1c296fac4f2a2c6fcf062cbd80b3526a4fd4ed Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/806588 (cherry picked from commit 24b57989dc9636b41004bac32ee56dce90318350) Reviewed-on: http://git-master/r/808242 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: implement set_gpc_tpc_mask for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | Bug 200137963 Change-Id: Ibd09b206620e6d6826586bb40e1125fc178dd8e4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/797151 (cherry picked from commit 343c4704564f4b4f22a943a94e66d2c83f63a28f) Reviewed-on: http://git-master/r/808241 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: implement reset_assert/deassert for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Implement platform specific reset_assert() and reset_deassert() calls for gp10b These APIs will in turn will use reset_control APIs to do their work Also, set force_reset_in_do_idle = true for gp10b, since railgating is not supported yet Bug 200137963 Change-Id: I2c0fe1273d3ecfd0c46704a44374712052ff51d6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/797150 (cherry picked from commit 6ac04ca84cee8a4d3b089678c81534799880712d) Reviewed-on: http://git-master/r/808240 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Implement SetCoalesceBufferSizeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Implement method for setting the coalesce buffer size at runtime. Bug 1681992 Change-Id: Ice6c00a27f642c2d68d6cd0e30c12df2e48f5374 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/802366 (cherry picked from commit bd763bc8a16b80ccc8f79b2229eccf2fe2417611) Reviewed-on: http://git-master/r/808239 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | fix below sparse warning drivers/gpu/nvgpu/gm20b/gr_gm20b.c:1055:6: warning: symbol 'gr_gm20b_enable_cde_in_fecs' was not declared. Should it be static? Bug 200088648 Change-Id: I862100d76f2ed5669d15a8f3b8cb9211df7f98ee Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/810394 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: enabling cyclestats for gp10bLeonid Moiseichuk2016-12-27
| | | | | | | | | | | | | Enabling cyclestats and cyclestats snapshot support for gp10b (t186) devices. Bug 1674079 Change-Id: I2e14801de3c61d180630bb9dcd2c607749814893 Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com> Reviewed-on: http://git-master/r/792953 Reviewed-on: http://git-master/r/806190 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Fix steady state beta CB sizeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | We program the default steady state beta CB size. The default is for deep binning, but we've disabled deep binning. As result steady state CB size was left too high. Bug 1683535 Change-Id: I17029078d9c83e55eec6faacfc83c6d812f8c3c0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/795306 Reviewed-on: http://git-master/r/806189
* gpu: nvgpu: gp10b: Fix CB size for GfxPTerje Bergstrom2016-12-27
| | | | | | | | | | Program correct CB size for GfxP channels. We were accidentally using the context image size. Change-Id: I273215256e41e89b7d76f3294a73641804beeb79 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/792713 Reviewed-on: http://git-master/r/806188
* gpu: nvgpu: ELPG init & statistics updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | - Required init param to start elpg - change in statistics dump Bug 1684939 Change-Id: Icc482c08303d0870ec2e1c18a845074968b15e77 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/802455 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/806194 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use clock API to enable clocksMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | Use CCF to enable GPU clocks. Keep an extra reference to prevent runtime PM callbacks from disabling clocks while GPU is powered up. Bug 1673672 Change-Id: I8c34be5ec338fedea62aa3e05bd6bed0513bf1b6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/788814 Reviewed-by: Automatic_Commit_Validation_User Reviewed-on: http://git-master/r/785265
* gpu: nvgpu: gp10b: add debug features for gfxp and cilpKirill Artamonov2016-12-27
| | | | | | | | | | | | | | | | Add debugfs switch to force cilp and gfx preemption Add debugfs switch to dump context switch stats on channel destruction. bug 1525327 bug 1581799 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66 Reviewed-on: http://git-master/r/794976 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/677231
* gpu: nvgpu: gp10b: update headersKirill Artamonov2016-12-27
| | | | | | | | | | | | | | | | Add counters for GFXP, WFI, CTA and CILP context switches bug 1525327 bug 1581799 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: Ifd6ee08af8a83ed827a8996725139416d81ca10e Reviewed-on: http://git-master/r/794977 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/778761 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable gp10b rail calls to bpmpMahantesh Kumbar2016-12-27
| | | | | | | | | | | Bug 200086985 Change-Id: I9eaa135b96629636a6b949ae1e3874dd3abd5138 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/794723 Reviewed-on: http://git-master/r/743217 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add gp10b supportAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | Add support for gp10b in a virtualized environment. Bug 1677153 VFND-693 Change-Id: I919ffa44c6773940a7a3411ee8bbc403a992b7cb Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/792556 Reviewed-on: http://git-master/r/806193 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Always disable security in simTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I1fc8c4c4c71ebf84fe913af07fc2055959e5ab91 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801850 Reviewed-on: http://git-master/r/806192
* gpu: nvgpu: fuse read to boot in SECURE modeMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | -Read fuse to boot in secure/production mode else non sercure mode. Bug N/A Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/791323 Reviewed-on: http://git-master/r/806191 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Correct C097_SET_GO_IDLE_TIMEOUT offsetRobert Morell2016-12-27
| | | | | | | | | | | Bug 1678603 Change-Id: I1c2c3c9395e068fabf554779ded6f0f536622c90 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/792831 Reviewed-on: http://git-master/r/806187 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Disable deep binningTerje Bergstrom2016-12-27
| | | | | | | | | Disable deep binning by default. Change-Id: I75da95984ac314015c6927e099a3eaa37fcc26fc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/790403 Reviewed-on: http://git-master/r/806186
* gpu: nvgpu: gp10b: Implement NVC0_SET_GO_IDLE_TIMEOUTTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1678603 Change-Id: Ib8fb09dace864567b1ce574c216a584831723684 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/790402 Reviewed-on: http://git-master/r/806185
* gpu: nvgpu: Add CDE scatter buffer code for GP10BSami Kiminki2016-12-27
| | | | | | | | | | | | | | Add GP10B-specific code for populating the scatter buffer. Essentially, this enables the use of SMMU bypass mode with 4-kB page compression. Bug 1604102 Change-Id: Ic586e2f93827b9aa1c7b73b53b8f65d518588c26 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/789434 Reviewed-on: http://git-master/r/806184 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Choose netlist ATerje Bergstrom2016-12-27
| | | | | | | | | Force usage of netlist slot A. Change-Id: Ib507b0e0c7ff6d0dbb43f91b6c7264424975d681 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/789060 Reviewed-on: http://git-master/r/806183
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | Fix below sparse warning by declaring gp10b_write_dmatrfbase() as static kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol 'gp10b_write_dmatrfbase' was not declared. Should it be static? Bug 200088648 Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/801213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: HAL to write DMATRFBASEMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | - Must write DMATRFBASE1 to 0 whenever DMATRFBASE is written. Bug 200137618 Change-Id: Id8526d1bafbd116ffc4d8018983791fe9e9fa604 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/798780 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: priv load for gpccs load.Mahantesh Kumbar2016-12-27
| | | | | | | | | | | | - clear mask to load gpcss with priv load. Bug n/a Change-Id: I21522bda83c4dd5c665d47ae334b9fed5cb8ec74 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/798406 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Separate kernel and user GPU VA regions (gp10b)Sami Kiminki2016-12-27
| | | | | | | | | | | | Specify that everything in bar2 VM is kernel reserved. Bug 200077571 Change-Id: I8f6c6ac6352ffd64eedc09187593b6c8d05757ef Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/746802 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:43:42 -0500