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* gpu: nvgpu: gp10b: add tpc disable fuse overrideRichard Zhao2016-12-27
| | | | | | | | | | | | | | | | When gp10b added fuse override callback, tpc disable fuse override was missed, which was added in gm20b file. Bug 200220632 Change-Id: I49101a6691f86ccbca390c83f3bd4314eb1a9e36 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1185066 (cherry picked from commit 46f8b7c66d745e80e8c5fc80c19f759ffadf3308) Reviewed-on: http://git-master/r/1189783 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* nvgpu-t18x: use tegra-path for t18x projectdmitry pervushin2016-12-27
| | | | | | | | | | | | | | | | | | Use the tegra-path function to compute the path to the t18x project. This allows the file to be unmodified if the nvmap project is collaped into the main project. Bug 1783210 Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Change-Id: I04e8311fda5ba7984f0985c9abec63beb1b38c74 Reviewed-on: http://git-master/r/1177101 Reviewed-by: Automatic_Commit_Validation_User Reviewed-on: http://git-master/r/1178718 Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/1189710 GVS: Gerrit_Virtual_Submit
* nvgpu-t18x: rename Makefile to Makefile.{suffix}dmitry pervushin2016-12-27
| | | | | | | | | | | | | Bug 1783210 Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Change-Id: I0ff8be222d18eb2fc81de1b22ae26bd4825e6c97 Reviewed-on: http://git-master/r/1175098 Reviewed-on: http://git-master/r/1178717 Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/1183066 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: ppc register supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | | | | | | | Fix support for ppc_in_gpc_base Add support for ppc_in_gpc_shared_base Bug 1771830 Change-Id: Icb0bdedbe78ec4246426789e62302118682ed20a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1158889 (cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433) Reviewed-on: http://git-master/r/1164398 (cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a) Reviewed-on: http://git-master/r/1181501 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/1189608 Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* Revert "gpu: nvgpu: ppc register support"Hoang Pham2016-12-27
| | | | | | | | | | This reverts commit 3639659575e76f81e31c5c9f3aca8896c4ebcb69. Change-Id: Ieb6a40e30128bb9c59f64f6e39bb026de9a30397 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/1189599 Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com> Tested-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: ppc register supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | | | | | Fix support for ppc_in_gpc_base Add support for ppc_in_gpc_shared_base Bug 1771830 Change-Id: I1d04bfd20eac08a26986a2436524b97a008ed913 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1158889 (cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433) Reviewed-on: http://git-master/r/1164398 (cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a) Reviewed-on: http://git-master/r/1181501 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add control flag to allow kernel to create privileged CE channelsLakshmanan M2016-12-27
| | | | | | | | | | | | | | Added control flag for nvgpu infra to allow kernel to create privileged CE channels for page migration and clearing support between sysmem and videmem. JIRA DNVGPU-53 Change-Id: I1fc35eea60af3d1ea9a0b5582011f20d58958ccb Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1173091 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: unset get_phys_addr_bits for dGPUThomas Fleury2016-12-27
| | | | | | | | | | | | | | | Unset get_phys_addr_bits as PCIe devices do not need to care if SMMU is enabled or not. Jira VFND-1965 Change-Id: Ice87ff06087ec6c0a123dcf054717eff80acc8f9 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1183085 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gp106: reserve wpr from allocatorKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | | In addition to nonwpr_base address, allocate also the wpr_base that is configured as wpr, in order to not overlap user allocations on that area. Jira DNVGPU-18 Change-Id: Ie2976a091e8084fcdc8ffd9fb4b6c75411450acb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1182874 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Fix read_ptimer hook for GP106Sami Kiminki2016-12-27
| | | | | | | | | | | | | | | | Add the read_ptimer hook for GP106. This makes NVGPU_GPU_IOCTL_GET_GPU_TIME not crash on call. Bug 1787348 Change-Id: I31d7c30bcf0d6ad7fdecccd25a7c9c16276632a2 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1179661 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Disable init_preemption_state on dGPUTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | Discrete GPU does not have clocks wired correctly. They're needed to be able to calculate correct preemption timeout, so disable setting the timeout. Change-Id: I14a6d262f6b004d40432a4e026c5558303aa90a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1176904 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: use vidmem by default in gmmu_alloc variantsKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | | For devices that have vidmem available, use the vidmem allocator in gk20a_gmmu_alloc{,attr,_map,_map_attr}. For others, use sysmem. Because all of the buffers haven't been tested to work in vidmem yet, rename calls to gk20a_gmmu_alloc{,attr,_map,_map_attr} to have _sys at the end to declare explicitly that vidmem is used. Enabling vidmem for each now is a matter of removing "_sys" from the function call. Jira DNVGPU-18 Change-Id: I4a67eae403f1d9d271118c35e3775b1129170676 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1176806 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clean up pm_domain codeDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | NvGPU is moving to use runtime PM only for its power management Remove pm_domain calls to register to nvhost Jira DNVGPU-57 Change-Id: Idd01b680af0e8fd601801150fc663afa53b7ce6f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1163217 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: support in-kernel vidmem mappingsKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | Propagate the buffer aperture flag in gk20a_locked_gmmu_map up so that buffers represented as a mem_desc and present in vidmem can be mapped to gpu. JIRA DNVGPU-18 JIRA DNVGPU-76 Change-Id: Icd675e83e3c28836f0ed8880425748697713bb0a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1169296 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: add support for vidmem in page tablesKonsta Holtta2016-12-27
| | | | | | | | | | | | | Modify page table updates to take an aperture flag (up until gk20a_locked_gmmu_map()), don't hard-assume sysmem and propagate it to hardware. Jira DNVGPU-76 Change-Id: I797fdaaf5f42a84fa0446577359147fb6908a720 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1169295 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: initial support for vidmem aperturesKonsta Holtta2016-12-27
| | | | | | | | | | | | | add gk20a_aperture_mask() for memory target selection now that buffers can actually be allocated from vidmem, and use it in all cases that have a mem_desc available. Jira DNVGPU-76 Change-Id: Ifd1908808d928155a0cadeff8ca451a151bfc8c5 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1169294 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add TSG ops for gp106Terje Bergstrom2016-12-27
| | | | | | | | | | | | Bug 200214046 Change-Id: I02a2e5d13f444dbdc1b4eab51ebfda6ab9402734 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1172600 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fixing sparse error/warningMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nvgpu/gp106/pmu_gp106.c:30:5: warning: symbol 'gp106_pmu_enable_hw' was not declared. Should it be static? nvgpu/gp106/pmu_gp106.c:118:5: warning: symbol 'gp106_pmu_reset' was not declared. Should it be static? nvgpu/gp106/pmu_gp106.c:146:5: warning: symbol 'gp106_sec2_reset' was not declared. Should it be static? nvgpu/gp106/acr_gp106.c:79:6: warning: symbol 'gp106_wpr_info' was not declared. Should it be static? nvgpu/gp106/acr_gp106.c:92:5: warning: symbol 'gp106_alloc_blob_space' was not declared. Should it be static? nvgpu/gp106/acr_gp106.c:120:5: warning: symbol 'pmu_ucode_details' was not declared. Should it be static? nvgpu/gp106/acr_gp106.c:187:5: warning: symbol 'fecs_ucode_details' was not declared. Should it be static? nvgpu/gp106/acr_gp106.c:265:5: warning: symbol 'gpccs_ucode_details' was not declared. Should it be static? nvgpu/gp106/acr_gp106.c:348:5: warning: symbol 'gp106_prepare_ucode_blob' was not declared. Should it be static? nvgpu/gp106/acr_gp106.c:1011:5: warning: symbol 'gp106_bootstrap_hs_flcn' was not declared. Should it be static? Bug 200088648 Change-Id: I13716e39f540f8674b1c0f917048bb6b63f7b763 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1173076 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: set graphics preemption stateThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | Set NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT from the default of ~20us to ~100us. Also set NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI o avoid going into GFXP all the time. Bug 1593548 Jira VFND-1894 Change-Id: I6310c3605f7b83178c38de88788d87e36ee428b4 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1162629 (cherry picked from commit 873ddc7288063b1773d31a5bda30d980122d6645) Reviewed-on: http://git-master/r/1166988 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: accessors for nv_pgraph_debug_2Thomas Fleury2016-12-27
| | | | | | | | | | | | | | | | Add accessors for GFXP_WFI_ALWAYS_INJECTS_WFI, field to control FE behaviour for GFXP Jira VFND-1900 Change-Id: Id531f795422393dc603859a0f3059d0681cf9464 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1162628 (cherry picked from commit 4175a21dd2fcbf9c25623bf5d472a3bc30476faa) Reviewed-on: http://git-master/r/1166989 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add QoS notifier for T186Deepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | Add QoS notifier callback gk20a_scale_qos_notify() for T186. This enables QoS for T186. Bug 1772462 Change-Id: Ie25ff4ba24c94354e08fa019704f5d5cc4ef8f33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1161162 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: Add CE engine to engine listTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Initialize CE engine also for gp10b. Change-Id: Ibce2f80b523a09fb1345995c03c5430f3b20844f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1170453 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Tested-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M <lm@nvidia.com>
* gpu: nvgpu: Add interface for privileged channel allocationLakshmanan M2016-12-27
| | | | | | | | | | | | | Added interface for privileged channel allocation to execute the privileged method (ex. CE phys mode transfer). JIRA DNVGPU-53 Change-Id: I1606f8c9d10f29d5a10738b5110ce9f6a2bb428d Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1169320 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: select FW based on ARCHMahantesh Kumbar2016-12-27
| | | | | | | | | | JIRA DNVGPU-34 Change-Id: Iea1964c7d12536591659188c8e969fc7fb632d12 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1166785 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add new CE class for gp10xLakshmanan M2016-12-27
| | | | | | | | | | | | | Added new CE class(PASCAL_DMA_COPY_B) for gp106 and gp104. JIRA DNVGPU-25 Change-Id: I3c85e3ffdedf7594d41bf5c2fbebbf44addd1720 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1166709 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: ngpu: gp106: use vidmem allocator for ucode blobKonsta Holtta2016-12-27
| | | | | | | | | | | | | Use the general video memory allocator for reserving wpr space for acr ucode blob instead of crafting a mem_desc manually. Jira DNVGPU-16 Change-Id: I9d34b3b964eb9ab781fcebecd15ba81643c5452d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1165642 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: set gops.read_ptimerRichard Zhao2016-12-27
| | | | | | | | | | | | | Bug 1395833 Change-Id: I7e7f453d83db76a46f79d62f205832254fcf401e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159589 (cherry picked from commit a1f43172ebf91066969c4d9e25b8a781edb20724) Reviewed-on: http://git-master/r/1158898 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add fifo conf support for gp10xLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | Added fifo configuration support for gp104 and gp106. These GPU chips have more number of channel fifo and runlist than gp10b. Added get_num_fifos and eng_runlist_base_size function pointer to find out the actual value from HW headers. JIRA DNVGPU-25 Change-Id: I2322a6354eaa2af2b2605f3e9eedebf9827c7dda Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1164653 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: WPR updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - setting WPR at 188MB of VIDMEM - setting 256/512MB location at VIDMEM for WPR cause ACR boot failure on GP104/GP106 PROD board but works fine for DEBUG board, - Removed unwanted WPR info dump JIRA DNVGPU-34 Change-Id: I44f9861774fe77dd534d316d91ed9f8dfcb298b4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1164840 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "WAR: gpu: nvgpu: gp10b: disable railgate for K4.4"Deepak Nibade2016-12-27
| | | | | | | | | | | | | | This reverts commit 39a62cba57b243632be56e155813b7318e22c273. Proper fixes are merged for failing tests. Hence re-enable railgating Bug 200198908 Change-Id: Ic9693736add36e7ff77d39fed585126bb6281677 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1163167 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Remove hard coded runlist_id mappingLakshmanan M2016-12-27
| | | | | | | | | | | | | | | From this patch onwards, runlist_id is a member of struct channel_gk20a. So removed hard coded runlist_id mapping logic. JIRA DNVGPU-25 Change-Id: Ib87d96a518a490d4167071708a76100a4d4c02dd Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1161776 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* WAR: gpu: nvgpu: gp10b: disable railgate for K4.4Bharat Nihalani2016-12-27
| | | | | | | | | | | | This is done to mask a race issue seen where power refcount is zero during ISR or bottom half. Bug 200198908 Change-Id: I0a8ed774cd4fda9db65429b5aad03c5e001ff666 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/1162314 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
* gpu: nvgpu: Enable GP10x GPMU secure bootMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | Build support & enable GPMU secure boot for GP10x JIRA DNVGPU-34 Change-Id: Id1316677ed44790aa150e0ada8ff39daf0ef1d0c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161174 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU/SEC2 reset sequence & OPS updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | - Enable OPS to support secure boot - PMU/SEC2 reset sequence change for GP104/GP106 JIRA DNVGPU-34 Change-Id: I583a6af1d5354649c3df9d9b4d74141d52d6ca9d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161132 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ACR boot on SEC2Mahantesh Kumbar2016-12-27
| | | | | | | | | | | | | ACR/SEC2 methods to support ACR boot SEC2 falcon JIRA DNVGPU-34 Change-Id: I917be1d6c61a1c1ae61a918f50228ea00492cd50 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161122 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ACR interface update for GP104/GP106Mahantesh Kumbar2016-12-27
| | | | | | | | | | | JIRA DNVGPU-34 Change-Id: Ieb8e73451a5d73480b8d9e29e78b1a273b17d796 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161120 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: register to nvhost for debug dump"Krishna Reddy2016-12-27
| | | | | | | | | | | | | | | This reverts commit fe3adf3d0a72f936788b98365557783b53ecb6ed. This revert is fixing the Vulkan 1.0.1 CTS failures. Bug 200196104 Change-Id: I8cc90ac9dc3d29a08341f37e83277a0b431e2187 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/1161577 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: include matching header in mm_gp106.cKonsta Holtta2016-12-27
| | | | | | | | | | | | | Include mm_gp106.h in mm_gp106.c to bring function declarations visible and to fix a Sparse warning. Bug 200088648 Change-Id: Id76f565021de585bc02a53a01e52084ff70009c2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1161607 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: detect vidmem configuration from HWKonsta Holtta2016-12-27
| | | | | | | | | | | | | Read video memory size from hardware during initialization for devices that support it. JIRA DNVGPU-14 Change-Id: I84e1bca0eaac8dc204e1fb82628acc6b52c3e5cc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove clockgate_delay paramSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Removed platform data parameter clockgate_delay, since it is not really used for gpu clock gating any more. Change-Id: I4c7148c70699cb5ed24f0b034ddc92bfb4b41887 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1159594 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: clear TEX ECC interruptAdeel Raza2016-12-27
| | | | | | | | | | | | Fix bug in clearing the TEX ECC interrupt. Bug 200206379 Change-Id: I758b55d20919173de527aeb98143851edcde4eeb Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1158806 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: map patch ctx in set_preemption_modeKonsta Holtta2016-12-27
| | | | | | | | | | | | The per-write map/unmap feature from gr_gk20a_ctx_patch_write_begin() is dropped, so call begin/end explicitly from gr_gp10b_set_preemption_mode for the commit_global_cb_manager call. Change-Id: I7bf952fffb54d4f18706e77dea015ffe4b68bcfe Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157835 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix patch write error check in update_ctxsw_preemption_modeKonsta Holtta2016-12-27
| | | | | | | | | | | | Don't attempt to access memory if the patch context can't be mapped, but print an error message instead. Change-Id: I374dc94d13674e0bd9d081b790f7c0dac834e868 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157828 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add Fuse prints on PMU HaltSupriya2016-12-27
| | | | | | | | | | | | | | -Print fuse values in case of PMU halt error -and mailbox reads 0xDEADDEAD Bug 1737044 Change-Id: Icb9677ca278bd316232e07f1d92980f6deb17125 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/1120988 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: use correct APIs for disable and preemptDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | In gr_gp10b_set_preemption_mode() and in gp10b_fifo_resetup_ramfc(), we call channel specific APIs to disable/preempt/enable channel But we do not consider TSGs in this case Hence use correct (below) APIs in above function which will handle channel or TSG internally : gk20a_disable_channel_tsg() gk20a_fifo_preempt() gk20a_enable_channel_tsg() Bug 200205041 Change-Id: I2369e79b2af3b8a91699044106293865d5f8f260 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157192 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: set floor emc freq to bwmgrSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Set emc floor frequency as zero during rail-gate and set max emc frequency as floor frequency during rail-ungate. Bug 1770241 Change-Id: Ib6b6ea6c8b04518423126c3ca3600b4afac15180 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1152848 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: init tsg HAL opsRichard Zhao2016-12-27
| | | | | | | | | | | | | Bug 1702773 Change-Id: I9b6e1d0f2f4fe979f6fab83347884bd69413ccda Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144935 (cherry picked from commit f79eb75272879c869b137cd042312db0a5953412) Reviewed-on: http://git-master/r/1127031 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: manage gr_ctx as independent resourceRichard Zhao2016-12-27
| | | | | | | | | | | | | | | gr_ctx will managed as independent resource in RM server and vgpu can get a gr_ctx handle. Bug 1702773 Change-Id: Ifceb44b7d9a1ba03fc2a4df847f4a78ac4c4a0d4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144934 (cherry picked from commit 0da3101d9b59fe1f9a47ce7b70b30cb8919f35ac) Reviewed-on: http://git-master/r/1150707 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Force GPCCS priv loadTerje Bergstrom2016-12-27
| | | | | | | | | | | | Use priv load for GPCCS instead of DMA. Bug 200204675 Change-Id: Ic7ea7d9e0ef98330e0bdd7606284b8fb3c5bfec8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1155281 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 15:23:50 -0500