| Commit message (Collapse) | Author | Age |
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CTX_STATUS_SWITCH: Engine save hasn't started yet, continue to poll
CTX_STATUS_INVALID: The engine context has switched off. The
preemption step for this engine is complete.
CTX_STATUS_VALID or CTX_STATUS_CTXSW_SAVE: check the ID field:
* If ID matches the TSG for the context being torn down, the engine
reset procedure can be performed, or SW can continue
waiting for preempt to finish if id is not being torn down.
* If ID does NOT match, the context isn't running on the engine.
CTX_STATUS_LOAD: check the NEXT_ID field:
* If NEXT_ID matches the TSG of the context being torn down, the engine
is loading the context and reset can be performed
immediately or after a delay to allow the context a chance to load and
be saved off, or sw can continue waiting for preempt to finish if id
is not being torn down.
* If NEXT_ID does not match the TSG ID or CHID then the context is no
longer on the engine.
SW may alternatively wait for the CTX_STATUS to reach INVALID, but this
may take longer if an unrelated context is currently on the engine or
being switched to.
JIRA GPUT19X-7
Change-Id: I61499f932019de32e0200084c4c41b21a7cbbd2b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1327164
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a_init_bus should not be used for gv11b hal init as
bar1_bind is not supported.
Change-Id: I59b6e991b12d8355b1f54ae3eaf78dc94ca6d767
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1327171
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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All GPUs have a copy engine. So delete the flag has_ce, because
it's always true.
JIRA NVGPU-16
Change-Id: I6daa77ff70ccc0195352109916cb98b43a2109de
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1325357
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gk20a_gr_get_channel_from_ctx() could return NULL as a result
fault_ch could be null
JIRA GPUT19X-7
Change-Id: If89507d3d3fa5a95ba75c4a90eb212d0c8b2214a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1323255
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks.
pbdma_intr_0 field changes for gv11b:-
bit 8(lbreq) does not exists in hw.
bit 28 (syncpoint_illegal)is removed in hw.
bit 20 is reused for clear_faulted_error in hw.
bit 24 (eng_reset) and bit 25 (semaphore) always existed in hw
but never handled in s/w. These are added as channel fatal.
JIRA GPUT19X-47
Change-Id: I13673430408f1cf7ef762075a29b94196f79a349
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325401
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add bus HAL and separate bus related functions from mm_gv11b:
timer access.
Change-Id: I311f258857238233103688fb653d27e4e79005a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323354
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Drop one #include, its contents are not used.
Bug 1853519
Change-Id: I51480b1d75b36c993af3a5005ee9b7fc6dee8a54
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1326127
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The calls to nvhost_{register,unregister}_client_domain don't do
anything, so remove the platform device's late_probe and remove ops that
serve no other purpose than calling those empty functions. Remove also
the corresponding #includes which are now unused.
Bug 1853519
Change-Id: I67149d1575be5b3cacc60e6c28e6f2debfabf71c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1326126
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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mmu fault reporting is moved from fifo* to fb* and gmmu* hw registers.
JIRA GPUT19X-7
Change-Id: If2040ab661229c2e734042f2eec1592030615fee
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1315203
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Don't use gk20a_gmmu_free_attr because the attrs are embedded in struct
mem_desc now.
Bug 1853519
Change-Id: Iaa4309d4c2cd334346e09c4fbf15ce826f2ff640
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1321314
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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preempt completion should be decided based on pbdma and
engine status. preempt_pending field is no longer used
to detect if preempt finished.
add a new function to to be used for preeempting ch and tsg
during recovery. If preempt timeouts while in recovery, do not
issue recovery.
JIRA GPUT19X-7
Change-Id: I0d69d12ee6a118f6628b33be5ba387c72983b32a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1309850
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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mmu fault is now part of hub interrupt
Change-Id: I9ce523d5f11955ac9552510d154eaa2f17a6cbf6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313484
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Currently priv, pbus and ltc interrupts are enabled as non-stall but
being handled in stall isr. Fix is to configure them as stall interrupt.
Change-Id: I86adc04f480d5f4befe7e9255b582ce13fa4efc1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1319018
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added TPC floor sweeping code for gv11b.
JIRA GV11B-73
Change-Id: Ib0d05e2d606fe13dff119948fbc9022e8af0fa7f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1315257
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
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Added dump for pbdma, engine status, channel status
and ramfc
JIRA GV11B-45
Change-Id: I25442932c61310005fea481455f68ba10c361381
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1302425
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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There is no peermem access for gv11b nvlink.
So no need to enable peermem access through l2.
Implemented gv11b specific ltc_cbc_fix_config
function to read correct num_active_ltcs.
JIRA GV11B-71
Change-Id: I348ce3bbf42e864341494e386b6f33478badb3a8
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1315148
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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For gv11b fifo recovery, triggering fake mmu fault is not required.
JIRA GV11B-7
Change-Id: I6c8c9672085dbbbd77e0d991d840c4cc75c2ab43
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313496
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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*client_type_gpc_v moved from fifo to gmmu
JIRA GV11B-7
Change-Id: Icd28a2ac8c0d0ae212cfca9410dfe781972367df
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313435
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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generated hw header for top_device_info_data_fault_id_enum_v
is different between legacy chips and t19x
JIRA GV11B-7
Change-Id: Ia765be740c419c5b2a61b03104b264c51f1e797e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313383
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implemented gv11b specific l2 state init and Configured
ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info:
- cbc_num_active_ltcs is read only for gv11b, so did not
write any data to that field.
- enforced serilized access to l2 from sysmem and peermem.
- nvlink connected peer trafic sent through l2
JIRA GV11B-71
Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1312831
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gr_fe_tpc_fs_r addr is different for t19x
Change-Id: Ibae4b7224ffbd4d8366890cd05649b1b66e22f02
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1310327
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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generate headers for pri ring, pbdma intr and gmmu
with updated reg generator
JIRA GV11B-47
JIRA GV11B-7
Change-Id: Id198fb338c03acc52c523754cfd07db01ff9bffd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1312756
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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To get maximum number of subctx, sw should read
NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of
LITTER_NUM_SUBCTX.
JIRA GV11B-72
Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1309591
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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PMU reset for GV11B is PRIV protected.
gp106_pmu_reset() also uses the same register
to reset PMU, therefore used same function for
gv11b.
Change-Id: I633a96256598e73ed02cbdfe0afdb9fba8b76afd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303740
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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t19x version.
Bug 1799159
Change-Id: I5e4c2a5341909d2e366ebc15adb4cdce70d695c7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1303264
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gv11b sync point support is moved to a shim outside of GPU,
and gv11b does not support sync points anymore. Remove use of
the sync point protection.
JIRA GV11B-47
JIRA GV11B-2
Change-Id: I70f3d2ce0cfe016453efe03f2bbf64c59baeb154
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1300964
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Init below fields in t19x_gpu_tegra_platform
-reset_assert = gp10b_tegra_reset_assert
-reset_deassert = gp10b_tegra_reset_deassert
JIRA GV11B-34
Change-Id: I69cff5621d7fa7de830567f4cce87f79934809e2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1296909
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gp10b_tegra_get_clocks called from gv11b_tegra_probe.
Also gv11b_tegra_probe is called from nvgpu_probe via function
ptr platform->probe
JIRA GV11B-34
Change-Id: I782286e191eef84ce41bc65440fbe5ae00995af3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1296840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The driver file includes <linux/tegra-powergate.h> but does
not use anything from this header.
Remove this unnecessarily inclusion of header file.
bug 200257351
Change-Id: Ibbc3c382c31a8c566ed4018fd36d1ffed08bf29e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1300556
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Added thermal registers for gv11b. Implemented chip specific
init_elcg_mode. In thermal control register, engine power auto
control config is removed and added new field for engine holdoff
enable signal.
JIRA GV11B-58
Change-Id: I412d9a232800d25efbdb0a40f14949d3f085fb0e
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1300119
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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pmu_get_queue_head/tail &
pmu_get_queue_head/tail_size ops are defined
for gv11b chip.
JIRA GV11B-30
Change-Id: Iae139732d9f68f93e3c197469c04ccd3f0d63ce7
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1285749
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add regops whitelists for gv11b.
JIRA GV11B-35
Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1295401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Update zcull and perfmon buffer pointers in context header.
For gv11b maximum 49 bits gpu va possible. But,
zcull and perfmon buffer pointers uses maximum 41 bit
va address (258 bytes aligned). To accommodate this, high pointer
registers needs to be updated in context header.
JIRA GV11B-48
Change-Id: Ibe62b6bfedd32c4f3721e4d19d96cce58ef0f366
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1291852
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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Update clock gating setting till HW CL#37750038
JIRA GV11B-15
Change-Id: I98c4a157df979c944122f4a7b05e3e692a28fe2f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1294824
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Similar HW header update as has been done for all the other chips.
HW header files are located under:
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/
And can be included like so:
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
Bug 1799159
Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284433
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Restore golden context correctly with subcontext header.
Increase subctx header size to hold complete golden context.
Also fill function pointer for freeing context header.
Bug 1834201
Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1282440
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The fuse headers are unified and moved all the content of
linux/tegra-fuse.h to the soc/tegra/fuse.h to have the
single fuse header for Tegra.
Use unified fuse header soc/tegra/fuse.h.
bug 200260692
Change-Id: Ied87164ea1de793d97a4cc6a754150164af04698
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1287500
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added proper sw methods handling of shader execptions
for gv11b.
Bug 1834201
Change-Id: I3f3a45beed777cc4af59368dccd9dc7bb8181c37
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1283729
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The interface for wait_idle() was changed for gk20a, etc, so this
change is necessary to update the wait_idle function for gv11b.
Similarly for wait_fe() - this needs to no longer use an end_jiffie
argument.
Bug 1799159
Change-Id: I192159feffda5476269194e7d6ef15b5fe3055bd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1280459
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Pre-GP10X
All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil
part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds).
Clears for these kinds typically happen in two phases, depth phase and
stencil phase. The depth clears can be compressed or ZBC-ed, whereas the
stencil part is always uncompressed.
Stencil ZBC in GP10X
For GP10X both the depth and the stencil data for these packed kinds can be
ZBC cleared. A given tile will be a cross product of the following states
for depth and stencil.
Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0,
ZBC index 1
Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2
JIRA GV11B-9
Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235520
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Add support for multiple runlists in gv11b.
Bug 1834201
Change-Id: I5a4cb92643626675314b4b61df330cde06e22c9f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1285044
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA GV11B-7
Change-Id: I32428e6b91050ad3f697eb80e2aabda2cc1bfda4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1249339
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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pmu_bootstrap() does not support gv11b PMU non-secure boot.
gv11b_pmu_bootstrap function is added with the updated/new args.
JIRA GV11B-30
Change-Id: I42c1a7bd77d75c6e59ee4cc695cc879ce7cec095
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1259271
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Change-Id: I7ca3d9968dc37b6514a08d3f49b6d2353e11671d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1277786
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA GV11B-15
Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1266705
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gv11b needs atleast one subcontext to submit work. To support
legacy in gv11b, currently main context is always copied into
subcontext0 (veid0) during channel commit instance.
As part of channel commit instance, veid0 for that channel is
created and relevant pdb and context info copied to vedi0.
JIRA GV11B-21
Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1231169
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: Ie25197e9bc08088ff837677d72fa8c28828f0bf4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1263414
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix following sparse warning by making function as static:
$TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/gr_gv11b.c:1529:5:
warning: symbol 'gr_gv11b_setup_rop_mapping' was not declared.
Should it be static?
Bug 200088648
Change-Id: Idd388170f35e7e6cd7559d8aab8968f7e8e545c6
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1261891
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Reuse gk20a_mm_setup_hw for gv11b.
JIRA GV11B-21
Change-Id: I5141dbb8088799a8bd5df55469bc371b63497e96
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254939
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Set copy engine context valid for channel loaded on
pbdma.
JIRA GV11B-21
Change-Id: I74445dcefe38b52723705c185e6a37c9f56ac2bf
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254916
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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