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* gpu: nvgpu: add support for PCI device 0x1ebaDeepak Nibade2018-06-15
| | | | | | | | | | | | | | | | | Add support for PCI device with ID 0x1eba Add corresponding platform data Change-Id: I2e5fe25666d4c00a6d4d27f0124fa02639f7aebd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746579 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: Unified CSS VGPU HALAntony Clince Alex2018-06-15
| | | | | | | | | | | | | | | | | - defined platform agnostic wrapper for mempool mapping and unmapping. - used platform agnositc wrapper for device tree parsing. - modified css_gr_gk20a to include special handling incase of rm-server JIRA: VQRM:3699 Change-Id: I08fd26052edfa1edf45a67be57f7d27c38ad106a Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1733576 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: removed linux includes from CSS HALAntony Clince Alex2018-06-15
| | | | | | | | | | | | | | | | | | | - removed inclusion of linux includes. - replaced with nvgpu/*.h's - reformated the function signature of "css_hw_get_pending_snapshot" and "css_hw_get_overflow_status" be global instead of static. - added get_pending_snapshot and get_overflow_status to ops->css. JIRA: VQRM-3699 Change-Id: I177904c263e143b414924c2c28ad6fd3cfd00132 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1732783 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract dt functionsRichard Zhao2018-06-15
| | | | | | | | | | | | Added nvgpu_dt_read_u32_index() for now. Jira VFND-4870 Change-Id: I3e51c408dfba3864372c515ba5d2c77708a489c8 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683008 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove deprecated ZBC registersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | All DS ZBC registers are non functional beginning Pascal and only the DSS ZBC registers are functional Hence remove access to deprecated ZBC registers Jira NVGPUT-25 Jira NVGPUT-107 Change-Id: I85ba13d2a9ec47b3fe98df7285f7a310ee69dadb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747933 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove extra deps to bus_gk20a.hTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | gk20a.c and mm_gk20a.c include bus_gk20a.h without needing anything from it. Drop that dependency. JIRA NVGPU-737 Change-Id: Ia1ae39248dad854797fb4be75c9ffeef3b191c7b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747766 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix userspace buildAdeel Raza2018-06-14
| | | | | | | | | | | | | | | | | | | | | The following changes moved/renamed/deleted files: - https://git-master.nvidia.com/r/#/c/1730893/ - https://git-master.nvidia.com/r/#/c/1730890/ These changes did not update Makefile.sources which is used by the userspace build. That's why the userspace build broke. This change updates Makefile.sources and fixes the userspace build. Change-Id: I011101c2f956cd1304d44d54d3e4a1a4cdfb6da9 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add HALs for mmu_fault setup and infoDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | Add below HALs to setup mmu_fault configuration registers and to read information registers and set them on Volta gops.fb.write_mmu_fault_buffer_lo_hi() gops.fb.write_mmu_fault_buffer_get() gops.fb.write_mmu_fault_buffer_size() gops.fb.write_mmu_fault_status() gops.fb.read_mmu_fault_buffer_get() gops.fb.read_mmu_fault_buffer_put() gops.fb.read_mmu_fault_buffer_size() gops.fb.read_mmu_fault_addr_lo_hi() gops.fb.read_mmu_fault_inst_lo_hi() gops.fb.read_mmu_fault_info() gops.fb.read_mmu_fault_status() Jira NVGPUT-13 Change-Id: Ia99568ff905ada3c035efb4565613576012f5bef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744063 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set hub interrupt enable/disable HALs for vGPUDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | Below HALs were missing in vGPU/gv11b. Add them. gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Jira NVGPUT-44 Change-Id: I981744b79e9fc0d72e6ab991b09bbbcb3f6bcd44 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744086 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cosmetic changes to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | | | A few review comments got lost in the review of moving bus code to common/bus. This takes care of renaming the header file protection define, deletes the unnecessary description of the file in header, and updates copyright years. Change-Id: Ib7dfe3d8fdf31ff3ea1fbf96fc41f9e454486dd1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741824 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10x PMU f/w version updateVaikundanathan S2018-06-14
| | | | | | | | | | | | | | -gp10x f/w version update for ucode https://git-master.nvidia.com/r/#/c/1748070/ Change-Id: Ie6f40fc931a24162497ef62778069814fd668c20 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1748071 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: effective freq load changesVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | | Read clk frequency through PMU RPC Bug 200399373 Change-Id: I9e887dcb1c5b622110eb4c1584f2f34434efd674 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701276 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Mask an unused HCE_ILLEGAL_OP InterruptVinod G2018-06-14
| | | | | | | | | | | | | | HCE interrupt is not being used in nvgpu platform now, masking the bit from the interrupt register. bug 2082123 Change-Id: I1d53584afebe57b9621c8f4ec395cd1dcd6c7611 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746850 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: warn if cde fails to find addr to patchKonsta Holtta2018-06-14
| | | | | | | | | | | | | | | | Print the surface address for which we fail to resolve an iova address when patcing cde parameters. This appears to happen extremely rarely for yet unknown reasons. Bug 2038362 Change-Id: I5ca300ea9b2f8c8867b7b43e37f51a50836129b7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1748455 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add support for FECS VAVaibhav Kachore2018-06-14
| | | | | | | | | | | | | | | | | Enable FECS trace support for t194 Linux + HV EVLR-2309 Change-Id: If22c931a54833eb995710b6e0dcad335e4ffbae6 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674970 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for FECS VAVaibhav Kachore2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - On t186, ucode expects physical address to be programmed for FECS trace buffer. - On t194, ucode expects GPU VA to be programmed for FECS trace buffer. This patch adds extra support to handle this change for linux native. - Increase the size of FECS trace buffer (as few entries were getting dropped due to overflow of FECS trace buffer.) - This moves FECS trace buffer handling in global context buffer. - This adds extra check for updation of mailbox1 register. (Bug 200417403) EVLR-2077 Change-Id: I7c3324ce9341976a1375e0afe6c53c424a053723 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: increase bios size to 0x90000Deepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | bios size is currently set to 0x40000, but this could insufficient on some platforms Increase it to 0x90000 so that we have buffer of sufficient size to store bios content Change-Id: I510d10763b1fc6ba427680e44a55e3604f67e049 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746578 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate vsm mapping based on nonpes_aware_tpcseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. For user space to be in sync with hw populate vsm mapping based on nonpes_aware_tpcs. Bug 200405202 Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744304 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct calculation of sm_id for .record_sm_error_stateRichard Zhao2018-06-14
| | | | | | | | | | | | | | | | | | Starting with Volta, one TPC could have more than 1 SMs. So .record_sm_error_state needs to have sm number as parameter. Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r. Let the function return logical sm_id. RM server will need it to nofify client. Jira EVLR-2643 Bug 200405202 Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742165 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle replayable mmu fault during waiting for SM lockdownRichard Zhao2018-06-14
| | | | | | | | | | | | | | outstanding replayable mmu fault will prevent SM from lockdown, so handle the replayable mmu fault while polling lockdown status. Jira EVLR-2643 Bug 200405202 Change-Id: I811f16ef4394a6cc42a5f37a17e426dd749c5652 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741997 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove duplicate NVGPU_SUPPORT_IO_COHERENCE enableAnup Kumar Sah2018-06-14
| | | | | | | | | | | | | | | | | | NVGPU_SUPPORT_IO_COHERENCE is already set in gk20a_probe based on the presence of dma-coherent property of gpu DT so this change removes the redundant enable in gv11b_init_gpu_characteristics VQRM-4044 Change-Id: I8c8d8d485f00aec6fae7a6794fecd855ce3a0004 Signed-off-by: Anup Kumar Sah <asah@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741090 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GPU NEXT PMU version updateMahantesh Kumbar2018-06-14
| | | | | | | | | | | | | | | | | | - PMU version update for NEXT GPU - Added condition to assign correct ops for NEXT GPU. P4 CL#: 24313845 Change-Id: Ia6ee5978d450c228b4f298382746e06da56056a5 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1745022 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export APIs to allocate/destroy context buffersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | Export below APIs in gr_gk20a.h header gk20a_gr_alloc_ctx_buffer() gk20a_gr_destroy_ctx_buffer() Jira NVGPUT-27 Change-Id: Ia181a3f464ffbc9abe12963dd709cebee9e7dbc9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1743364 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support additional global context bufferDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | Increase NR_GLOBAL_CTX_BUF from 8 to 9 and increase NR_GLOBAL_CTX_BUF_VA from 5 to 6 to accomodate a new global context buffer Jira NVGPUT-27 Change-Id: I21fe4357f19db7f5647741d9ce932460868a856d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1743363 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to allocate/map/commit global context buffersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | Add below new HALs to allocate/map/commit global context buffers gops.gr.alloc_global_ctx_buffers() gops.gr.map_global_ctx_buffers() gops.gr.commit_global_ctx_buffers() Set these HALs for all the supported GPUs We right now re-use below APIs to set these HALs gr_gk20a_alloc_global_ctx_buffers() gr_gk20a_map_global_ctx_buffers() gr_gk20a_commit_global_ctx_buffers() Jira NVGPUT-27 Change-Id: I975a54e8d1716af057f982d543787748d35a256e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1743362 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Include NEXT gpu fecs/gpccs sign supportMahantesh Kumbar2018-06-14
| | | | | | | | | | | | | | | | Added support to get fecs/gpcss sign file based on GPU ID for sign verification by ACR for the NEXT gpu. Change-Id: I8e12d74ae70c6635049dd1a2248685f1382ad2a2 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742976 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove nvlink on driver removalNitin Kumbhar2018-06-14
| | | | | | | | | | | | | | Unregister nvlink and nvlink device when gpu is getting removed. Without this next modprobe of nvgpu results in nvlink registration failure. Bug 1987855 Change-Id: I785e707d1fa90f45a3ff0e9790f3f02fa15510d4 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735986 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove ldiv_slowdown_factor sysfs nodeNitin Kumbhar2018-06-14
| | | | | | | | | | | | | | | ldiv_slowdown_factor sysfs node is added with change f9e55fba but it didn't update nvgpu_remove_sysfs() to remove it. This results in EEXIST error for modprobe-rmmod-modprobe sequence of nvgpu driver. Bug 1987855 Change-Id: I4360028ba75435f3e144be23f6d9f42a81dcb94b Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730538 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for SW WARTejal Kudav2018-06-14
| | | | | | | | | | | | | | Workaround of setting SAFE_CTR_INIT on NVLINK (WAR for Bug 1888034) is needed only on nvlink 2.0. Add HAL to avoid running the WAR on future chips. Bug 2006692 Change-Id: I85fb90ea5ce7b848946f2c362e7a952787cc1261 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738401 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL to get link_maskTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | VBIOS link_disable_mask should be sufficient to find the connected links. As VBIOS is not updated with correct mask, we parse the DT node where we hardcode the link_id. DT method is not scalable as same DT node is used for different dGPUs connected over PCIE. Remove the DT parsing of link id and use HAL to get link_mask based on the GPU. JIRA NVLINK-162 Change-Id: Idb7b639962928ce48711a0d7fc277c4c324bee91 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738967 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for minion INIT* dlcmdTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | The sequence of INIT* minion dlcmd varies between nvlink 2.0 and 2.2. The order is strict for 2.2. Also there are new dlcmds added to the nvlink bringup sequence. Add HAL to allow sequence update for nvlink 2.2. Old sequence: INITLANEENABLE-> INITDLPL New Sequence: INITDLPL->INITDLPL_TO_CHIPA->INITTL->INITLANEENABLE JIRA NVLINK-176 Change-Id: I49e0a726f56e7d6122ac4cddf0f0e021d16f1926 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738329 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Multiple WPR supportMahantesh Kumbar2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | The WPR will be divided into several sub-WPRs, one for each Falcon and one common for sharing between Falcons which bootstrap falcons - Defined & used flag NVGPU_SUPPORT_MULTIPLE_WPR to know M-WPR support. - Added struct lsfm_sub_wpr to hold subWPR header info - Added struct lsf_shared_sub_wpr_header to hold subWPR info & copied to WPR blob after LSF_WPR_HEADER - Set NVGPU_SUPPORT_MULTIPLE_WPR to false for gp106, gv100 & gv11b. - Added methods to support to multiple WPR support & called by checking flag NVGPU_SUPPORT_MULTIPLE_WPR in ucode blob preparation flow. JIRA NVGPUTU10X / NVGPUT-99 Change-Id: I81d0490158390e79b6841374158805f7a84ee6cb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Handle all SM errorsVinod G2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | Add the missing register bits to identify the SM errors. Except for mmu_nack error, all other errors are handled using a single function. That function sets the error notifier with GR_EXCEPTION, clears interrupt and triggers recovery process. bug 200402677 JIRA NVGPU-573 Change-Id: Icfaff1f20f1f35adb4cd35ce288ce694845aed3c Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730963 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fbpa ecc supportRichard Zhao2018-06-14
| | | | | | | | | | | | | | - add fbpa ecc counters - add HALs for init_fbpa and fbpa_isr Jira NVGPUT-69 Jira NVGPUT-68 Change-Id: I3c8fbb664a9b08ece23d860d84881d4860706f77 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726307 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Read sublink state when neededTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | | On nvlink 2.2, we poll for sublink substate to be stable before checking sublink primary state. Currently, we read both TX and RX sublink state during set_sublink_mode() irrespective of which sublink mode is changed. This is not correct when we are polling on substate value while getting sublink state. JIRA NVLINK-164 Change-Id: I474705f059dbf41e5fb7e45bef455c33ee21aa95 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1734539 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move SW scratch register read to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | SW scratch register is in bus register range. Move query of that register to bus HAL from bios. JIRA NVGPU-588 Change-Id: I69f35af3d5f8da3550eb68fe7d060a3ec48ce275 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730898 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Combine variants of init_mm_setup_hwTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | gp10b and gk20a variants of init_mm_setup_hw were essentially the same. Delete the gp10b version and use gk20a variant instead. gv11b variant now also inherits gk20a variant. JIRA NVGPU-588 Change-Id: I842516a1c0be68562ad0ece6e1837a1416d24957 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730897 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement bus HAL for bar2 bindTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL. BAR2 bind HW API is in bus. JIRA NVGPU-588 Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730896 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use gm20b version of BAR1 bindTerje Bergstrom2018-06-14
| | | | | | | | | | | | | All chips should use the waiting version of BAR1 bind since gm20b. Change gp10b and gp106 to do that. BAR1 is not used in Volta. JIRa NVGPU-588 Change-Id: Ib6957ebea4effa7c64f4d71522447fa6245728ed Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730895 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not set MMU page size againTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | | MMU page size is set already in MMU initialization. Do not re-set it when binding BAR2. JIRA NVGPU-588 Change-Id: I3b5309baa2adf0917c59a390fe41c29b13398e6c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730894 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Separate timer from busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Code touching timer registers was combined with bus code. They're two logically separate register spaces, so separate the code accordingly. JIRA NVGPU-588 Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730893 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove setting of PRI timeoutTerje Bergstrom2018-06-14
| | | | | | | | | | | | | PRI timeout should always use the HW initialization value. Do not set it explicitly. JIRA NVGPU-588 Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730892 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove direct MC and GR deps from busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | | | bus_gk20a.c had some debug dump references to MC and GR registers. The dumps have not been very useful, so instead of refactoring the code just remove the dumps. JIRA NVGPU-588 Change-Id: Id974731716d058ef4a3fe77240c11b1c53db169c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting of BAR0_WINDOW to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to common code so that pramin_gk20a.[ch] can be deleted. JIRA NVGPU-588 Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730890 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting priv interrupt to priv_ringTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Registers to set priv interrupts are in priv_ring, but the code was in bus HAL. Move the code and related HALs to priv_ring instead. JIRA NVGPU-588 Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730889 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: bus: Remove use of extra includesTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | bus_gk20a.c had a few unnecessary includes. Remove them to speed up compilation. JIRA NVGPU-588 Change-Id: I0e94e788104ba6acb259c315734e6b42f69a8074 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730888 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: clean up nonstall isrsRichard Zhao2018-06-14
| | | | | | | | | | | | | | | | | | It has moved to use TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP, removing legacy isrs. Jira EVLR-2696 Change-Id: Ie977bba59c0af8589989d872150c3f9b2080854a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1736399 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gr: remove only created sysfs nodesNitin Kumbhar2018-06-14
| | | | | | | | | | | | | | | | Sysfs nodes for GR stats are created on GR init. If nvgpu module is removed without any ops, then it tries to remove sysfs nodes which do not exist resulting in kernel panic. Fix this issue by removing sysfs nodes only if ecc counters are initialized. Bug 1987855 Change-Id: I3f967ee92ec02ad19ffbd9bfa8bace5bfd229dd2 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: skip destroy if vidmem not initializedNitin Kumbhar2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | The vidmem shall be destroyed only if it has been initialized. If not skipped, it accesses mutexes which are in invalid state. This results in BUG like: BUG: spinlock bad magic on CPU#0, rmmod/1560 Also, destroy vidmem bootstrap allocator which is set up in nvgpu_vidmem_init(). Bug 1987855 Change-Id: I68e91422a54b40feeb9071158b797828e2391303 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730535 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add Ctrl API to read SM error stateVinod G2018-06-14
| | | | | | | | | | | | | | Expose IOCTL to Ctrl node to read Single SM error under NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE bug 200412642 JIRA NVGPU-700 Change-Id: I3cbcf4d7f23a53dbd2350b38a5e259559d5fd3af Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-29 22:37:27 -0400