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* gpu: nvgpu: Use nvgpu_alloc_vid_at for dGPU ACRTerje Bergstrom2018-06-22
| | | | | | | | | | | | | | | | | | ACR allocates buffers from vidmem and passes explicitly flag NVGPU_DMA_NO_KERNEL_MAPPING. Vidmem buffers are never mapped to CPU, and dGPU ACR does not actually care, so switch to using nvgpu_alloc_vid_at(). This removes another explicit dependency to NVGPU_DMA_NO_KERNEL_MAPPING, which is going to be removed. Change-Id: I532d40c5ba9e71f07461c526bd2a43e1eb01a290 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753711 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add nvgpu_dma_alloc_vid_at()Terje Bergstrom2018-06-22
| | | | | | | | | | | | | | Add a wrapper function nvgpu_dma_alloc_vid_at() for performing vidmem allocation at a specific address without needing to pass any flags. Change-Id: Ib7a21a4fd33120749cf7b79750c3a382ba08b470 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753710 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update Linux side VM code for API solidificationAlex Waterman2018-06-22
| | | | | | | | | | | | | | | | | | | | | | Update the Linux specific code to match the MM API docs in the previous patch. The user passed page size is plumbed through the Linux VM mapping calls but is ultimately ignored once the core VM code is called. This will be handled in the next patch. This also adds some code to make the CDE page size picking happen semi-intelligently. In many cases the CDE buffers can be mapped with large pages. Bug 2011640 Change-Id: I20e78e7d5a841e410864b474179e71da1c2482f4 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1740610 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update __get_pte_size() to check IOMMU-abilityAlex Waterman2018-06-22
| | | | | | | | | | | | | | | | | | | | When generating the PTE size for a given mapping the code must consider whether the GPU is being IOMMU'ed. The presence and usage of an IOMMU implies the buffers will appear contiguous to the GPU. Without an IOMMU we cannot assume that and therefor must use small pages regardless of the size of the buffer to be mapped. Bug 2011640 Change-Id: I6c64cbcd8844a7ed855116754b795d949a3003af Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1697891 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: resolve missing -ENOSYS errorDebarshi Dutta2018-06-22
| | | | | | | | | | | | | | | | Added the header #include <nvgpu/errno.h> in os_fence.h Bug 200414723 Change-Id: I2a4290d2b9f80fdb66665ff4c8e8f3f163b9f2c3 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721543 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: resolve missing kfree error messageDebarshi Dutta2018-06-22
| | | | | | | | | | | | | | | | | | Insert the header <linux/slab.h> to resolve the kfree error for driver_common.c Bug 200414723 Change-Id: I2696b88d3a29decb2c984f69295274ccda6c0069 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721522 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: resolve missing DMA_ERROR_CODE error message.Debarshi Dutta2018-06-22
| | | | | | | | | | | | | | | | | | Add the header <linux/dma-mapping.h> to nvgpu_mem.c file to resolve compilation errors in linux-4.14 Bug 200414723 Change-Id: Ie6fd532688a1bf6d9705d423fcfde660693a3654 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721526 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: zero prealloc indices on initKonsta Holtta2018-06-21
| | | | | | | | | | | | | | | | | | Initialize the prealloc job list put and get indices to zero when allocating these resources. Otherwise we'd get whatever got left from the channel's previous lifetime. Change-Id: Idb17ec7bfbd0c1e2121c7a63e41dc5845560e988 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756871 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sami Kiminki <skiminki@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move slices_per_ltc & cacheline_size init to floorsweepingRichard Zhao2018-06-21
| | | | | | | | | | | | | It was initialized at .init_comptags, but we may also need them without comptags. Jira NVGPUT-63 Change-Id: Ie818c3ecf890fc84323b9662a32d666a6d2b3936 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756373 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: suspend/resume support for vGPUDeepak Bhosale2018-06-21
| | | | | | | | | | | | | | | | | | | | | | | - Added suspend/resume power management callbacks for vGPU - Added suspend/resume commands for communication between vGPU and RM server - Added suspend/resume message parameters for IVC messages between vGPU and RM server JIRA EVLR-2305 JIRA EVLR-2306 Change-Id: I83a314b4e125a53117d16c5ea72dbc5d8ef96ef7 Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735153 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: only free wait_cmd if it existsKonsta Holtta2018-06-21
| | | | | | | | | | | | | | | | | | gk20a_submit_prepare_syncs can fall to error handling paths without an allocated wait command buffer. In that case, just don't try to free the null wait_cmd; the user never requested one. Change-Id: Ice9041c0efa9bb14cde917e7ea82f4a7b6bf537c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756829 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sami Kiminki <skiminki@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: kernel version check for dma_buf_opsPritesh Raithatha2018-06-21
| | | | | | | | | | | | | | | | | | | In K4.14, dma_buf_ops members are renamed from kmap_atomic to map_atomic and kmap to map. So put the kernel version check to fix the build error for k4.14. Bug 200414723 Bug 200421495 Change-Id: Ic959960a43d2247f9cd4b530f9172a152bcbc08b Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747013 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not use NO_KERNEL_MAPPING for GRTerje Bergstrom2018-06-20
| | | | | | | | | | | | | | | | With arm64 mapping buffers to CPU is free. Remove the use of NO_KERNEL_MAPPING. Change-Id: Ic99ca6b7f8c698e2d3cb1d61a821939798bb237b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753709 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: split gk20a_submit_append_gpfifoKonsta Holtta2018-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_submit_channel_gpfifo the gpfifo entries can come from a kernel buffer or from userspace. To simplify the logic in gk20a_submit_append_gpfifo, extract out a function that copies the entries directly from userspace to the gpu memory for performance, and another function that copies from a kernel buffer to the gpu memory. The latter is used for kernel submits and when the gpfifo pipe exists which would mean that the gpfifo memory is in vidmem and is thus not directly accessible with a kernel virtual pointer. While this function is being changed a lot, also rename it to start with nvgpu_ instead of gk20a_. Additionally, simplify pushbuffer debug tracing by always using the kernel memory for the prints. Tracing when the gpfifo memory has been allocated in vidmem is no longer supported; sysmem is almost always used in practice anyway. Jira NVGPU-705 Change-Id: Icab843a379a75fb46054dee157a0a54ff9fbba59 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730481 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract away ioctl gpfifo readKonsta Holtta2018-06-20
| | | | | | | | | | | | | | | | | | | The biggest remaining Linuxism in the submit path is the copy_from_user() calls for reading the gpfifo entries to the HW-visible buffer. Abstract away the copy of one such segment starting at some offset and keep the wraparound logic and vidmem proxy in the core submit path. Jira NVGPU-705 Change-Id: I0c6438045c695e5e3f5da4fbc0c92d2c6e7f32cb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730480 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add submit entry points for kernel and ioctlKonsta Holtta2018-06-20
| | | | | | | | | | | | | | | | gk20a_submit_channel_gpfifo() supports reading the gpfifo entries from either a kernel buffer or an userspace buffer in an ioctl. Add two separate entry points: one for the ioctl and another for any other kernel use. This shortens the function prototypes and simplifies and clarifies the call sites slightly. Jira NVGPU-705 Change-Id: If5141a459261a451f78cc50972f4c94d95ba44d1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730479 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PG refcount check moved to a wrapper function.Vinod G2018-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | Moved PG refcount checking to a wrapper function, this function manages the refcount and decides whether to call dbg_set_powergate function. Instead of checking the dbg_s->is_pg_disabled variable, code is checking g->dbg_powergating_disabled_refcount variable to know if powergate is disabled or not. Updating hwpm ctxsw mode without disabling powergate will result in priv errors. Bug 200410871 Bug 2109765 Change-Id: I33c9022cb04cd39249c78e72584dfe6afb7212d0 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753550 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add API to print process nameKonsta Holtta2018-06-19
| | | | | | | | | | | | | | Add an OS-abstracted API for printing the name of the current process into a log message and convert the single occurrence of current->comm in submit path power failure to use it. Jira NVGPU-705 Change-Id: I1a509dcc5aecc3c89ce4582733888081b3e38f1f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1749833 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix fecs trace buffer indexesDeepak Nibade2018-06-18
| | | | | | | | | | | | | | Index for global_ctx_buffer #8 and global_ctx_buffer_va #5 are reserved Hence move FECS_TRACE_BUFFER to 9 and FECS_TRACE_BUFFER_VA to 6 Change-Id: I165842b6a68f67a8b357109988c87d4020c7b1ed Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1751500 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove PMC_ENABLE and PMC_ELPG_ENABLE accessesDeepak Nibade2018-06-18
| | | | | | | | | | | | | | | We don't need to enable l2/fb/hub/xbar from PMC_ENABLE or PMC_ELPG_ENABLE explicitly from nvgpu Remove the redundant code which accesses those registers Jira NVGPUT-51 Change-Id: I423d3bfc2f63460fc168815b5b5104962e3e72ef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1751445 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: cast cpu_va in priv cmdbuf traceKonsta Holtta2018-06-18
| | | | | | | | | | | | | Avoid arithmetic on a void pointer by casting the priv cmdbuf pointer to u32 first, then adding offset. Jira NVGPU-705 Change-Id: I6734a002bc376f6ff72e5b73b720921bfd63951f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1749899 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move Linux files away from commonTerje Bergstrom2018-06-15
| | | | | | | | | | | | | | | Move all Linux source code files to drivers/gpu/nvgpu/os/linux from drivers/gpu/nvgpu/common/linux. This changes the meaning of common to be OS independent. JIRA NVGPU-598 JIRA NVGPU-601 Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747714 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: recover on first interrupt reported for mmu nackAparna Das2018-06-15
| | | | | | | | | | | | | | | | | | | In case of mmu nack error interrupt is received twice through SM reported mmu nack interrupt and mmu fault in undertermined order. Recover on the first received interrupt to avoid semaphore release and skip doing a second recovery. Also fix NULL pointer dereference in function gv11b_fifo_reset_pbdma_and_eng_faulted when channel reference is invalid in teardown path. Bug 200382235 Change-Id: I361a5725d7b6355ebf02b2870727f647fbd7a37e Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1739804 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable watchdog for in-kernel CDE channelsKonsta Holtta2018-06-15
| | | | | | | | | | | | | | | | | | The watchdog tracks wall clock time. If the GPU's runlist is heavily congested, other work can last long enough to trigger the watchdog for trusted kernel channels too. We don't expect the CDE work to ever get stuck, so disable wdt there. Bug 200311892 Change-Id: I58c7d23891bc73aaeea0ccfcead567b3c6c13a52 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1493814 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unused variables in clkKonsta Holtta2018-06-15
| | | | | | | | | | | | | Delete a couple of unused struct pmu_msg locals from clk.c. Change-Id: Idc7b7e4d18eefb12c4b5c0ebb852f74f721fd0fc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1749927 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update ecc sysfs node handlingNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | | | | | | | | | | | Make ecc sysfs hash table per GPU by adding it as part of nvgpu_os_linux. Using a single hash table might give incorrect results as GPUs have same filenames and a filename is used as a key for a lookup. Add device_attribute as part of struct gk20a_ecc_stat. Using a single array of pointers of device attribute for an ecc_stat results in memory leak and incorrect stats if multiple GPUs are present on the system. This array of pointers will always hold info for GPU which created sysfs nodes last. Fix this by making device attribute array per ecc stat per GPU. Fix ecc stat removal to consider zero sub-units for a given number of hwunits. The multiplication with zero results in not removing any sysfs node at all. Bug 1987855 Change-Id: Ifcacc5623cede8decfe228c02d72786337cd0876 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move ecc sysfs funcs to a common fileNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | To make ecc sysfs related code reusable, move it to a seprate file. This allows possible optimizations with localized changes. There is no change in the code. Bug 1987855 Change-Id: I69aefb649df628d0c8dad529de6dde07ab4e6009 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735988 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add remove_gr_sysfs gpu opNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | | | | | | Add remove_gr_sys() op to gpu_ops to reverse steps done in create_gr_sysfs(). Make gv11b_tegra_remove() specific to gv11b instead to properly remove sysfs nodes. This also helps in having gv11b specific remove steps. Also, update platform remove function of dGPU i.e. nvgpu_pci_tegra_remove() to remove sysfs nodes. This adds parity with iGPU platform remove. Bug 1987855 Change-Id: Ibbaffac5c24346709347f86444a951461894354d Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735987 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: deprecate fb flush timeout registersDeepak Nibade2018-06-15
| | | | | | | | | | | | | | | FB flush timeout is deprecated in h/w and we use memop timeout instead which has same bits in the register Hence remove fb flush timeout accessors and use memop timeout ones Jira NVGPUT-50 Change-Id: Ia4696275f721f28cbb7e300889c4d70aaf0824ef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747956 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for PCI device 0x1ebaDeepak Nibade2018-06-15
| | | | | | | | | | | | | | | | | Add support for PCI device with ID 0x1eba Add corresponding platform data Change-Id: I2e5fe25666d4c00a6d4d27f0124fa02639f7aebd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746579 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: Unified CSS VGPU HALAntony Clince Alex2018-06-15
| | | | | | | | | | | | | | | | | - defined platform agnostic wrapper for mempool mapping and unmapping. - used platform agnositc wrapper for device tree parsing. - modified css_gr_gk20a to include special handling incase of rm-server JIRA: VQRM:3699 Change-Id: I08fd26052edfa1edf45a67be57f7d27c38ad106a Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1733576 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: removed linux includes from CSS HALAntony Clince Alex2018-06-15
| | | | | | | | | | | | | | | | | | | - removed inclusion of linux includes. - replaced with nvgpu/*.h's - reformated the function signature of "css_hw_get_pending_snapshot" and "css_hw_get_overflow_status" be global instead of static. - added get_pending_snapshot and get_overflow_status to ops->css. JIRA: VQRM-3699 Change-Id: I177904c263e143b414924c2c28ad6fd3cfd00132 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1732783 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract dt functionsRichard Zhao2018-06-15
| | | | | | | | | | | | Added nvgpu_dt_read_u32_index() for now. Jira VFND-4870 Change-Id: I3e51c408dfba3864372c515ba5d2c77708a489c8 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683008 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove deprecated ZBC registersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | All DS ZBC registers are non functional beginning Pascal and only the DSS ZBC registers are functional Hence remove access to deprecated ZBC registers Jira NVGPUT-25 Jira NVGPUT-107 Change-Id: I85ba13d2a9ec47b3fe98df7285f7a310ee69dadb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747933 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove extra deps to bus_gk20a.hTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | gk20a.c and mm_gk20a.c include bus_gk20a.h without needing anything from it. Drop that dependency. JIRA NVGPU-737 Change-Id: Ia1ae39248dad854797fb4be75c9ffeef3b191c7b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747766 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix userspace buildAdeel Raza2018-06-14
| | | | | | | | | | | | | | | | | | | | | The following changes moved/renamed/deleted files: - https://git-master.nvidia.com/r/#/c/1730893/ - https://git-master.nvidia.com/r/#/c/1730890/ These changes did not update Makefile.sources which is used by the userspace build. That's why the userspace build broke. This change updates Makefile.sources and fixes the userspace build. Change-Id: I011101c2f956cd1304d44d54d3e4a1a4cdfb6da9 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add HALs for mmu_fault setup and infoDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | Add below HALs to setup mmu_fault configuration registers and to read information registers and set them on Volta gops.fb.write_mmu_fault_buffer_lo_hi() gops.fb.write_mmu_fault_buffer_get() gops.fb.write_mmu_fault_buffer_size() gops.fb.write_mmu_fault_status() gops.fb.read_mmu_fault_buffer_get() gops.fb.read_mmu_fault_buffer_put() gops.fb.read_mmu_fault_buffer_size() gops.fb.read_mmu_fault_addr_lo_hi() gops.fb.read_mmu_fault_inst_lo_hi() gops.fb.read_mmu_fault_info() gops.fb.read_mmu_fault_status() Jira NVGPUT-13 Change-Id: Ia99568ff905ada3c035efb4565613576012f5bef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744063 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set hub interrupt enable/disable HALs for vGPUDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | Below HALs were missing in vGPU/gv11b. Add them. gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Jira NVGPUT-44 Change-Id: I981744b79e9fc0d72e6ab991b09bbbcb3f6bcd44 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744086 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cosmetic changes to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | | | A few review comments got lost in the review of moving bus code to common/bus. This takes care of renaming the header file protection define, deletes the unnecessary description of the file in header, and updates copyright years. Change-Id: Ib7dfe3d8fdf31ff3ea1fbf96fc41f9e454486dd1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741824 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10x PMU f/w version updateVaikundanathan S2018-06-14
| | | | | | | | | | | | | | -gp10x f/w version update for ucode https://git-master.nvidia.com/r/#/c/1748070/ Change-Id: Ie6f40fc931a24162497ef62778069814fd668c20 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1748071 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: effective freq load changesVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | | Read clk frequency through PMU RPC Bug 200399373 Change-Id: I9e887dcb1c5b622110eb4c1584f2f34434efd674 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701276 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Mask an unused HCE_ILLEGAL_OP InterruptVinod G2018-06-14
| | | | | | | | | | | | | | HCE interrupt is not being used in nvgpu platform now, masking the bit from the interrupt register. bug 2082123 Change-Id: I1d53584afebe57b9621c8f4ec395cd1dcd6c7611 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746850 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: warn if cde fails to find addr to patchKonsta Holtta2018-06-14
| | | | | | | | | | | | | | | | Print the surface address for which we fail to resolve an iova address when patcing cde parameters. This appears to happen extremely rarely for yet unknown reasons. Bug 2038362 Change-Id: I5ca300ea9b2f8c8867b7b43e37f51a50836129b7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1748455 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add support for FECS VAVaibhav Kachore2018-06-14
| | | | | | | | | | | | | | | | | Enable FECS trace support for t194 Linux + HV EVLR-2309 Change-Id: If22c931a54833eb995710b6e0dcad335e4ffbae6 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674970 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for FECS VAVaibhav Kachore2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - On t186, ucode expects physical address to be programmed for FECS trace buffer. - On t194, ucode expects GPU VA to be programmed for FECS trace buffer. This patch adds extra support to handle this change for linux native. - Increase the size of FECS trace buffer (as few entries were getting dropped due to overflow of FECS trace buffer.) - This moves FECS trace buffer handling in global context buffer. - This adds extra check for updation of mailbox1 register. (Bug 200417403) EVLR-2077 Change-Id: I7c3324ce9341976a1375e0afe6c53c424a053723 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: increase bios size to 0x90000Deepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | bios size is currently set to 0x40000, but this could insufficient on some platforms Increase it to 0x90000 so that we have buffer of sufficient size to store bios content Change-Id: I510d10763b1fc6ba427680e44a55e3604f67e049 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746578 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate vsm mapping based on nonpes_aware_tpcseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. For user space to be in sync with hw populate vsm mapping based on nonpes_aware_tpcs. Bug 200405202 Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744304 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct calculation of sm_id for .record_sm_error_stateRichard Zhao2018-06-14
| | | | | | | | | | | | | | | | | | Starting with Volta, one TPC could have more than 1 SMs. So .record_sm_error_state needs to have sm number as parameter. Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r. Let the function return logical sm_id. RM server will need it to nofify client. Jira EVLR-2643 Bug 200405202 Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742165 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle replayable mmu fault during waiting for SM lockdownRichard Zhao2018-06-14
| | | | | | | | | | | | | | outstanding replayable mmu fault will prevent SM from lockdown, so handle the replayable mmu fault while polling lockdown status. Jira EVLR-2643 Bug 200405202 Change-Id: I811f16ef4394a6cc42a5f37a17e426dd749c5652 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741997 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove duplicate NVGPU_SUPPORT_IO_COHERENCE enableAnup Kumar Sah2018-06-14
| | | | | | | | | | | | | | | | | | NVGPU_SUPPORT_IO_COHERENCE is already set in gk20a_probe based on the presence of dma-coherent property of gpu DT so this change removes the redundant enable in gv11b_init_gpu_characteristics VQRM-4044 Change-Id: I8c8d8d485f00aec6fae7a6794fecd855ce3a0004 Signed-off-by: Anup Kumar Sah <asah@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741090 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 02:21:33 -0500