| Commit message (Collapse) | Author | Age |
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This is needed to handle new pbmda intr_1 in t19x
JIRA GPUT19X-47
Change-Id: If75de0b57f3f18420aff07ee99feaad67ac63752
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1329373
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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It'll let gpu tests pass by using sem before enabling syncpt.
Especially for vgpu, the plat data is shared across different GPUs, so
we can use dt to override and disable syncpt.
Jira VFND-3796
Change-Id: I2cc32a1ea1cc1097047427eb1e52ec50c3a0bf90
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1507494
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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Add gm20b "B" revision chipip.
Bug 1870669
Change-Id: Ife31e6d739aabb8ef4a4f401091c3202b415a70e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1490650
Reviewed-by: Samuel Payne <spayne@nvidia.com>
Signed-off-by: Samuel Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/1490648
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- set nvgpu_flcn_reset() to point to gk20a_pmu_reset()
- set PMU interrupt using nvgpu_flcn_enable_irq()
- replace pmu_idle with nvgpu_flcn_wait_idle()
JIRA NVGPU-57
Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1469478
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added flacon reset dependent interface & HAL
methods to perform falcon reset.
- method to wait for idle
- method to reset falcon
- method to set irq
- method to read status of CPU
- Updated falcon ops pointer to point gk20a
falcon HAL methods
- Added members to know support of falcon
& interrupt.
- Added falcon dependency ops member to support
flacon speicifc methods
JIRA NVGPU-99
JIRA NVGPU-101
Change-Id: I411477e5696a61ee73caebfdab625763b522c255
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1469453
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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H/W header for gk20a, gm20b, gp10b &
Gp106 falcon controller.
JIRA NVGPU-56
Change-Id: Iec2066f83f499e86f5d28860ffaa6bdac0716c71
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1331258
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Reorder non-function pointer members of gpu_ops to be at the
very end of their respective sub-structs. This allows for
easier debug interpretation and slightly improves readability.
Jira NVGPU-107
Change-Id: Ife3279180306de70f7fad6760f616c6d69769b36
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: http://git-master/r/1506591
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move devfreq field from struct gk20a to os_linux. It's a Linux
specific framework.
JIRA NVGPU-38
Change-Id: I1e00f5a80e31deb4aaba379274c3a7a7b04d963b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505176
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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dma_params is inherently a Linux structure, so move it to os_linux.
JIRA NVGPU-38
Change-Id: If81249b3cb7d65187202df72b35a1d24e274263b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505928
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move Linux devnode related fields to a new header file os_linux.h.
The class structure is defined in module.c, so move its declaration
to module.h.
JIRA NVGPU-38
Change-Id: I5d8920169064f4289ff61004f7f81543a9aba221
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505927
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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linux/version.h and linux/sched.h are not used by gk20a.h, so remove
them.
acr_gm20b.h and bus_gk20a.h are not needed by gk20a.h, so remove them.
pmu_gp106.c relies on implicit #include of acr_gm20b.h by gk20a.h, so
add that as an explicit #include.
Remove #include of iomap.h. platform_gk20a_tegra.c legacy rail gating
code still relies on access to that header, so add it as explicit
include.
JIRA NVGPU-38
Change-Id: I1cf57b9d3a7ee5e3cad298341107e317b4b8662f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505926
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When contexts are unloaded from GR, the valid bit is reset
but the instance pointer information remains intact.
Check valid bit in *is_channel_ctx_resident* function as
valid bit might not be set when *get_channel_from_ctx function*
is called from gr_isr
Bug 200289491
Change-Id: I4da7f04794c7e7e80b511756dbd851205cd76fbc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1505908
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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ctx id should be read from right mem area else
it will return 0 and cause issue with fecs methods
that depend on ctx id
Bug 200289491
Change-Id: Iba74f653afccf34e95cd90175833e3270239c264
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1505902
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Enable the log.h debug printing to print log messages on
boot based on the NVGPU_DEFAULT_DBG_MASK define. Previously
this only affected the legacy gk20a_dbg() function which
is being slowly phased out.
Change-Id: I74caed3bcdeec5481fb34e3151cfbc1acaabf233
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1505922
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add backward support for HW2.5 Rev.A board:
- no INA3221 for voltage, current, and power
- use PG418 MCLK switching sequences
Allow VBIOS from .53 for PG419
Bug 1929155
Change-Id: Ifacfc8cff6d00f66af92305119d0f0d3b9a1e438
Reviewed-on: http://git-master/r/1497001
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
(cherry picked from commit 952778f814916b0b3d5043c43755bfccb467c3d4)
Reviewed-on: http://git-master/r/1497295
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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move mclk switching to gp106 hal.
Bug 1921082
JIRA EVLR-1269
Change-Id: I97812b871384460bec88fddac0f6a326df12fc45
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1499393
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VBIOS memory settings have been updated for PG419, significantly
modifying MCLK switching sequences. This change adds support for
PG419 tables, while remaining backward compatible with PG418.
Bug 1921082
JIRA EVLR-1269
Change-Id: Ia8a1f8b3f482e348a46f0acb540af23287d9c11e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1484110
(cherry picked from commit c2444ae89caf97da2702e8486cc8fb162b4f50b1)
Reviewed-on: http://git-master/r/1485300
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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tegra/linux path was created to separate Tegra kernel specific
dependencies from common Linux specific dependencies. The split has
not really worked, so merge tegra/linux to common/linux.
JIRA NVGPU-38
Change-Id: I582e12a0a8b5de62a29e41a37f4f8b8caae955fc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505178
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Always check for valid channel gr_ctx before issuing channel
preempt. Commands like "echo > /dev/nvhost-gpu" create channel
to just power-up gpu without any valid channel context. So
don't try to preempt those channels.
Bug 1937331
Change-Id: I48a4bfd35728b83b27eb968e51a56b900d1fa799
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1505783
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Instead of the very coarse jiffies, use the more accurate monotonic
Linux ktime API for the nvgpu timeout API.
The expiration time is handled as an u64 nanosecond value to hide the
ktime_t from the public nvgpu_timeout struct. The conversion is cheap.
Jira NVGPU-83
Change-Id: I08a0a67be8935d46f05356162281463d4eb6f4ae
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1505390
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove pointer to struct device from gk20a_gpu_ctx. The pointer is
not used anywhere, and it adds an unnecessary Linux dependency.
JIRA NVGPU-38
Change-Id: Id5843a21e4809ca840e4f5d561728f859bbd964e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505202
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Pass struct gk20a to secure alloc API instead of Linux specific
struct device.
JIRA NVGPU-38
Change-Id: I6d9afaeeff9b957351072caa29690f2caf58f858
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505179
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Pass struct gk20a pointer to gk20a_busy_noresume() and
gk20a_idle_nosuspend(). This reduces the number of dependencies to
Linux specific struct device.
JIRA NVGPU-38
Change-Id: I5e05be32e2376bc8be5402bb973c20e28c35a1c3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505177
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Delete a version of WRITE_ONCE() that gk20a.h defines only for
kernels older than 3.18. We don't support kernels below 4.4.
JIRA NVGPU-38
Change-Id: I0af50936523fde9929c21eea0547b91dac4a0081
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505175
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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We don't use cooling device, so delete its definition from gk20a.h.
JIRA NVGPU-38
Change-Id: Ie39d3dea4f0de870ebe6493bbf90a286452ae61d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505174
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Move internal channel trace function to ioctl_channel.c. It's not
used anywhere else, so it does not need to be exported outside
ioctl_channel.c.
JIRA NVGPU-38
Change-Id: If6300781961ffffad4f63bc212d68adf8f3497fc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505173
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The function tsg_gk20a_from_ch() is an operation on tsg_gk20a
structure, so move it to be part of tsg_gk20a.c and export
via tsg_gk20a.h.
JIRA NVGPU-38
Change-Id: I2afba3533ac829088a5edf8b16cf4e071b69b77a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505172
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Time correlation does not have chip or OS specific dependencies, so
move it to generic new source file bus.c.
JIRA NVGPU-38
Change-Id: Ic7fdf8c9ccacf05baf1b3438a86b28e517093641
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505171
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The gk20a_channel_wait() ioctl still considers a timeout value type to
be jiffies, but NVGPU_COND_WAIT_INTERRUPTIBLE takes milliseconds. Pass
the millisecond value from args directly to the cond wait.
NVGPU_NO_TIMEOUT is the max unsigned value that fits in 32 bits, so it
does not need to be tested explicitly.
Jira NVGPU-83
Change-Id: If7979c015696b2d1e0bbe9612c546410a0f41f2e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1505422
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Currently callbacks from the PM_QOS framework (for
thermal events), result in a RPC call to set GPU frequency.
Since the governor will now be responsible for setting desired
rate, the max PM_QOS callback will now cap the possible
GPU frequency w/ a new RPC call to the server. The server
is responsible for setting the ultimate frequency
based on the cap & desired rates.
Jira VFND-3699
Change-Id: I806e309c40abc2f1381b6a23f2d898cfe26f9794
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1295543
(cherry picked from commit e81693c6e087f8f10a985be83715042fc590d6db)
Reviewed-on: http://git-master/r/1282467
(cherry picked from commit 7b4e0db647572e82a8d53e823c36b465781f4942)
Reviewed-on: http://git-master/r/1321836
(cherry picked from commit 57dafc08a57ea768eb302bf1adb901425ce2f835)
Reviewed-on: http://git-master/r/1313469
Tested-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add devfreq governor support in order to allow frequency scaling
in virtualization config. GPU clock frequency operations are
re-directed to the server over RPC.
Bug 200237433
Change-Id: I1c8e565a4fff36d3456dc72ebb20795b7822650e
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1295542
(cherry picked from commit d5c956fc06697eda3829c67cb22987e538213b29)
Reviewed-on: http://git-master/r/1280968
(cherry picked from commit 25e2b3cf7cb5559a6849c0024d42c157564a9be2)
Reviewed-on: http://git-master/r/1321835
(cherry picked from commit f871b52fd3f553d6b6375a3c848fbca272ed8e29)
Reviewed-on: http://git-master/r/1313468
Tested-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
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msleep is not recommended for (1ms - 20ms). So use usleep_range
instead to have a more deterministic sleep time.
Also fix the print for target_ref_count that could either be 2 or
1 based on whether GPU rail-gating is enabled or not.
Bug 200294536
Change-Id: I26c9ed8a1badc84db5efa89347a227e6b46f603c
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/1500409
Reviewed-on: http://git-master/r/1503628
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Remove the two other unnecessary options based on jiffies and
gettimeofday, leaving only the time stamp counter clocksource.
Jira NVGPU-83
Change-Id: I289951aba832eda36cb9cb68b7e41e6061ec3a03
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1503000
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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This patch also adds new interface for GR INIT PARAM cmd
and adds new pmu command to update sub-feature mask for ELPG.
JIRA GPUT19X-20.
Change-Id: Id3b3b65882c714f80a05de5660895258b26a08bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1503141
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Save the time using nvgpu_current_time_ms() instead of the
Linux-specific jiffies counter.
Jira NVGPU-83
Change-Id: I19b4296d8b64ddf52506144e77d151f668ff7838
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1503002
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add nvgpu_current_time_ms() to return a time from a monotonic clock
source in milliseconds. The start time is unspecified; this API is meant
to be used for duration measurements.
Jira NVGPU-83
Change-Id: I135c8ee88283149422a68d5fa859241eebbd6459
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1503001
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Instead of using raw jiffies, use milliseconds and the nvgpu timeout
API. The COND_WAIT API uses also just milliseconds.
Jira NVGPU-83
Change-Id: I21b5e0880f0b6aa02856d7c207be97861e423b6b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1502999
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Get rid of manual timeout tracking with jiffies in xve_gp106.c by using
the timeout API instead.
Jira NVGPU-83
Change-Id: Ida45539e05ac4de2a9d747170627c7104f27a544
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1502998
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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If platform probe fails as a result of DEFER_PROBE, it should be
reported as dev_info instead of dev_err.
Bug 1926777
Change-Id: Iba4392abdd6089da9678695b8ee7f2c92bea1505
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: http://git-master/r/1492711
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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When the pmu reaches PMU_STATE_STARTED, exit from the nvgpu_pg_init_task
thread as it's no longer necessary. This prevents a possibly long wait
on the signaling condition, which would make Linux think that the thread
has been blocked and print a warning.
Bug 200317814
Change-Id: I4104896867ee13eb9d53b1b19b659a7839adb73f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1501504
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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It's technically possible for a thread to exit without first calling
nvgpu_thread_stop() in another, so mark the thread exit status from the
thread after it has finished instead of in nvgpu_thread_stop(). Do this
by starting the thread as a proxy function which calls the actual thread
function and then sets the flag.
Also, add a new flag to actually signify the running state because the
thread->task going null abruptly would break nvgpu_thread_stop().
This does not guarantee that the kernel thread itself has stopped, but
the function which can be considered as an "nvgpu thread" will be.
Change-Id: Ib911b02bd51342ddeb8e6b9533ef7943f2606d2d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1501571
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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In order to perform timestamps correlation for FECS
traces, we need to collect GPU / GPU timestamps
samples. In virtualization case, it is possible for
a guest to get GPU timestamps by using read_ptimer.
However, if the CPU timestamp is read on guest side,
and the GPU timestamp is read on vm-server side,
then it introduces some latency that will create an
artificial offset for GPU timestamps (~2 us in
average). For better CPU / GPU timestamps correlation,
Added a command to collect all timestamps on vm-server
side.
Bug 1900475
Change-Id: Idfdc6ae4c16c501dc5e00053a5b75932c55148d6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1472447
(cherry picked from commit 56f56b5cd9d2e75cf7d2613b5e115bfebdbee0ce)
Reviewed-on: http://git-master/r/1489183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Moved perfmon code from pmu_gk20a.c to
"drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c" file
-Moved below related methods
perfmon init,
start/stop sampling,
load counter read/write/reset,
perfmon event handler
- prepend with nvgpu_ for perfmon global methods
by replacing gk20a_
JURA NVGPU-56
JURA NVGPU-98
Change-Id: Idbcdf63ebd76da170e609cc401b320a42110cd7b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1501418
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove <soc/tegra/fuse.h> includes and include
<nvgpu/fuse.h> header to remove direct dependency
on platform specific header
Use specific APIs like below to read/write fuses
nvgpu_tegra_fuse_write_bypass()
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable()
Remove old code which was compiled for kernel versions
less than 4.4 since we support only k4.4 and greater
versions now
Jira NVGPU-75
Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Add below new APIs in common/linux/fuse.c and export them from
include/nvgpu/fuse.h to read/write specific tegra fuse offsets
void nvgpu_tegra_fuse_write_bypass(u32 val);
void nvgpu_tegra_fuse_write_access_sw(u32 val);
void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val);
void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val);
int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val);
int nvgpu_tegra_fuse_read_reserved_calib(u32 *val);
These APIs are needed to remove nvgpu's direct
dependency on platform specific <soc/tegra/fuse.h> header
Remove below generic APIs since they are no longer needed :
nvgpu_tegra_fuse_read()
nvgpu_tegra_fuse_write()
Jira NVGPU-75
Change-Id: I366e6a3382f0c392b2132f4d3a7e286306bb2ec2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497517
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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To make do_idle work when nvgpu is built as a module, reverse the order
of call dependencies for do_idle. Don't provide visible
gk20a_do_{idle,unidle}() functions for the kernel but instead call the
kernel for registering and unregistering pointers to them when the
driver loads and unloads.
Refactor the internal __gk20a_do_{idle,unidle} functions to take a
struct gk20a * instead of struct device *, and use the callback api for
providing that g instead of retrieving the plat device from device tree.
Bug 200290850
Change-Id: Ibef8b069302e547b298069cbb97734f461a10cc3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1493774
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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To support deterministic channels even with platforms where railgating
is supported, have each deterministic-marked channel hold a power
reference during their lifetime, and skip taking power refs for jobs in
submit path for those.
Previously, railgating blocked deterministic submits in general because
of gk20a_busy()/gk20a_idle() calls in submit path possibly taking time
and more significantly because the gpu may need turning on which takes a
nondeterministic and long amount of time.
As an exception, gk20a_do_idle() can still block deterministic submits
until gk20a_do_unidle() is called. Add a rwsem to guard this. VPR resize
needs do_idle, which conflicts with deterministic channels' requirement
to keep the GPU on. This is documented in the ioctl header now.
Make NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING always
set in the gpu characteristics now that it's supported. The only thing
left now blocking NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL is
the sync framework.
Make the channel debug dump show which channels are deterministic.
Bug 200291300
Jira NVGPU-70
Change-Id: I47b6f3a8517cd6e4255f6ca2855e3dd912e4f5f3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1483038
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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ioctl function name and number are printed if
gk20a_dbg_fn is enabled. This is good to have for
debugging.
Change-Id: I4d0f99affaba493a4c586559d699f86174e4c64d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1498750
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fixup a minor spacing issue in the VM code.
Change-Id: Ia4aaa3cdd7cb63958870cebb51821bf640d56123
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1499446
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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- moved pg related code to pmu_pg.c under common/pmu folder
PG state machine support methods
PG ACK handlers
AELPG methods
PG enable/disable methods
-prepended with nvgpu_ for elpg/aelpg global methods
by replacing gk20a_
JIRA NVGPU-97
Change-Id: I2148a69ff86b5c5d43c521ff6e241db84afafd82
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1498363
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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