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* gpu: nvgpu: gp10b: Use gp10b version of phys bitsTerje Bergstrom2016-12-27
| | | | | | | | Use gp10b version of get_physical_addr_bits. Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/714402
* gpu: nvgpu: add exception registers to dumpDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | Add below exception registers to GR dump : NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN Bug 200078514 Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/712481 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix swdx_rm_spill size and pointerKirill Artamonov2016-12-27
| | | | | | | | | | | | | Fixed incorrectly encoded pointer and size. bug 1525327 bug 1581799 Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/713209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add replayable pagefault bufferSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for replayable fault buffer and enable it. Bug 1587836 Change-Id: Iee4ba42ab175c0d72d2c041fdb3ac9d845358847 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/661668 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: support for replayable faultsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | Add support for enabling replayable faults during channel instance block binding. Also fixed register programing sequence for setting channel pbdma timeout. Bug 1587825 Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681703 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: setup mm hw initSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for gp10b specific mm hw init. Bug 1587825 Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update fb headersSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Update fb header with new mmu invalidate fields. Bug 1587836 Change-Id: I33a30dc742f35d325c528a9bc73fea8cfc21e856 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/680800 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update headersSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Sync with latest hw includes and generated header files. Bug 1587825 Change-Id: I165b541e3215245eb43614e34670093b8420a7df Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/709881 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ce interrupt supportSam Payne2016-12-27
| | | | | | | | | | | | | ce interrupts use different register mapping and format from gk20a and gm20b. Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/681646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add ELPG_ENABLE registerTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I8b2272641c7f406cec9bb2649846e4b4b195e21a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/708720 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b specific LTC ISRTerje Bergstrom2016-12-27
| | | | | | | | | | | LTC interrupt register got moved, so use the new offset. Bug 1587638 Change-Id: I3dbd44d92f2bcb3634c21ed46870ec1620d936cf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709571 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Set correct PBDMA signatureTerje Bergstrom2016-12-27
| | | | | | | | | GPFIFO class was set to Maxwell class number. Also implement the PBDMA signature HAL. Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/672921
* gpu: nvgpu: gp10b: Enable warnings as errorsTerje Bergstrom2016-12-27
| | | | | | Change-Id: I86de27309ebecd038a7b32c6f86d87ce0156eb14 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709867
* gpu: nvgpu: reg with FECS HALT methodSupriya2016-12-27
| | | | | | | | Change-Id: Ia196b98c79a71c9545e555260660e274982455a3 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/709279 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: dump GR status registersDeepak Nibade2016-12-27
| | | | | | | | | | | | | Add function pointer gr_gp10b_dump_gr_status_regs() which will enable dumping GR status registers for gp10b Bug 200062436 Change-Id: Iaecc2f9c9364232079bb03e114f68550bd035372 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/678832 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: use tight loop for fecs methodVijayakumar2016-12-27
| | | | | | | | | | | bug 200078367 Change-Id: I9a68e988fa7921276e334c75afa5ee4b15aab464 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/707313 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: headers for linsim CL 34116551Peng Du2016-12-27
| | | | | | | | | Change-Id: Ia8760772b0135813475f96a786484d7caef3759d Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/677464 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: gp10b: Enable debug spewTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I58811bbce0e39b85074f3aa9022a730f696e407e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/679704 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: enable CDE for t18xJussi Rasanen2016-12-27
| | | | | | | | | | | | Mark CDE as supported on t18x. Change-Id: I03c23178712b9018137edddfa8e1ff3a2ad9106c Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/672384 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: read gobs_per_comptagline_per_sliceJussi Rasanen2016-12-27
| | | | | | | | | | | | Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE during t18x ltc init and store it for use in CDE code. Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441 Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/673150 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Compression page size to 64kTerje Bergstrom2016-12-27
| | | | | | | | | Define compression page size for gp10b to be 64k. We also need to copy some LTC initialization code from gm20b to gp10b. Change-Id: I0235c32cdb1486a23d33eb98ebbc79c97a3c32d4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/677837
* gpu: nvgpu: gp10b: Add Bar2 supportSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | Add bar2 support for gp10b and set-up bar2 binding. Bug 1587825 Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/659236 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable replayable fault interruptSeshendra Gadagottu2016-12-27
| | | | | | | | | | Bug 1587825 Change-Id: I6df2f870b4488bb3d5ada52b4819f6f80624becd Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/659092 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: headers for linsim CL 34000094Adeel Raza2016-12-27
| | | | | | | | Change-Id: I43380fda328414e96601e1c03c3e0ec28c0b4871 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/666905 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update headersSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Update replayable page fault fifo, interrupt and bar2 block headers. Bug 1587825 Change-Id: Ifa0d3b640bdd5f3f6fbc7826c1d1edba494340df Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/661117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Enable cycling through ctx binsTerje Bergstrom2016-12-27
| | | | | | | | | | | Remove hard coded NETB for gp10b. This enables cycling through available firmware files. Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/676557 Reviewed-by: Peng Du <pdu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Default page size 64kBTerje Bergstrom2016-12-27
| | | | | | | | | | Set default big page size to 64kB. Bug 1592495 Change-Id: Id23dac012cde75f2809a49779e1a1cee879d08a0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/671705
* gpu: nvgpu: gp10b: Fix L2 size calculationTerje Bergstrom2016-12-27
| | | | | | | | | | L2 size is expressed in kB, so add a multiplier. Bug 1592495 Change-Id: I4c10034cd21bf874c84c96f1adc25261b195063d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/671704
* gpu: nvgpu: gp10b: Enable CILP mode for computeTerje Bergstrom2016-12-27
| | | | | | | | | | | Allow enabling CILP for compute. Set CTA by default. Bug 1517461 Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/661298 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Handle MC pmu interruptsMahantesh Kumbar2016-12-27
| | | | | | | | | | - Made changes to MC to get pmu interrrupts Change-Id: I07aaec8392b1fbb34ae727bc7547a571aaeeb814 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/661212 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gp10b: gpmu elpg supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | Temporally used gm20b elpg sequencing values for gp10b elpg. Bug 1525971 Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/662517 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement gp10b context creationTerje Bergstrom2016-12-27
| | | | | | | | | | | Implement context creation for gp10b. GfxP contexts need per channel buffers. Bug 1517461 Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660236
* gpu: nvgpu: gp10b: Correct SMMU bit numberTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Bit 36 is the correct bit to indicate SMMU translation. Bug 1580756 Change-Id: I761e70265d5981b07940f1d43716416829993827 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/658827 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
* gpu: nvgpu: gp10b: Change order of alpha & betaTerje Bergstrom2016-12-27
| | | | | | | | | Change order of alpha & attribute buffers in CB. The new order follows RM. Change-Id: I2b24daa46055b3bd667a1026c282f74d56882623 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657907
* gpu: nvgpu: gp10b: Program CB sizesTerje Bergstrom2016-12-27
| | | | | | | | | | | Program CB sizes. Bug 1567274 Change-Id: Idc88f69b70e85bf950af852a9ca80a328d95883f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/654097 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Implement SW methodsTerje Bergstrom2016-12-27
| | | | | | | | Bug 1567274 Change-Id: I6d760eca7ac0931847f9a04a9d4a408519ade511 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/654098
* gpu: nvgpu: gp10b: Calc global context buffer sizeTerje Bergstrom2016-12-27
| | | | | | | | | | In gp10b we need to limit global context buffer size, and it needs to be 128b aligned. Change-Id: I51570e2457a374c09be4d611e683ae30917f9fc0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657911 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Add new supported kindTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606931 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Define pagepool sizeTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I4369458d3af0c4da32af8a5881c8fe60b11f7632 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606932 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Define physical address widthTerje Bergstrom2016-12-27
| | | | | | | | | | | | GP10B physical address width is 37 bits. Use old width for now, and add gp10b specific definition. We can switch to new definition once we've verified them. Bug 1567274 Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601703
* gpu: nvgpu: Write ZBC registers to DSSTerje Bergstrom2016-12-27
| | | | | | | | Bug 1567274 Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601108
* gpu: nvgpu: Define gp10b big page sizeTerje Bergstrom2016-12-27
| | | | | | | | | | Set default big page size of 128kB. Bug 1567274 Change-Id: Ie27c6ffa23b8d75ebd21afca267068604fb57f0b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/603498
* gpu: nvgpu: Add SM registersTerje Bergstrom2016-12-27
| | | | | | | | | | | | Add SM registers which were taken into use in GPU characteristics. Bug 1551769 Bug 1558186 Change-Id: I705da9ac25556b6b94137199e0acd9af3c8e6422 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601020
* gpu: nvgpu: Use queried interrupt idsTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I258b54447d09b32adc076de50997d792f0567af5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601019 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Implement L2 queryTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/602858 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: headers for linsim CL 33823014Adeel Raza2016-12-27
| | | | | | | | | Change-Id: I1b9172f0afa0391ce6289aa24dc1a993c723c90e Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/594681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Enable interrupts in linsimTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I7d4211743793b905a20080bb44c62c036f23c854 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592336 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Fill class numbersTerje Bergstrom2016-12-27
| | | | | | | | | | | Fill class numbers to characteristics structure. Bug 1567274 Change-Id: I129e79fa3f850899ae0c7d93704dc4786ad514d9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/594404 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Add own platform data to enable host1xTerje Bergstrom2016-12-27
| | | | | | | | | | | Add gp10b platform data to enable sync point support. Bug 1572701 Change-Id: Iaf03ecb8fb6b8bf4bb824e2a012c80dfe3f4fcae Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592099 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Add SM debug registersTerje Bergstrom2016-12-27
| | | | | | | | | | Add SM debug registers to gp10b, and regenerate headers. Bug 1567274 Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592646
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