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* gpu: nvgpu: add resume_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I844b5cf02a75ba397891a1100d917875e5a3e181 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512217 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add resume_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512216 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add suspend_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Icdae3b6ed67a3d3deeb17f29528184b2d7a70af5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512215 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add suspend_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Id104f611736535874cdaa5a2f768f692d799c2c5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512214 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add sm_debugger_attached gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support t19x sm register address changes JIRA GPUT19X-75 Change-Id: I7f961147e0e6464a71e240487f7bc964b0544e5d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: replace gk20a_dbg_* with nvgpu_dbg_*Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | -replace gk20a_dbg_* statements with nvgpu_dbg_* for PMU in drivers/gpu/nvgpu/common/pmu folder JIRA NVGPU-93 Change-Id: Id616d1f5cb5ce4007bc9543f05e57e4631cdd691 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512925 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: rename gk20a_pmu_cmd_post()Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | | - rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Falcon controller halt interrupt status clearMahantesh Kumbar2017-07-04
| | | | | | | | | | | | | | | | | | | | | - Added nvgpu_flcn_clear_halt_intr_status() to Wait for halt interrupt status clear by clear_halt_interrupt_status() HAL within timeout - Added gk20a_flcn_clear_halt_interrupt_status() to clear falcon controller halt interrupt status - Replaced flacon halt interrupt clear with nvgpu_flcn_clear_halt_intr_status() method NVGPU JIRA-99 Change-Id: I762a3c01cd1d02028eb6aaa9898a50be94376619 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1511333 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Falcon controller wait for haltMahantesh Kumbar2017-07-04
| | | | | | | | | | | | | | | | | | | - Added nvgpu_flcn_wait_for_halt() interface to wait for falcon halt, which block till falcon halt or timeout expire for selected falcon controller - Replaced falcon wait for halt code with method nvgpu_flcn_wait_for_halt() NVGPU JIRA-99 Change-Id: Ie1809dc29ff65bddc7ef2859a9ee9b4f0003b127 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1510201 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: falcon HAL to support SEC2Mahantesh Kumbar2017-07-03
| | | | | | | | | | | | | | | | | | - Updated falcon controller HAL to support SEC2 falcon & used "is_falcon_supported" flag to know the support on chip. - Created falcon HAL “flcn_gp106.c/h” under gp106 to enable support for SEC2 & inherited gk20a flcn support. - Deleted SEC2 falcon related methods to make use of generic flacon controller methods for SEC2. - GP106 SEC2 code cleanup NVPU JIRA-99 Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1510200 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: PMU IMEM/DMEM scrubbing cleanupMahantesh Kumbar2017-07-03
| | | | | | | | | | | | | | | PMU IMEM/DMEM scrubbing completion check is part of PMU reset, so removing explicit IMEM/DMEM scrubbing check NVGPU JIRA-99 Change-Id: I4553701fd8c08217e109ef3a5fe1e33e372c26d4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1510202 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gp10b_ce_isr declared non-staticSeema Khowala2017-07-02
| | | | | | | | | | | | | Required for t19x ce isr handling JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: I18558d633012205f7e0920da65c8d9e89aab906d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1510290 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add ops to support t19x ce changesSeema Khowala2017-07-02
| | | | | | | | | | JIRA GPUT19X-46 Change-Id: Idd17f2f644da1bbb8d31a55ac91561b25ff68aac Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1509749 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: Makefile: Change include paths to t19xIshan Mittal2017-07-01
| | | | | | | | | | | | nvhost-t19x source now resides in t19x Bug 200295104 Change-Id: I1ee1e260340268c8d1b873d3c2f1ee6ab90d9611 Signed-off-by: Ishan Mittal <imittal@nvidia.com> Reviewed-on: https://git-master/r/1506454 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Init cfg variable to avoid warningAlex Frid2017-06-30
| | | | | | | | | | | Change-Id: I485e4267766b5e906d1ea5e19ff33712fb4ff8df Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master/r/1511785 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Samuel Payne <spayne@nvidia.com> Tested-by: Samuel Payne <spayne@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Enable GM20B GPCPLL C1 in calibrationAlex Frid2017-06-30
| | | | | | | | | | | | | | | | | | Enabled GM20B GPCPLL revision C1 during internal calibration in order to read calibration status and results. Bug 1942225 Change-Id: I8fb5f43669bb308de7439792033f640d26f8a3dd Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1504228 (cherry picked from commit a5bed86858fe0e28482bea1a57ecd3085f146ad1) Reviewed-on: https://git-master/r/1511085 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Samuel Payne <spayne@nvidia.com> Tested-by: Samuel Payne <spayne@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Use accessor for finding struct deviceTerje Bergstrom2017-06-30
| | | | | | | | | | | | | Use dev_from_gk20a() accessor whenever accessing struct device * from struct gk20a. JIRA NVGPU-38 Change-Id: Ide9fca3a56436c8f62e7872580a766c4c1e2353e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507930 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Convert logging from dev_*() to nvgpu_*()Terje Bergstrom2017-06-30
| | | | | | | | | | | | Convert a few calls from dev_*() logging to nvgpu_*(). This reduces dependency to Linux specific struct device pointer. JIRA NVGPU-38 Change-Id: Ib51a6b1287db25b7dd4d164aec3ac75fa2801ebf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507929 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Per chip default big page sizeTerje Bergstrom2017-06-30
| | | | | | | | | | | | | | Make default big page size query a HAL op instead of per-platform constant. This allows querying for default big page size without accessing Linux specific gk20a_platform structure. JIRA NVGPU-38 Change-Id: Ibfbd1319764fdae5fdb06700fb64d23f6f3dd01a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507928 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove gk20a supportTerje Bergstrom2017-06-30
| | | | | | | | | | | | Remove gk20a support. Leave only gk20a code which is reused by other GPUs. JIRA NVGPU-38 Change-Id: I3d5f2bc9f71cd9f161e64436561a5eadd5786a3b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507927 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: rename pmu_mclk_gp106 to mclk_gp106Thomas Fleury2017-06-30
| | | | | | | | | | | | | | | Rename files, as they are not directly related to PMU. They just send commands to PMU, similar to all other clock change codes. Bug 1921094 Change-Id: I4a67d4c950d995c68cfce464108cd36104f44080 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master/r/1508820 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move mclk_init to pstate_pmu_supportThomas Fleury2017-06-30
| | | | | | | | | | | | | | | Preparation for all clock changes should happen in P-state module Bug 1921094 Change-Id: I3bfa7d52eee5b40a41d80b362e064665081694a3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master/r/1508819 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move mclk related functions to clkThomas Fleury2017-06-30
| | | | | | | | | | | | | | Move mclk related functions be moved to clk structure instead of pmu. We want to keep pmu only for basic pmu interaction and split clk, lpwr etc. Bug 1921094 Change-Id: I32394bc0e6d3657dfbd34dbcf19c9af56c12e194 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master/r/1506586 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mclk switching sequences for .58 OEM VBIOSThomas Fleury2017-06-30
| | | | | | | | | | | | | | | Add mclk switching sequences for VBIOS 8606580012. Bug 1921094 Change-Id: I0e5b0e967c467a40d498ea5c634302f208722922 Reviewed-on: http://git-master/r/1499550 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 3c60b8ded3764a700a9719ae6bf176dcec94a989) Reviewed-on: https://git-master/r/1506585 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: determine memory configuration in halThomas Fleury2017-06-30
| | | | | | | | | | | | | | | | | | | Remove mem_config_idx from platform data, and instead let HAL determine which memory configuration to use. For this purpose, HAL may use PCI device identifiers, VBIOS version and possibly RAMCFG strap register. Bug 1929155 Change-Id: I6633e9e0c79728c8e3740f3f956b53b3abfc667b Reviewed-on: http://git-master/r/1497812 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit b7141ff5441b7ea95f9826eb37ae869f408e1414) Reviewed-on: https://git-master/r/1506584 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: determine memory configuration in halThomas Fleury2017-06-30
| | | | | | | | | | | | | | | | | | | Remove mem_config_idx from platform data, and instead let HAL determine which memory configuration to use. For this purpose, HAL may use PCI device identifiers, VBIOS version and possibly RAMCFG strap register. Bug 1929155 Change-Id: I9fcd67ff407382839ff81470789043fae1c81283 Reviewed-on: http://git-master/r/1497813 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 3f722945213bacfc5f6707059b9baccebd92cef1) Reviewed-on: https://git-master/r/1506583 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add t19x supportRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | - add commit_inst hal ops - add t19x cmds to cmd big union - add t19x vgpu driver and call t19x hal init - get guest channel_base to calculate hw channel id Jira VFND-3796 Change-Id: Ic2431233fd174afc2c84c4794e20552e6e88b1dc Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1474715 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: fixes for no bar1 support caseRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | - add check of is_bar1_supported - move vgpu_init_fifo_setup_hw to hal - assume it's bar1 reg if no "reg-names" in dts Jira VFND-3796 Change-Id: I022a0ed98144bb8f1e7e55f24fcaf928b4a3fe32 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1474716 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add fifo_t19x and channel_baseRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | - add fifo_t19x to fifo_gk20a - add channel_base to fifo_gk20a It'll make kick off code re-usable by vgpu. Jira VFND-3796 Change-Id: I7f7607d3682f2eaad903e1690d83c1d78eba8052 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1510456 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename hw_chid to chidRichard Zhao2017-06-30
| | | | | | | | | | | | | hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1509530 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gr: rename write_preemption_ptrseshendra Gadagottu2017-06-29
| | | | | | | | | | | Change function name write_preemption_ptr to set_preemption_buffer_va to match with what exactly getting done in that function. Change-Id: Ia20c1df865dde01ab2878d3cf10281676ff5000e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1510972 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: post PMU_STATE_STARTED for pmu threadKonsta Holtta2017-06-29
| | | | | | | | | | | | | Make the PMU_STATE_STARTED state change visible to the thread so that the thread quits when it is no longer necessary. Bug 200317814 Change-Id: I2a2d664bd772b5bb19ec096e50c9992fcec9170e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1509968 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use correct log type print in ftraceKonsta Holtta2017-06-29
| | | | | | | | | | | | | Supply the log type argument as text from the table as the log format string specifies for trace_printk. Change-Id: I9e0f2dd8bffeeb0f8cbdba95d9969403d7161474 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1509334 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: depend on gk20a for all configsKonsta Holtta2017-06-29
| | | | | | | | | | | | | | | | Depend on the main GK20A config for all subitems so that they get grouped properly under the top level item in the menuconfig. Also remove an extraneous CONFIG_ to make the trace printk config visible in the menu when its deps are there. Change-Id: I03ee5b8dff9ad02342ab31d0faad9549e8352059 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1509333 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU reset reorgMahantesh Kumbar2017-06-29
| | | | | | | | | | | | | | | | | | | | | | | | - nvgpu_pmu_reset() as pmu reset for all chips & removed gk20a_pmu_reset() & gp106_pmu_reset() along with dependent code. - Created ops to do PMU engine reset & to know the engine reset status - Removed pmu.reset ops & replaced with nvgpu_flcn_reset(pmu->flcn) - Moved sec2 reset to sec2_gp106 from pmu_gp106 & cleaned PMU code part of sec2. JIRA NVGPU-99 Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: functions made non-staticSeema Khowala2017-06-29
| | | | | | | | | | | | | | gr_gp10b_handle_fecs_error and gr_gp10b_set_cilp_preempt_pending made non-static to be reused for t19x Bug 200289491 Change-Id: I8ef7ffab1209abc7f7d7d05cbbdf8ce4365613c5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1505954 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add GPU_LIT_SM_PRI_STRIDE litter defineSeema Khowala2017-06-29
| | | | | | | | | | | | | Required to support multiple SM JIRA GPUT19X-75 Change-Id: If4397f29bfc4f31da13187182f0ae3c7423d0432 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1490096 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: Support multiple SM for t19xSeema Khowala2017-06-29
| | | | | | | | | | | | | | | | | -Add sm input param for handle_sm_exception and pre_process_sm_exception for gr ops/functions. -Add functions to calculate gpc and tpc reg offsets. -Add function to find SMs which raised SM exception. JIRA GPUT19X-75 Change-Id: I257e7342ddabadb1556c9551c50a54d34b0f9d1e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1476108 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: add GPU_LIT_NUM_SM_PER_TPC litter valueSeema Khowala2017-06-29
| | | | | | | | | | | | | Required for multiple SM support in t19x JIRA GPUT19X-75 Change-Id: I14e19700849faf5180813e82179707a78eb977a5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1510358 GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Set default devfreq polling ratePeter Boonstoppel2017-06-29
| | | | | | | | | | | | | Sets default polling rate for GPU podgov governor to 25ms. Jira NVGPU-20 Change-Id: I994f3aab772b41c238f6755e0bd22ed3d4b27cf4 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: https://git-master/r/1473141 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove gk20a_scale_notify_busy/idle() hooksPeter Boonstoppel2017-06-29
| | | | | | | | | | | | | | | | Remove dependency for nvgpu to invoke devfreq govenor on every gk20a_busy/idle() call. This dependency was originally necessary to track GPU load (busy vs idle) in software. However, since we currently read the load GPU from HW/PMU there is no need to invoke the devfreq governor in this path. Instead it can use timer-based polling. Jira NVGPU-20 Change-Id: Id09f89a8a562ed49164a2e06dcbb901e4a46e7d5 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: https://git-master/r/1473140 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: perfbuffer supportPeter Daifuku2017-06-27
| | | | | | | | | | | | | | | | | Add vgpu support for ModeE perfbuffers - VM allocation is handled by the kernel, with final mapping handled by the RM server - Enabling/disabling the perfbuffer is handled by the RM server Bug 1880196 JIRA EVLR-1074 Change-Id: Ifbeb5ede6b07e2e112b930c602c22b66a58ac920 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master/r/1506747 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove fmodel GMMU allocationAlex Waterman2017-06-27
| | | | | | | | | | | | | | | | | Remove the special cases for fmodel in the GMMU allocation code. There is no reason to treat fmodel any different than regular DMA memory. If there is no IOMMU the DMA api will handle that perfectly acceptably. JIRA NVGPU-30 Change-Id: Icceb832735a98b601b9f41064dd73a6edee29002 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1507562 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorganize ltc HAL initializationSunny He2017-06-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ltc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1110e301e57b502cf7f97e6739424cb33cc52a69 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1507564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove ltc_common.cSunny He2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | Remove ltc_common.c and integrate the included functions into device specific ltc_gXXXX.c files. Merge non-device reg definition dependent ltc functions into ltc_gk20a.c/h. Prior to this patch, ltc_common.c was being directly included into the device specific ltc source files as a workaround to allow different devices to share the same code but still include in different hw reg definitions. Given that this approach was not adopted for other systems, this code has been separated out for readability and consistency. Jira NVGPU-74 Change-Id: I4eea301927418532cc150b029535f165928cab89 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1507502 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_copy_to_dmem()Mahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | - replace usage of pmu_copy_to_dmem() with nvgpu_flcn_copy_to_dmem() - delete nvgpu_flcn_copy_to_dmem() JIRA NVGPU-99 Change-Id: I9bb5837556e144521b181f9e15731beee08b435a Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506577 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon copy to DMEM supportMahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | | - Added falcon interface/HAL copy to DMEM method. JIRA NVGPU-99 Change-Id: I783f8046e96d9e47091afb943697256c289ebab6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506576 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_copy_from_dmem()Mahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | - replace usage of pmu_copy_from_dmem() with nvgpu_flcn_copy_from_dmem() - delete nvgpu_flcn_copy_from_dmem() JIRA NVGPU-99 Change-Id: If0919187078f95a165d6a152f180549ac121beaa Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon copy from DMEMMahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | | | | - Added interface/HAL method for falcon to support copy from dmem - Method to read dmem size - Method to check error on input parameters JIRA NVGPU-99 Change-Id: Id27b2b7f4f338196fc3b187555718543445d35bd Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506525 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move sysfs dependencies from HAL to LinuxTerje Bergstrom2017-06-27
| | | | | | | | | | | | | Move sysfs dependencies from gk20a/ and gp10b/ to common/linux. At the same time the gk20a and gp10b variants are merged into one. JIRA NVGPU-48 Change-Id: I212be8f1beb8d20a57de04a57513e8fa0e2e83b4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1466055 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 00:41:38 -0400