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* gpu: nvgpu: update gr_gv11b_get_netlist_name methodMahantesh Kumbar2016-06-21
| | | | | | | | | | | update gr_gv11b_get_netlist_name method as per ops get_netlist_name declaration Change-Id: Ide79d999564f489a80cff748ff61e42aabd5662a Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1166905 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove hard coded runlist_id mappingLakshmanan M2016-06-13
| | | | | | | | | | | | | | | From this patch onwards, runlist_id is a member of struct channel_gk20a. So removed hard coded runlist_id mapping logic. JIRA DNVGPU-25 Change-Id: Ia02feffdc057b0dceab9721423feeed1cc7a1c12 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1161779 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-06-07
| | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Volta GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156023 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix patch write error check in update_ctxsw_preemption_modeKonsta Holtta2016-06-06
| | | | | | | | | | | | Don't attempt to access memory if the patch context can't be mapped, but print an error message instead. Change-Id: I2d0ec22378ace0ef826f5a84a9ce4d35466f7832 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157281 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: t19x: config: Add t19x config fileSeshendra Gadagottu2016-06-02
| | | | | | | | | | | | | Add t19x config file to enable config for TEGRA_T19x_GPU. Bug 1757988 Change-Id: I0d1afd3f9a1d8f3b08963a07090583a2bb46dd69 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1157320 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add device_info_data supportLakshmanan M2016-05-27
| | | | | | | | | | | | | | | Added device_info_data H/W register in Volta GPU hw_top_gv11b.h header. JIRA DNVGPU-26 Change-Id: I954a02df86ac7514c50ff72e71ea9b53e60c3354 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151618 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gv11b: change kernel pathPritesh Raithatha2016-05-25
| | | | | | | | | | | | | | All kernel versions are getting moved inside $TOP/kernel folder. Changing kernel paths accordingly. Bug 200190733 Change-Id: I7dc6d1768151977fc60bacae34c2f8d839216351 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/1143388 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gv11b: add PRAMIN support for mem accessorsKonsta Holtta2016-05-24
| | | | | | | | | | | JIRA DNVGPU-23 Change-Id: I47c8d89e65b9bdb30b1399728d51bba77c3929ae Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1148389 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Use gp10b GR floorsweepingTerje Bergstrom2016-05-16
| | | | | | | | Use gp10b version of GR floorsweeping function. Change-Id: I5715672b5f94b779165f44c78aec14a2836928e7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1144905
* gpu: nvgpu: Add support for multiple PBDMAsLakshmanan M2016-05-13
| | | | | | | | | | | | | | | | Added support for multiple PBDMAs handling during fifo_pbdma_isr and gk20a_init_fifo_reset_enable_hw use case. JIRA DNVGPU-26 Change-Id: I2e70c6f9a724899aaef179ae015149d7127f227b Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1145603 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: refactor gk20a_mem_{wr,rd} for vidmemKonsta Holtta2016-05-13
| | | | | | | | | | | | | | | | | To support vidmem, pass g and mem_desc to the buffer memory accessor functions. This allows the functions to select the memory access method based on the buffer aperture instead of using the cpu pointer directly (like until now). The selection and aperture support will be in another patch; this patch only refactors these accessors, but keeps the underlying functionality as-is. JIRA DNVGPU-23 Change-Id: Ie2cc17c4a0315d03a66e92fb635c217840d5399e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1128863 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: use preemption modes defined in nvgpu-t18x.hDeepak Nibade2016-05-09
| | | | | | | | | | | | | | | | | | | | Below definitions of preemption modes are deleted: NVGPU_GR_PREEMPTION_MODE_GFXP NVGPU_GR_PREEMPTION_MODE_CILP Use new definitions defined in nvgpu-t18x.h NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP NVGPU_COMPUTE_PREEMPTION_MODE_CILP Bug 1646259 Change-Id: Ieff51e41ef34eb61357f95778c400c8a3fa330c8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1133597 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set soc memory aperture typeSeshendra Gadagottu2016-04-23
| | | | | | | | | | | | | | For gv11b, set platform data for soc memory aperture type to sysmem instead of vidmem. Bug 1749338 Change-Id: I6632e79e3ca68c437e5b04f6865f8f0b6f2943ce Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1129169 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gv11b: sysmem aperture for soc memorySeshendra Gadagottu2016-04-19
| | | | | | | | | | | | | In gv11b, soc memory needs to be accessed as sysmem instead of videmem. Bug 1749338 Change-Id: I325c107958229cf717b0b0f18dd123597d1d7567 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1128377 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gv11b: fix sparse warningsSeshendra Gadagottu2016-04-19
| | | | | | | | | | | | | | | | | | | Fixed following sparse warnings: drivers/gpu/nvgpu/gv11b/gv11b.c:21:5: warning: symbol 'gv11b_init_gpu_characteristics' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/hal_gv11b.c:36:5: warning: symbol 'gv11b_init_hal' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/gr_gv11b.c:766:5: warning: symbol 'gr_gv11b_alloc_buffer' was not declared. Should it be static? Bug 200088648 Change-Id: I327f9d69bf1853727d74d2c125cfab54c2f0e5b0 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1128299 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
| | | | | | | | | | | | | | Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: header update related to smSeshendra Gadagottu2016-04-16
| | | | | | | | | | | | | Updated priv registers related to sm re-organization Bug 1735757 Change-Id: I5656f87c17fb3d95a162f06d96d29dab25d648f8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126960 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: added initial source codeSeshendra Gadagottu2016-04-13
| | | | | | | | | | Bug 1735757 Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1122123 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gv11b: add hw headers for gv11bSeshendra Gadagottu2016-04-13
Add initial versions of header for gv11b Bug 1735757 Change-Id: I76f85bbe98c1fa13c11d8ee1b2889703f62c6f67 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1121486 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
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