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* gpu: nvgpu: Cast det_out to u64 for 64-bit calcTerje Bergstrom2017-01-04
| | | | | | | | | | | voltage_get() defines det_out as u32. That variable is used to calculate a 64-bit result, so cast det_out to u64. Change-Id: I054ec299a4c7961cb38dd5ac0cbf0ac173b09efb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267692 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
* gpu: nvgpu: fix out-of-bound access on gr->gpc_tpc_countDeepak Nibade2017-01-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix slab-out-of-bounds issue reported by KASAN [ 29.922710] BUG: KASAN: slab-out-of-bounds in gr_gk20a_init_fs_state+0x1bc/0x898 at addr ffffffc1a0988c04 ... [ 29.961820] INFO: Allocated in gr_gk20a_init_gr_config+0x380/0x1b20 age=374 cpu=5 pid=1 ... Out-of-bound access from [ 30.241943] [<ffffffc0007d2674>] gr_gk20a_init_fs_state+0x1bc/0x898 [ 30.248205] [<ffffffc000839a2c>] gr_gm20b_init_fs_state+0x4c/0x5c8 [ 30.254381] [<ffffffc000871670>] gr_gp10b_init_fs_state+0x160/0x3a8 [ 30.260643] [<ffffffc0007d70ec>] gk20a_init_gr_setup_hw+0x974/0x1530 [ 30.266991] [<ffffffc0007eac6c>] gk20a_init_gr_support+0x14c/0xeb0 [ 30.273164] [<ffffffc00079d9c8>] gk20a_pm_finalize_poweron+0x738/0xd10 [ 30.279684] [<ffffffc00079dfd0>] gk20a_pm_runtime_resume+0x30/0x58 Fix this by using a separate API gr_gk20a_get_tpc_count() which returns tpc count for a gpc and returns 0 if gpc index is greater than available gpcs Bug 200257557 Change-Id: I78856ca93c0381cb4bcef7a56a5210fa269cf3ac Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1277692 GVS: Gerrit_Virtual_Submit Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: compile local t18x codeDeepak Nibade2016-12-28
| | | | | | | | | | | | | | | | | Compile local t18x code from nvgpu repo (in case CONFIG_ARCH_TEGRA_18x_SOC config is set) instead of compiling from $(srctree)/../nvgpu-t18x Remove Makefile.nvgpu-t18x since this Makefile is not needed now Bug 200266498 Change-Id: Ib8ef39be7e948debe0ff895c904a6c370a5711a6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1277119 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: skip setting preemption modes if already setDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | In gr_gp10b_set_preemption_mode(), skip setting anything if both graphics and compute preemption modes are already set Bug 200263471 Change-Id: I2788464750835da8f6396c6c1ca8356a63758c80 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1275465 GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: PG statistics updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | - PG statistics read support for multiple engines JIRA DNVGPU-71 Change-Id: I2dc3aad243300d21dc3d20a54a5e4736977e071b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1250507 (cherry picked from commit 985cb3be1d6d990bc6651e417d9e6ba9bfe306e0) Reviewed-on: http://git-master/r/1270991 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: MSCG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: RPPG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - Added rppg module to init GR/MS-RPPG. mscg is dependent on gr-rppg & without gr-rppg engage mscg does not engage. - Update pg engines HAL to return supported pg engines & its sub features JIRA DNVGPU-71 Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247486 (cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9) Reviewed-on: http://git-master/r/1270762 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: no support for sparse mappingAparna Das2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Currently sparse mapping is not supported for gp10b in virtualized environment. Modify gpu characteristics to reflect non-implementation of this functionality. Also fix return value in vgpu_gp10b_locked_gmmu_map() on error condition. Bug 200243373 Change-Id: Ia367b923b87738a5cad0617cdb074f5a24fb1c81 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: http://git-master/r/1269710 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Sachit Kadle <skadle@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: fix CLFC arbiter vf table updateDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | (1) Adding additional debug in case of VF update failure (2) The length of the tables must be re-initialized prior to requesting the vf table update JIRA: DNVGPU-193 Change-Id: Id5a369359bc5f52ee58da539bfc3ec1ec7887de1 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1252061 (cherry picked from commit dfb6fec02f8e3ff6a22bbea000347923b0306018) Reviewed-on: http://git-master/r/1274547 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: arb: fix rounding in effective clocksDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | Current code cast casting the frequency to 16 bit before division, giving out incorrect data JIRA DNVGPU-164 Change-Id: I4eb1fa73fb9e8963f550d3d853db39b49b990fa4 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1251663 (cherry picked from commit c0d91a054f8278af9a2383bb3f837465779132a9) Reviewed-on: http://git-master/r/1274546 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cap minimum gpc clocks to HW limitsDavid Nieto2016-12-27
| | | | | | | | | | | | | | | JIRA: DNVGPU-180 Change-Id: I1928e77cea4ac87bf2ba2b6b7b2f2942dfb97de9 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1251493 (cherry picked from commit 7b8a105652a3169d9ec0cb7ce52c3b92e42ca310) Reviewed-on: http://git-master/r/1274545 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use common API to write TPC fusesDeepak Nibade2016-12-27
| | | | | | | | | | | | | Use common fuse write API tegra_fuse_control_write which should work on all kernel versions Bug 200262155 Change-Id: I29e8514e9660549ecf94711287ec4bbf4c897a86 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1270169 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow upgrading preemption modesDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | We currently do not allow resetting preemption modes once set Relax this check to allow upgrading preemption modes. Downgrading of preemption modes is still not allowed Bug 200263471 Change-Id: Ie2dae910028929090899a661f4b8b9dd4d6d7ee7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1269472 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: call set volt always during vf switchVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | bug 1845211 clfc is reset during vf switch. it resets delta values stored in pmu structure. if voltage has not changed, delta calculation happens on top of corrected voltage causing volt to keep on increasing in cases where voltage does not change during a vf switch. Change-Id: I9d1a58b6b7652f22c3a7304162bb8ca6f7d1da6f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1266632 (cherry picked from commit 74e2e97d4d149d3eac65b5f65b358b977fba463e) Reviewed-on: http://git-master/r/1273911 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: actions before and after vf changeVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | JIRA DNVGPU-175 1)Add functions to be called before and after vf change 2)Capture noise unaware vmin value and pass it as param to vf change functions 3)Before VF change disable CLFC and update noise unware vmin 4)After VF change is done enable CLFC Change-Id: I4bb59fbe96ec5a792e8930db3ab4a39ec74c9a71 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248211 (cherry picked from commit cf07892204d7ce11a0d27ecbc1f5826fbabbde61) Reviewed-on: http://git-master/r/1270950 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: keep sec2 idleMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | sec2 falcon reset after secure boot complete to keep sec2 idle issue: ELPG does not engage if PG engine is dependent on sec2 idleness JIRA DNVGPU-71 Change-Id: If264c610dae857ae9b9f9bc77c59f24f239ce1ce Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247290 (cherry-picked from commit de2337de1211e4167993982e50237fe1115053a1) Reviewed-on: http://git-master/r/1267260 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: pstate interface updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | lpwr_entry_idx member is required to map pstate with lwpr tables JIRA DNVGPU-71 Change-Id: I4cad54c61dec7ad7e3c1a60178938d0eeaf65e24 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247303 (cherry-picked from commit b1f6e0036922d2104b3d08548219e72a38f2e231) Reviewed-on: http://git-master/r/1267403 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update pg engine init/list/features HALMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - Updated gp10b_pg_gr_init() to post init param based on PG engine parameter - Assigned pg engine list/features HAL to respective functions/NULL JIRA DNVGPU-71 Change-Id: I7d059796746694b22800c6ae0327cbc90331e929 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247407 (cherry-picked from commit aee4e565ca2b475c0680674e4e6345b3b30cc502) Reviewed-on: http://git-master/r/1269321 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix fll regime checkVijayakumar2016-12-27
| | | | | | | | | | | | | | For target clocks >= FFR cutoff clock use FR, else use FFR. JIRA DNVGPU-180 Change-Id: Iefed871d2acf1552230b066c32e1b3f69d96079e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1249041 (cherry picked from commit edcb12d8784c62aa857dcab2e27d4e45033fbf11) Reviewed-on: http://git-master/r/1270883 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set p state floor for sys and xbar clkVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | bug 200254784 If XBAR and SYS clocks for a given GPC clock point is lower than minimum value mentioned in P state set the floor to minimum value mentioned in p state. it was set to value based ratio of a GPC clk value in VF table which can give value higher than one mentioned in p state. Ignore ratio and just set to p state value Change-Id: I9f7cd1d5842d057aff6d8243a31ab503ce35a8ca Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1257251 Reviewed-by: Automatic_Commit_Validation_User (cherry picked from commit 5798680286967ff999f674bedd4fc0411615f914) Reviewed-on: http://git-master/r/1270949 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add clock freq controller supportVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-170 1) Add clock frequency controller VBIOS structure definitions 2) Parse VBIOS tables and build boardobj structures for clock frequency controller. 3) send clock frequency controller data structures to PMU 4) implement public function to send load/unload command to pmu to enable/disable clock frequency controller support Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07) Reviewed-on: http://git-master/r/1270897 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fn to send noise-unaware vmin to pmuVijayakumar2016-12-27
| | | | | | | | | | | | | | | JIRA DNVGPU-184 implement a function which takes noise unaware vmin for logic and sram rails as input and sends them to pmu via RPC Change-Id: Ic0d72daf99870477d4dbd17e1c609dd0c39f8197 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248210 (cherry picked from commit 2ad833c1edf65ada6c72b56ecd3551e7c4d396f6) Reviewed-on: http://git-master/r/1270885 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: p-state bound arbiterDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modification of the ARBITER clocks to be P-State aware Up to now the arbiter just considered the whole range of the GPC and MCLK domains, which could end up on illegal combinations of MCLK, GPC2CLK, and set the SYSCLK and XBARCLK domains below their minimum VCO The following has been implemented: (1) Modified VF tables to add which PState are supported on each point. (2) Return and store the current PState on the arbiter state. (3) Modified logic to prevent illegal combinations of MCLK and GPC2CLK. (4) Modified logic to prevent setting VF points for XBAR and SYS domains below VCO limits. (5) Modified voltage calculation to account for increased values of XBAR and SYS on some VF points. (6) Modified arbiter clock target logic to prevent an application that has not requested a particular VF point to set target to default targets. (7) Remove unnecesary mutexes from critical path JIRA DNVGPU-182 JIRA DNVGPU-183 Change-Id: I3d1c30903278f848681b8da833a867835acc99bb Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1247937 (cherry picked from commit b8bcc07eb3b5b70ec1ee19ace237df99d6170138) Reviewed-on: http://git-master/r/1268063 Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle vf curve change due to tempVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-129 1)send 150'c as default temperature to PMU so that PMU will start reading temperature from sensor to evaluate VFE equations 2)Send GP106's temp min and max range for GPU sensor so that PMU will read right temperature 3)PMU will send event whenever temperature goes above +ve hysteresis or goes below -ve hysteresis. Call the Arbiter's VF re-evaluation function in the event handler. Change-Id: Iaebc0655f60e17998f0864824095f4fc8bba5b62 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1245392 (cherry picked from commit 7e59d0faa8cee6aace5524c724001e88248b2da7) Reviewed-on: http://git-master/r/1268062 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: prevent hang on failing arbiter initDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | The current code can lead to application hang when opening device on first time if the arbiter fails to set the clocks Also it solves a buffer overrun condition in case the requested frequency is above the maximum range of the VF curve bug 1835042 Change-Id: I385401ea27d5cc4bfa41b7ca2eb3a1db53138418 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1245911 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1268061 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: resolve signed/unsigned mismatchDavid Nieto2016-12-27
| | | | | | | | | | | JIRA DNVGPU-143 Change-Id: I0536aff4f994efc3dbd2db949068f8e1345ece9c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1268107 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: get voltage, current, power and temperatureThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | Add ioctls to retrieve voltage, current, power and temperature. Add flags in GPU characteristics to indicate if feature is supported. Jira DNVGPU-166 Change-Id: Ifaafe2efdb6b09d7b28215b641814f28e894151e Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1241861 Tested-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1267122
* gpu: nvgpu: make clock arbiter locklessDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Modification of the arbiter to remove all locking from the arbiter callback and move the callbacks out of the global queue Adding modification to call for updated values of vf table from arbiter init function and on vf table update JIRA: DNVGPU-170 Change-Id: I7a7d34c0590522901e06356c06fd8114ebf10f37 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1243212 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1268009 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gpu: read effective frequence from counterDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | (1) modified counters debug code to export to the driver (2) modified arbiter to read from those functions (3) modified counter for higher accuracy on MHz range JIRA DNVGPU-164 Change-Id: I2bbf7c9be4dc59718d1d91c53028a39020b5aea5 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239467 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1268008
* nvgpu: gpu: Use pstates for MCLK rangeDavid Nieto2016-12-27
| | | | | | | | | | | | | JIRA DNVGPU-168 Change-Id: I7ac05dca745b22b411fc0aa797969b97536dd2e6 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239466 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1267121 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: arbiter for vf switch managementDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-143 The arbiter is charged with selecting the proper frequencies when multiple applications submit simultaneously clock change requests On the current implementation, the arbiter guarantees that the selected frequency will be always higher or equal to the request, as long as the request is in range. The current code is not yet realtime friendly, as requests are not pre-allocated. Summary of changes: (1) pstate/vf switch no longer selects boot frequency (2) changed mclk code change to accept input freq (3) added arbiter (4) now a single session can submit concurrent requests the last request is the one that applies for that session (5) modified locking mechanism to reduce lock contention (6) Added callback to notify the arbiter that the VF table has changed and is no longer valid (PMU/Thermals must call this when VF table is invalid) (7) changed internal API to work with MHz (8) added debugfs for stats Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239461 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267120 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Use bootstrap base for WPR addressTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | | | Use the bootstrap base address for calculating the address of WPR. The bootstrap base is dynamic and depends on amount of memory, so we should not hard code any address. Bug 200244445 Change-Id: Ia700d24c8d572a25946f7b1847faec72c40c6796 Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1242252 Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/1267125 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove FB ISO CG from init listTerje Bergstrom2016-12-27
| | | | | | | | | | | Remove FB ISO clock gating register from initializion list. The register does not exist on GPUs without own memory. Change-Id: I86a8c8050baad88a99029771511363f2a1d44341 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1265297 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: fix va leak when call gk20a_vm_free_vaRichard Zhao2016-12-27
| | | | | | | | | | | | | | | | page size index needs to be set explicitly when call gk20a_vm_free_va. Bug 200255799 JIRA VFND-3033 Change-Id: Ic23ea68905ea423173d1859fd100e7b2c82a1bcc Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1262590 (cherry picked from commit 918aea147b395f7337db348d2616fb4b195dc53a) Reviewed-on: http://git-master/r/1263400 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: clk requests completion and event fdsThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | Install one completion fd per SET request. Notifications on dedicated event fd. Changed frequencies unit to Hz from MHz. Remove sequence numbers from dummy arbiter. Added effective clock type (query frequency from counters). Jira DNVGPU-125 Change-Id: Id5445c6ae1d6bf06f7f59c82ff6c5d3b34e26483 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1230239 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit d17083f4ceb69725c661678607a3e43148d38560) Reviewed-on: http://git-master/r/1243106
* gpu: nvgpu: clk arbiter skeletonThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | | Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove debugger check for cilp completion eventDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | We can trigger CILP only if SM debug mode is on. So in fecs interrupt handler, we could have graphics context running for which SM debug mode is disabled. And in that case we skip posting of cilp completion events to UMD. But since CILP event was anyways triggered, we need to post events to UMD irrespective of SM debug mode is enabled at that point or not Hence remove check gk20a_gr_sm_debugger_attached() for posting events to UMD Bug 200243092 Change-Id: I54ad205be11ec6d5034d524bfbb28f8a1fa72993 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1263591 (cherry picked from commit e6259e2d0d5a4bb5929e70e03e154f8b82ae3600) Reviewed-on: http://git-master/r/1264780 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: hardcode gp10b fbpa valuesPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | | gp10b does not have an fbpa unit, although the hw header files claim it does. Hardcode all fbpa values to 0. Bug 200249125 Change-Id: I6ed63b3231d7af8e31ccf5047d56bdb85f05a9d9 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1256422 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: correct adc slope ofset sign bitVijayakumar2016-12-27
| | | | | | | | | | | | | | bug 1838549 Change-Id: I40457aebd49a02d0dd54d6dc9c965f89613ee21f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1251371 (cherry picked from commit 2c80f36830baf48bab043d7f1ebbcbe7759789c4) Reviewed-on: http://git-master/r/1251452 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu: gp10x: use chip specific init_inst_blockseshendra Gadagottu2016-12-27
| | | | | | | | | | JIRA GV11B-21 Change-Id: I3e2cb2384b6a26ba339a79d38c91dd47480fe6a6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254876 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: clear ce isr before wakeupSachit Kadle2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | In gp10b_ce_nonstall_isr(), we trigger a semaphore wakeup. Currently, we clear the interrupt status register after the wakeup is complete. There is potential for an interrupt to come in while the wake-up operation is in progress, and it is possible that: 1) We miss processing the interrupt in that ISR iteration AND 2) We clear the interrupt status register anyways This change clears the status register before triggering wakeup, so the interrupt will properly re-fire. Bug 200244458 Change-Id: Ia3338252eeea4eb60d11c0e241279989a46dac04 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1253107 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add FBPA base addressesPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | Add FBPA base addresses Bug 200249125 Change-Id: I235fa12a00ef2c5b2f0415bb18755523e8a2754b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1247802 (cherry picked from commit d2c73ee989d3abeae305ff68ab355772c5e0af5a) Reviewed-on: http://git-master/r/1252163 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Program RX bias currentTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Hard code RX bias current to 0x2. Bug 1833830 Change-Id: I1107bad52de7b38d311bc5795739777a4bb4239a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1253656 (cherry picked from commit 7e853b0c62043cc53847e3535e05886d574dc779) Reviewed-on: http://git-master/r/1255724 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: Expose the boot max freqTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | Expose the currently hard coded boot frequency, which is at the same time the max frequency. We use it for filling in GPU characteristics. Bug 200251486 Change-Id: I3c0abb7a385a83f61b93ddfa857b982c850853e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252906 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com> Tested-by: Shreshtha Sahu <ssahu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gp10x: updated API for get_litter_valueseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | get_litter_value API is updated to use int instead of enum type. JIRA GV11B-21 Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1252212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix signed comparison bugsTerje Bergstrom2016-12-27
| | | | | | | | | | | | Fix small problems related to signed versus unsigned comparisons throughout the driver. Bump up the warning level to prevent such problems from occuring in future. Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252069 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: no emc change when railgatedJuha Lainema2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | GPU frequencies can be set by powerhal when GPU is railgated, and before this change that would cause EMC floors to remain set until GPU is unrailgated. After this change, EMC floors are not requested by the GPU client when the GPU is railgated. It is ok to ignore the requests, as the GPU client maxes the floor when powering up. Bug 1807560 Change-Id: I9a0d58b0288edbd03b2edf09580ecabd9b74f0c2 Signed-off-by: Juha Lainema <jlainema@nvidia.com> Reviewed-on: http://git-master/r/1216233 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-by: Cyril Raju <craju@nvidia.com> Tested-by: Cyril Raju <craju@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Add regops whitelistsPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | Add regops whitelists for gp106. The whitelist is generated, and is the same for context switched and global registers. Bug 200239422 Change-Id: Ib6689956c191c8f346da8cc5c7e3791f105db4eb Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1243253 (cherry picked from commit 1bdc23c9f9aac7ba91a50b83397925237851f8db) Reviewed-on: http://git-master/r/1247645 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Free pmu_sig if init PMU failsTerje Bergstrom2016-12-27
| | | | | | | | | | | If gk20a_init_pmu() fails, go to the error path that frees pmu_sig. Change-Id: I2f6fcb86570aba54ab45aec14ee6f341e3faebd5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249971 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: Return correct GPC base addressesTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Due to missing break statements, GPC base and GPC shared base were overwritten by values in following select cases. Change-Id: Iba50d8256c1cf07ff8e631e2fcf22a68cdc992e0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249970 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 15:20:28 -0500