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* gpu: nvgpu: fix arbiter teardown on PCIDavid Nieto2017-03-20
| | | | | | | | | | | | | | | | The driver is not properly tearing down the arbiter on the PCI driver unload. This change makes sure that the workqueues are drained before tearing down the driver bug 200277762 JIRA: EVLR-1023 Change-Id: If98fd00e27949ba1569dd26e2af02b75897231a7 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1320147 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add fifo ops for intr_0_error_maskSeema Khowala2017-03-20
| | | | | | | | | | This change is required to support t19x mmu fault Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313482 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: del channel job before fence is closedPeter Daifuku2017-03-17
| | | | | | | | | | | | | | | | | | | In gk20a_channel_clean_up_jobs, move removal of job from channel's job list to before fences are cleaned up; this will prevent gk20a_channel_abort from asynchronously trying to dereference an already freed job. Bug 1844305 JIRA EVLR-849 Change-Id: I1ba05237aa74be1350007630bfa5eba9988f859a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> (cherry picked from commit 2a9ce58b1b318b95ecfcdf78462f918d090eab99) Reviewed-on: http://git-master/r/1319026 (cherry picked from commit 990f070b0a363159ce1b21f936b7512f469018ca) Reviewed-on: http://git-master/r/1321624 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move all FB programming to FB HALTerje Bergstrom2017-03-17
| | | | | | | | | | | | | | | | | | | | | Move all programming of FB to fb_*.c files, and remove the inclusion of FB hardware headers from other files. TLB invalidate function took previously a pointer to VM, but the new API takes only a PDB mem_desc, because FB does not need to know about higher level VM. GPC MMU is programmed from the same function as FB MMU, so added dependency to GR hardware header to FB. GP106 ACR was also triggering a VPR fetch, but that's not applicable to dGPU, so removed that call. Change-Id: I4eb69377ac3745da205907626cf60948b7c5392a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1321516 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use $(srctree) properly in makefileKonsta Holtta2017-03-17
| | | | | | | | | | | | Fix include paths for kernel 4.9 and clean up some unnecessary ones. Bug 1853519 Change-Id: Ic9dc865654e593f4ed92e88863bca87d850aab3c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321226 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: don't read missing gpc_tpc_count in dumpKonsta Holtta2017-03-17
| | | | | | | | | | | | | The gp10b gr status dump can get printed so early that this array is null, so don't access it in that case. Bug 1853519 Change-Id: I7474a7f7c50f89aea4ef8e9b16cb1644355e415b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321119 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove use of PM runtime in VPR fetchTerje Bergstrom2017-03-17
| | | | | | | | | | | | | VPR fetch is called only from code which already has GPU powered on. Skip calling PM runtime. Change-Id: I8f90f1afab150e81ad16a157cfe063848a3e4fc1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1320732 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Implement get_rate/set_rate as GPU opTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | | | | | | Move clock APIs from gk20a_platform to gpu_ops. At the same time allow use of internal get_rate/set_rate for querying both GPCCLK and PWRCLK on iGPU. At the same time we can replace calls to clk framework with the new HAL and drop direct dependency to clk framework. gp10b ops were replaced as a whole at HAL initialization. That replaces anything set in platform probe stage, so reduce that to touch only clock gating regs. Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300113 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move platform files to Tegra LinuxTerje Bergstrom2017-03-16
| | | | | | | | | | | | Platform files are used for adding code to probe for Tegra Linux platform. Move the files to Tegra Linux directory to make this clear. Change-Id: Ida66af835688325f095260c618dad90395851267 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300112 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Rename clk->get_rate to measure_freqTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | get_rate is already used for call-back that queries the last set clock rate. This instance of get_rate actually measures the frequency so renaming it to measure_freq. At the same time modify to use hertz instead of megahertz. We use fractional megahertz already in GPU. Change-Id: I387473d6a6cbf3bb9b9e5a909677a1a725403c32 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300111 Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Fix timers failure addressAlex Waterman2017-03-16
| | | | | | | | | | | | | | | | | | In the timers code a macro was using __builtin_return_address(0) when it should have been using _THIS_IP_. __builtin_return_address(0) will cause the timers code to print the return address of the function that calls the timers code. This isn't actually useful, of course. A user actually cares about where the timers code call comes from which is easily obtained with _THIS_IP_. Bug 1799159 Change-Id: Iac16bc79e89e4cd18133db3d20f5a50d4d5e8f31 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1320839 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cancel vidmem worker only if supportedKonsta Holtta2017-03-16
| | | | | | | | | | | | | | | | Cancel the vidmem.clear_mem_worker during suspend only if vidmem is enabled via kernel config. Otherwise it's not initialized. Bug 1853519 Change-Id: If88c756ae14f348eddda01218fa218480217388c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321118 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: avoid double-free of incr cmdKonsta Holtta2017-03-16
| | | | | | | | | | | | | | | | The call site (gk20a_submit_prepare_syncs) owns the incr_cmd buffer passed to __gk20a_channel_semaphore_incr. Delete the free in the error path of the latter case to avoid freeing the same buffer twice. Bug 1853519 Change-Id: I9b90ce7ebb17ac63992938c7f9fe90bbd139f85f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321117 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use GPU's own fuse registersTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | | | Read fuse values from GPU's own fuse registers instead of Tegra fuse registers whenever possible. This reduces the number of dependencies to Linux fuse code. Some fuses do not have a corresponding register in GPU, so they're left as is. Change-Id: Id9f2f4da897f3e20b20c300a67f705e3fa5ba35a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1318278 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: vgpu: force gpu preepmtion policyAparna Das2017-03-14
| | | | | | | | | | | | | | | | | | Query the RM server to retrieve gpu preemption policy of guest based on pct configuration. If guest is not allowed to request wfi preemption mode then set context with either gfxp or cta preemption mode only. Jira VFND-3079 Jira VFND-3081 Change-Id: I60cbf121d6f0e2373568cf40b3dfdb4df76fe02d Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: http://git-master/r/1280903 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Sachit Kadle <skadle@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: gp10b: fix stall interrupt enablementSeema Khowala2017-03-14
| | | | | | | | | | | Currently priv, pbus and ltc interrupts are enabled as non-stall but being handled in stall isr. Fix is to configure them as stall interrupt. Change-Id: I78a0ad3eb4207dcd70da63098234ed6139f0664a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1320031 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: channel_from_inst_ptr renamed and made non staticSeema Khowala2017-03-14
| | | | | | | | | | required to support t19x mmu fault Change-Id: Ibe621d924717696a359d7e2065beb6501a9f9b5e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1315928 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove unused function gk20a_get_phys_from_iovaTerje Bergstrom2017-03-14
| | | | | | | | | | | | Remove unused function gk20a_get_phys_from_iova. At the same time remove the #include for iommu.h, which was only needed by this function. Change-Id: Ia858b0ad5fe7e423d650aa9f82e430f419f2a492 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1319070 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not use pm_runtime calls directlyTerje Bergstrom2017-03-14
| | | | | | | | | | | | mm_gk20a.c had direct calls to pm_runtime_put_noidle(). Replace them with calls to wrapper gk20a_idle_nosuspend() to prevent unnecessary dependencies to Linux. Change-Id: Iaf8b9255750be2f3e1aa39587c1a4a3cbeacc67f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1319069 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not query SEC2 freq from CCFTerje Bergstrom2017-03-14
| | | | | | | | | | | | | | | | | | | dGPU's SEC2 is passed frequency, which is queried with clk_get_rate(). dGPU clocks are not represented in CCF, so the query always returned an error. The value is ignored, so this went unnoticed. Replace the call to clk_get_rate() by just hard coding 0 as the clock rate. Change-Id: I86fec3726d2b6683cdadd86cab1672f3b199378f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1319068 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* Revert "gpu: nvgpu: change stall intr handling order"Rajkumar Kasirajan2017-03-14
| | | | | | | | | | | | | This reverts commit 35f0cf0efefe4a64ee25a5b118338b15e552dcb0 as it caused lp0 suspend/resume failure. Bug 1886110 Change-Id: Ib62207650344180361b6529f716f77b84528cd56 Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-on: http://git-master/r/1317986 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init for channel/TSGDeepak Nibade2017-03-14
| | | | | | | | | | | | | | - check return value of nvgpu_mutex_init for all the mutexes of a channel and TSG - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: Iba3a5f8bc2261ec684b300dd4237ab7d22fa3630 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317139 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init for semaphoresDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init for semaphores - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I5404dbd29e3fce29f1a445eb2e6ce8e1d1b616c4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317138 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in nvgpu_allocatorDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in nvgpu_allocator - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I1522b53fb4126fdc2b24fda4b86b45987fe3d203 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317137 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in fecs_trace_gk20a.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in fecs_trace_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I1fe9dd31bbc084bf66dd73dd26b395d898fde9c4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317136 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in dbg_gpu_gk20a.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in dbg_gpu_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I153ef2dd17d0fe17b3f38f6fa7e165d1aeaa2a42 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317135 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in ctxsw_trace_gk20a.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in ctxsw_trace_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I7075c6f742dba7ad4c559fedb80a3a96e824db56 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317134 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in clk_arb.cDeepak Nibade2017-03-14
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in clk_arb.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I823888ec234ce5358187c449de8e6cabc5fc5503 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1317133 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: fix suspending all SMsCory Perry2017-03-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_suspend_all_sms(), we currently loop over all GPCs and then loop over all TPCs in inner loop But this is incorrect and leads to SM with invalid GPC,TPC ids Fix this by looping over number of TPCs in each GPC in inner loop Also, fix gk20a_gr_wait_for_sm_lock_down() as per below - we right now wait infinitely for SM to lock down - restrict this wait with a timeout on silicon platforms - return ETIMEDOUT instead of EAGAIN - add more debug prints with additional data for SM lock down failures Bug 200258704 Change-Id: Id6fe32e579647fd8ac287a4b2ec80cbf98791e0d Signed-off-by: Cory Perry <cperry@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1316471 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refactor interrupt handlingDavid Nieto2017-03-14
| | | | | | | | | | | | | | | | | | | | | JIRA: EVLR-1004 (*) Refactor the non-stalling interrupt path to execute clear on the top half, so on dGPU case processing of stalling interrupts does not block non-stalling one. (*) Use a worker thread to do semaphore wakeups and allow batching of the non-stalling operations. (*) Fix a bug where some gpus will not properly track the completion of interrupts, preventing safe driver unloads Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1312796 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: debug dump enablement for t19xSeema Khowala2017-03-09
| | | | | | | | | | | | Fifo ops added for dumping channel & ramfc status and pbdma & engine status. Change-Id: Icc739f4f05f0864721954489517fefdfa2fa608a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1302369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add clear single SM error stateThomas Fleury2017-03-09
| | | | | | | | | | | | | | | | | | | | | | Add support for clearing single SM error state for CUDA debugger. In addition to clearing local copy of SM error state, vgpu_gr_clear_sm_error_state now sends a command to RM server (TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE), to clear global ESR and warp ESR. Bug 1791111 Change-Id: I3a1f0644787fd900ec59a0e7974037d46a603487 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1296311 (cherry picked from commit fd07e03c3d086f396e4d65575c576a4dd68c920a) Reviewed-on: http://git-master/r/1299060 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry <cperry@nvidia.com> Tested-by: Cory Perry <cperry@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: suspend/resume contextsThomas Fleury2017-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | Add ability to suspend/resume contexts for a debug session (NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS), in virtualized case: - added hal function to resume contexts. - added vgpu support for suspend contexts, i.e. build a list of channel ids, and send TEGRA_VGPU_CMD_SUSPEND_CONTEXTS - added vgpu support for resume contexts, i.e. build a list of channel ids, and send TEGRA_VGPU_CMD_RESUME_CONTEXTS Bug 1791111 Change-Id: Icc1c00d94a94dab6384ac263fb811c00fa4b07bf Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1294761 (cherry picked from commit d17a38eda312ffa92ce92e5bafc30727a8b76c4e) Reviewed-on: http://git-master/r/1299059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry <cperry@nvidia.com> Tested-by: Cory Perry <cperry@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add NVGPU_GPU_FLAGS_SUPPORT_MAP_COMPBITSRichard Zhao2017-03-08
| | | | | | | | | | | | | | native gpu driver supports map compbits but vgpu does not. Bug 1778448 Bug 200275051 JIRA VFND-3513 Change-Id: I433a6f8631b495875ba899af9609203ab36187ef Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1314065 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: remove cycle stats from characteristicsRichard Zhao2017-03-08
| | | | | | | | | | | | | | | vgpu does not support cycle stats. Bug 1781434 Bug 200275051 JIRA VFND-3513 Change-Id: Id1d566027913632fc8a4f0285609be5f56b26288 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1314064 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: in-kernel kickoff profilingDavid Nieto2017-03-07
| | | | | | | | | | | | | | | | | Add a debugfs interface to profile the kickoff ioctl it provides the probability distribution and separates the information between time spent in: the full ioctl, the kickoff function, the amount of time spent in job tracking and the amount of time doing pushbuffer copies JIRA: EVLR-1003 Change-Id: I9888b114c3fbced61b1cf134c79f7a8afce15f56 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1308997 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: drop 0x in front of timed out symbolKonsta Holtta2017-03-07
| | | | | | | | | | | | | | | The Linux timer code prints an error message containing the caller when a timeout happens. The caller is formatted as a function name instead of a pointer, so don't print 0x in front of it. Bug 1799159 Change-Id: I4f86d885aba78ca20ba025a91c8c940d3c927d58 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1315749 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add fifo ops for *client_type_gpc_vSeema Khowala2017-03-07
| | | | | | | | | | *client_type_gpc_v is different for t19x Change-Id: Ic8f8eff2d98138a877ef95c6f7f40226f0d61a61 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313436 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add pmu trace support for dgpusVijayakumar2017-03-07
| | | | | | | | | | | | | | | | | | | | | | | 1) Trace buffer allocation now calls generic gmmu alloc/map. so for dGPUs they are allocated in vidmem and iGPUs they are allocated in sysmem 2) Use pmu surface mechanism to setup trace buffer params as dGPU binaries follow falcon memory structure to get mem surface params 3) Fix minor coverity issue by removing unnecessary overwrite of count variable in trace print function JIRA DNVGPU-217 Coverity ID 2431386 Change-Id: I2ae49a4e0450481cde2a778447c270a796681dad Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1312404 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change stall intr handling orderSeema Khowala2017-03-07
| | | | | | | | | | | | | | | | | | | | -Handle pbus and priv stall interrupts first. In general critical interrupts should be handled before any other non critical ones. -Dump info enabled with gpu_dbg_intr if priv_ring interrupt is flagged by fmodel. JIRA NVGPU-25 Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1311273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable trace_printk use by defaultTerje Bergstrom2017-03-07
| | | | | | | | | | | | | | | trace_printk() does an extra stringify operation before calling do_trace_printk(). The string ends up unused. This has an impact to kernel even if we never end up using trace_printk(). Disable use of trace_printk() and introduce a Kconfig option for re-enabling it. Change-Id: I2e1014f5231f2089d7dc3cb2539e3eb5f4d58361 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1295298 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: kmem abstraction and trackingAlex Waterman2017-03-03
| | | | | | | | | | | | | | | | Implement kmem abstraction and tracking in nvgpu. The abstraction helps move nvgpu's core code away from being Linux dependent and allows kmem allocation tracking to be done for Linux and any other OS supported by nvgpu. Bug 1799159 Bug 1823380 Change-Id: Ieaae4ca1bbd1d4db4a1546616ab8b9fc53a4079d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1283828 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Give nvgpu_kalloc a less generic nameAlex Waterman2017-03-03
| | | | | | | | | | | | | | | | | | | | | | Change nvgpu_kalloc() to nvgpu_big_[mz]alloc(). This is necessary since the natural free function name for this is nvgpu_kfree() but that conflicts with nvgpu_k[mz]alloc() (implemented in a subsequent patch). This API exists becasue not all allocation sizes can be determined at compile time and in some cases sizes may vary across the system page size. Thus always using kmalloc() could lead to OOM errors due to fragmentation. But always using vmalloc() is wastful of memory for small allocations. This API tries to alleviate those problems. Bug 1799159 Bug 1823380 Change-Id: I49ec5292ce13bcdecf112afbb4a0cfffeeb5ecfc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1283827 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove nvgpu_gpuid_t18x.hAlex Waterman2017-03-02
| | | | | | | | | | | | | | | Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate the relevant definitions and defines into their expected places and make the code use the real defines. No longer is hiding t18x specific stuff necessary. Bug 1799159 Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1300976 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add and move FECS trace flagvishnu Reddy2017-03-02
| | | | | | | | | | | | | | | | Added fecs trace characteristic flag to vgpu to determine for platform support Also moved fecs flag from ctxsw init to fecs init for native linux. This makes flag init uniform across both platforms. JIRA EVLR-993 Change-Id: Id62f31954cb5d7028ef01a199548f5f908b51eb0 Signed-off-by: Vishnu Reddy Mandalapu <vmandalapu@nvidia.com> Reviewed-on: http://git-master/r/1305045 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add worker for watchdog and job cleanupKonsta Holtta2017-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a worker thread to replace the delayed works in channel watchdog and job cleanups. Watchdog runs by polling the channel states periodically, and job cleanup is performed on channels that are appended on a work queue consumed by the worker thread. Handling both of these two in the same thread makes it impossible for them to cause a deadlock, as has previously happened. The watchdog takes references to channels during checking and possibly recovering channels. Jobs in the cleanup queue have an additional reference taken which is released after the channel is processed. The worker is woken up from periodic sleep when channels are added to the queue. Currently, the queue is only used for job cleanups, but it is extendable for other per-channel works too. The worker can also process other periodic actions dependent on channels. Neither the semantics of timeout handling or of job cleanups are yet significantly changed - this patch only serializes them into one background thread. Each job that needs cleanup is tracked and holds a reference to its channel and a power reference, and timeouts can only be processed on channels that are tracked, so the thread will always be idle if the system is going to be suspended, so there is currently no need to explicitly suspend or stop it. Bug 1848834 Bug 1851689 Bug 1814773 Bug 200270332 Jira NVGPU-21 Change-Id: I355101802f50841ea9bd8042a017f91c931d2dc7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1297183 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use litter val for pbdma/eng *status__size*Seema Khowala2017-03-02
| | | | | | | | | | | | | | | fifo_pbdma_status__size_1_v() and fifo_engine_status__size_1_v() are not same for all gpus. Use litter value to calculate chip specific fifo*status__size_1(v) JIRA GV11B-45 Change-Id: I3d3d45bf79d15e14739fcc18cb1ca987669d5c11 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1312688 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Allow compute preemption mode on PASCAL_A classSandeep Shinde2017-03-02
| | | | | | | | | | | | | | | | | | Remove restriction of setting compute preemption mode for channels created with PASCAL_COMPUTE_A class only and allow it to be set for PASCAL_A class too. Also print compute preemption mode during channel closing. Bug 200284575 Change-Id: I2de3b3acda128e91caa2ab0fd341915ce6e6520b Signed-off-by: Sandeep Shinde <sashinde@nvidia.com> Reviewed-on: http://git-master/r/1313286 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Donghan Ryu <dryu@nvidia.com>
* gpu: nvgpu: Do not bind FECS trace on VPR channelsTerje Bergstrom2017-03-02
| | | | | | | | | | | | | | | | VPR channels can access VPR, and writing to FECS buffer outside of VPR causes a region violation. Bug 1877511 Change-Id: Ida466c81e928d1f67bf1b0e7dd6afb799c1ab2f6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1312759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Tested-by: Season Li <seasonl@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: check for pmu enableseshendra Gadagottu2017-03-02
| | | | | | | | | | | | Check for pmu enable, before calling pmu_destrory(). Change-Id: I64c5071ed69b6b50140e46da48a2b165c1f7ba02 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1313391 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-28 19:56:56 -0400