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* gpu: nvgpu: gv11b: fix for replay fault addr equal to 0Seema Khowala2017-07-19
| | | | | | | | | | | | | | | fault_addr "0" is not supposed to be fixed ever. For the first time when prev = 0, next = 0 and fault addr is also 0 then handle_mmu_fault_common will not be called. Fix by checking fault_addr not equal to 0 Bug 200277163 Change-Id: I532bca54a85e540415b9f5f5e71daec9cf0e0619 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522653 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: support egpc and etpc context regoptypeSeema Khowala2017-07-19
| | | | | | | | | | | | | | | | - implement is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops - implement decode and create priv addr for egpc/etpc JIRA GPUT19X-49 Bug 200311674 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Change-Id: Ia0cef51b2064df28460711185cd90b60aac03e4f Reviewed-on: https://git-master.nvidia.com/r/1522450 GVS: Gerrit_Virtual_Submit Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com> Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init access_smpc_reg gr opsSeema Khowala2017-07-19
| | | | | | | | | | | | | | This is needed to support t19x smpc register addresses JIRA GPUT19X-49 Bug 200311674 Change-Id: I67146d997d96eeca4344ed0fb4cabbc216461c6c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1508543 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init perf related gr opsSeema Khowala2017-07-19
| | | | | | | | | | | | | | | Implement gv11b specific perf gr ops JIRA GPUT19X-49 Bug 200311674 Change-Id: Ia65fe84df6e38e25f87d2c1b21c04b518c334d42 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1497402 GVS: Gerrit_Virtual_Submit Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com> Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: h/w header updated for CL 38810810Seema Khowala2017-07-17
| | | | | | | | | | H/w header updates for FPGA SNAP_0617 Change-Id: I6d3fe0b5b36de5999b09b9aa65e6dde2817634b5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1515766 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: updated clock gating prod settingsSeema Khowala2017-07-17
| | | | | | | | | | Updated clock gating prod settings for HW CL 38810810 Change-Id: Ie0769edb41b46e323b042a654e6002a4f7044030 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1517514 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw methodLauri Peltonen2017-07-14
| | | | | | | | | | | | | | | | The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1516205 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: Reorg debug HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the debug and dbg_session_ops sub-modules of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I23cda2fbb47fb41975a4a938e352a7427853be94 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514820 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Move gops.mc's non-fp membersSunny He2017-07-13
| | | | | | | | | | | | | | | | | | Move non-function pointer members out of the mc substruct of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. gops.mc.intr_mask_restore is now mc_intr_mask_restore Jira NVGPU-74 Change-Id: I789087704fb5e6338f6010f18457948d0ee6c630 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509604 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Reorg mc HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509603 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Reorg falcon HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the falcon sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If980fcd2605a445bd623a5fcca8262826ce289c4 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: support SET_SKEDCHECK s/w methodsSeema Khowala2017-07-13
| | | | | | | | | | | | | | | Support sw method NVC397_SET_SKEDCHECK and NVC3C0_SET_SKEDCHECK data fields are data:0 SKEDCHECK_18_DISABLE data:1 SKEDCHECK_18_ENABLE Bug 200315442 Change-Id: I0652434ab0b4d6e49dab94be329072861e99c38c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1515772 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: recover from replay and ce mmu faultSeema Khowala2017-07-12
| | | | | | | | | | | | Fix pte valid bit for replayable fault and ce fault JIRA GPUT19X-12 Change-Id: I77a7a452d9b5b304f182e120e8d75959d46d4422 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1515538 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: set replay fault for tex and gccSeema Khowala2017-07-12
| | | | | | | | | | | | | This is to enable replay fault from tex and gcc engines JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I0cc8a59499da9eb056d19ee8d6cd33a94e3f0835 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1493407 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: check bar2 bind_statusSeema Khowala2017-07-11
| | | | | | | | | | | | | | This is needed as BAR1 support is removed and there is no way to know if gpu successfully accessed memory. JIRA GPUT19X-115 Change-Id: I5d18b6bf73e11b103d1951d2e28fb1f895e72c85 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515813 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: enable and handle mpc exceptionSeema Khowala2017-07-10
| | | | | | | | | | | | | Implement gr ops to handle MPC exception triggered per TPC JIRA GPUT19X-69 Change-Id: Ia92b1d51ad896116b25d71e07ed26f1539475be8 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515915 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: fifo recovery for nonreplay faultSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | Host will no longer receive replayable or non-replayable fault requests. MMU will handle both types of fault reporting. This means that Host will no longer automatically disable scheduling or preempt a PBDMA when an engine page faults. After fault happens, engine will stall on its own fault and will not context switch until the fault is serviced JIRA GPUT19X-7 Change-Id: I8039e6f50d87f43e101d1372faa5ca6fb739036e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1493417 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: add mmu fault handlingSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: set up for enabling/handling hub intrSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: generated mmu fault fields/masksSeema Khowala2017-07-08
| | | | | | | | | | | | | Generated h/w header for mmu fault handling JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I857ab6b67f6d9ac9a2c2ee982496dd0603bd010e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1494842 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add support for L3 cache allocation of buffersDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | | | | | | Add gv11b implementation of gpu_phys_addr() that checks the t19x GMMU attributes struct to determine if L3 allocation should be enabled. If L3 alloc is enabled then a special physical address bit is set. Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct nvgpu_as_map_buffer_ex_args so that User space can add a hint to allocate buffer in L3 cache Jira GPUT19X-10 Bug 200279508 Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512602 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: enable IO coherence support flag for gv11bDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | Set flag NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE for gv11b to indicate IO coherence support is enabled Jira GPUT19X-17 Bug 1651331 Bug 200283998 Change-Id: If74db3de293e8ebd39e45d81cd1c0d1f7aa01d2d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512601 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Implement PD packingAlex Waterman2017-07-06
| | | | | | | | | | | | | Necessary Volta changes for equivalent change in nvgpu. JIRA NVGPU-30 Change-Id: I541d6d6005bc7ea0bfb654d0f5f5554e46afc510 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1506611 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init handle_sm_exception gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | | | | gr_gk20a_handle_sm_exception is initialized to handle_sm_exception and new gr ops handle_tpc_sm_ecc_exception is initialized to gr_gv11b_handle_tpc_sm_ecc_exception to handle sm ecc errors per tpc. JIRA GPUT19X-75 JIRA GPUT19X-109 Change-Id: Iefa95b185b9eed23f9f54e231405fcd9fd83ccc0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514039 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init clear_sm_hww gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Required for multiple SM support and SM register address changes JIRA GPUT19X-75 Change-Id: I552bae890a416dc4a430b907641b5b3d09b638c7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514038 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init sm lock_down gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | init lock_down_sm and wait_for_sm_lock_down gr ops Required to support multiple SM and register address changes JIRA GPUT19X-75 Change-Id: I992d1c0c5a1f559dc57bcef50025fa42913d6761 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514037 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init get_sm_no_lock_down_hww_global_esr_mask gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | Support SM register changes JIRA GPUT19X-75 Change-Id: I5d5e702d681398a8a8181d912e8c691c15e265d9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514036 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init gr ops get_sm_hww_global_esrSeema Khowala2017-07-06
| | | | | | | | | | | | | Required for multiple SM support and sm register address changes JIRA GPUT19X-75 Change-Id: I3fb62a935636f3df050ed125ebe57d8469069591 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514035 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Reorg misc HAL initializationSunny He2017-07-06
| | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the lone function pointers of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I098559103ef280faca4e82708bb47b9b37057cfd Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1510390 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b, use nvgpu_flcn_bootstrap()Mahantesh Kumbar2017-07-06
| | | | | | | | | | | | | | - Replaced falcon bootstrap code with nvgpu_flcn_bootstrap() method JIRA NVGPU-102 Change-Id: I5133419957c890847cac66c5ac018e8188db41e3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1513647 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Use g->name instead of dev_name()Terje Bergstrom2017-07-05
| | | | | | | | | | | Dump device name using g->name instead of dev_name(). dev_name() is Linux specific. Change-Id: I65eb89e41ca81ca6143fb247a10c306b4efc96ad Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1512176 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: support for full subcontextseshendra Gadagottu2017-07-05
| | | | | | | | | | | | | | | | | Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: init get_sm_hww_warp_esr gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | get sm hww_warp_esr reg val JIRA GPUT19X-75 Change-Id: I4ed04045e947c417291b7b1e2fc81bbe51f0b48c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512212 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init resume_from_pause gr opsSeema Khowala2017-07-05
| | | | | | | | | | | JIRA GPUT19X-75 Change-Id: Ie741bf50c771f21de3bf762ca506a36276f38437 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512211 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init resume_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Ia5c0a3d1dead9c6094ca28716c06929dd3461814 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512210 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init resume_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I0ebbfdad73d6212997a21f9240f5d4bc2f28ab2f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512209 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init suspend_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I46b7d58ed02710339aa27cd9db999aa60fbd4dd9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512208 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init suspend_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | Take care of SM register address changes. JIRA GPUT19X-75 Change-Id: I7fa68dbef014fb07a3656b2816d7d8d538a7cf52 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512207 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init sm_debugger_attached gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | Support gv11b sm register address changes. JIRA GPUT19X-75 Change-Id: I22562789ef7c064fa36c2d382224af6dc6a806c7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512206 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Use sm dbgr bpt and warp mask 0/1Seema Khowala2017-07-05
| | | | | | | | | | | | | | Instead of assuming mask_0 and mask_1 as consecutive registers, use mask_1 and mask_0 registers for reading/writing sm dbgr warp and bpt mask registers JIRA GPUT19X-75 Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1511736 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: read from unicast registerSeema Khowala2017-07-05
| | | | | | | | | | | | | | For updating broadcast register, read the current value from unicast register. JIRA GPUT19x-75 Change-Id: Ib4a3791304cabe77cf46543d4bec0312c6fcc0fb Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1511735 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b, rename gk20a_pmu_cmd_post()Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I1ce20cdd7190311535917058ad09a8896e505179 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512972 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: add a function to reset pbdma and eng faultedSeema Khowala2017-07-02
| | | | | | | | | | | | | | | | | | | | When Host receives a page fault signal from a CE, Host will immediately set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel and will trigger a preempt of the TSG/channel. A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0 and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel. If a TSG has a faulted channel, Host will not schedule the entire TSG agin until all _FAULTED bits from channels in the TSG are cleared by SW. This function will be required for ce page fault handling. JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1509776 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: implement eng method buffer init/deinitSeema Khowala2017-07-02
| | | | | | | | | | | | | | | | | | | | | | When CE hits a page fault it needs to save out methods, it will save it out to a per runqueue per TSG method buffer. The method buffers (one per TSG runqueue) are allocated in BAR2 space during TSG creation All channels in a TSG that are mapped to the same runqueue will point to the same buffer. S/w will insert channel's method buffer pointer in the channel's instance block entries NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO and NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI. Method buffer in memory will be 32B aligned. Eng method buffer allocated per tsg will be de-allocated during tsg_release. JIRA GPUT19X-46 Change-Id: Ib480ae5840d9815d24fe2eadc169ac3102854cd0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1509747 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init get_num_pce ce opsSeema Khowala2017-07-02
| | | | | | | | | | | | | | | Implement get_num_pce ce ops to get number of physical copy engines. This is required to calculate eng method buffer size JIRA GPUT19X-46 Change-Id: I5a37eb26ec11bc358700d1761cfdb6ca060e4287 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1511788 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add ce interrupt handlingSeema Khowala2017-07-02
| | | | | | | | | | | | | | | | | | | | | | Added handling for below ce interrupts -INVALID_CONFIG interrupt will be generated if a floorswept PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG registers. This is a fatal error and the LCE will have to be reset to get back to a working state. -MTHD_BUFFER_FAULT interrupt will be triggered if any access to a method buffer during context load or save encounters a fault. This is a fatal interrupt and will require at least the LCE to be reset before operations can start again, if not the entire GPU. JIRA GPUT19X-12 JIRA GPUT19X-46 Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1510298 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Per chip default big page sizeTerje Bergstrom2017-06-30
| | | | | | | | | | | | | Stop defining per-platform default big page size. It's defined via HAL and inherited from gp10b. JIRA NVGPU-38 Change-Id: If5eedd5d351d5504bdf87489d1aa091d430c43ba Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1508069 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: check flag before enabling CG.Deepak Goyal2017-06-30
| | | | | | | | | | | | | | | | We should check if BLCG/SLCG feature is enabled before trying to enable/disable them in hardware. Bug 200314250 Change-Id: I5431f97cc559444298b7bd4d53a9f4fc598fd268 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master/r/1509184 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init set_hww_esr_report_maskSeema Khowala2017-06-30
| | | | | | | | | | | | | | gv11b has 2 SMs per TPC. Use *gpcs_tpcs_sms_hww_warp/global_esr* registers instead of *gpcs_tpcs_sm_hww_warp/global_esr* GPUT19X-75 Change-Id: I86c7ded32b2b69214e047e6de67a1745f2cef6f3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1474860 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init record_sm_error_state gr opsSeema Khowala2017-06-30
| | | | | | | | | | | | | Take care of t19x sm reg address changes and support multiple SM JIRA GPUT19X-75 Change-Id: I675b76b90d08fe75331f0023f1fe722497d06373 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1477673 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:11:20 -0500