| Commit message (Collapse) | Author | Age |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fix below sparse warning by declaring gp10b_write_dmatrfbase()
as static
kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol
'gp10b_write_dmatrfbase' was not declared. Should it be static?
Bug 200088648
Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/801213
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Must write DMATRFBASE1 to 0 whenever
DMATRFBASE is written.
Bug 200137618
Change-Id: Id8526d1bafbd116ffc4d8018983791fe9e9fa604
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798780
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
- clear mask to load gpcss with priv load.
Bug n/a
Change-Id: I21522bda83c4dd5c665d47ae334b9fed5cb8ec74
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798406
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Specify that everything in bar2 VM is kernel reserved.
Bug 200077571
Change-Id: I8f6c6ac6352ffd64eedc09187593b6c8d05757ef
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/746802
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Bug 1667322
Accomodate for transcfg address change
Change-Id: I83c5d4921040258a480df44a69792c721ff88f05
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/779764
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Add CDE program number selection for GP10B.
Bug 1604102
Change-Id: I0054e670e3bc6b8c2380124eb58204088aaae275
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/785459
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
bug 1675413
work around for timestamp slcg bug
Change-Id: I0950403b89e9ea161bd7eb7052f47de3f9733240
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/785854
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Use physical addresses in PDEs. All page table levels fit in 4k, so no
need for SMMU mapping.
Change-Id: Id9e418f35a79343f4a332a230e04abda5e0dd5d2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/783748
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
|
|
|
|
|
|
|
|
|
|
| |
This reverts commit f7bf99929cf2ec5a295ac21c74cf9c4f1afd78c5.
Change-Id: I0acfa18e9cf9bedd4051ec00faa497b3cdb9454b
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/768599
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fixed the following sparse warning by making the local function as static:
- symbol 'gp10b_pmu_load_multiple_falcons' was not declared.
Should it be static?
- symbol 'gp10b_load_falcon_ucode' was not declared.
Should it be static?
bug 200067946
Change-Id: I67d865aef6f57bf614db351929cd4bb1b6077c00
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/764646
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
|
|
|
|
|
|
| |
Implement support for privileged pages. Use them for kernel allocated buffers.
Change-Id: I24778c2b6063b6bc8a4bfd9d97fa6de01d49569a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/761920
|
|
|
|
|
|
|
|
|
|
| |
bug 200080684
Change-Id: I013a0ca7762f6cca0498bd282303597bf683cb7d
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/746737
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Use always physical addresses for page tables. In gp10b new format
each level fits in one page, so we do not need SMMU translation.
Change-Id: Ie46b2bce0f7a4e8d2904d74b1df616e389874141
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/758181
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Add regops whitelists for gp10b. The whitelist is generated, and is the
same for context switched and global registers.
Bug 1633363
Change-Id: I6d4d43d036d684c9f0d836a1a032f2c452604902
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760935
|
|
|
|
|
|
|
|
|
|
|
| |
gm20b clock registers do not exist in gp10b. Skip setting the clock
HAL to gm20b variants.
Change-Id: Ieaa9a04a8afbe772864d947d968e3e1c7f9968e9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760854
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update sync point protection field only when we have a valid sync
point id, and the new id is different from old id.
Bug 1653328
Change-Id: Ie07e26f8abd7c8239ad562603b62fda00164cbc7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/757102
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
|
|
|
|
|
|
|
|
|
| |
Bug 1642669
Change-Id: I683338256b7f2a165a7933aa59de510eb109ea6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755150
Reviewed-by: Automatic_Commit_Validation_User
|
|
|
|
|
|
|
|
|
|
| |
Set address check mode for SM.
Bug 1625763
Change-Id: I5ddf8334673b414956e57c55aaa5be1a9f9aeaf1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752139
|
|
|
|
|
|
|
|
|
|
|
| |
Alpha and beta sizes need to be clipped to a maximum value. For
alpha CB we were using beta size in clipping, and for both we were
not using number of TPCs to determine the max value.
Change-Id: I0c925464ba4c9f575e6e59dd5ba7759aa1cb6381
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752667
Reviewed-by: Automatic_Commit_Validation_User
|
|
|
|
|
|
|
|
|
| |
Some fields have different widths, so duplicate the code to program
global bundle CB.
Change-Id: Ib6af5abf3e90dfa1bcda2fbc6b97ad1031e6ab16
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752635
|
|
|
|
|
|
|
|
| |
Program CB base to new gp10b registers.
Change-Id: I1ab39a487dade58d3a024fb1aba1af5c878f31bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752634
|
|
|
|
|
|
|
|
|
|
| |
When allocating betacb for a GfxP channel, add both alpha and beta
cb sizes together.
Change-Id: I8cef62f6272bfb3b5e9a3835a51590e5eb91dc92
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752633
Reviewed-by: Automatic_Commit_Validation_User
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Compbit backing store did not take into account number of GOBS
per comptagline per slice.
Bug 1604102
Change-Id: I42666e72ea54697b6fbc7318e65a6a09d867f5b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/754706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This reverts commit 053037f1450d6ba6c5d01abcdcd9b24019ae8c85
since the issue seen with bug 200106514 is fixed with change
http://git-master/r/#/c/752080/.
Bug 200112195
Change-Id: If54eb570fd2ad5de99d180d03d5d90492283fe33
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/752504
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Kick channel off PBDMA before writing new sync point id to allowed
sync points.
Bug 1648297
Bug 1646477
Change-Id: I7c686d474c403fdd54bc64cff63b7d049feecb4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/750981
|
|
|
|
|
|
|
|
|
|
|
|
| |
Expose CILP and GFXP flags to user space ioctl
NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX.
Bug 200111328
Change-Id: I10931db2babd3222e308fd491824d95204355ff3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/748932
GVS: Gerrit_Virtual_Submit
|
|
|
|
|
|
|
|
| |
Change-Id: Ic71ff2408bd01a1bf5cf1354453a2fe715438cf0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/751555
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Change for new VA space allocator is being reverted with
http://git-master/r/#/c/749291/ but only for Kernel3.18
In Kernel3.10, we support the new VA allocator
Since we support both the kernel versions as of now,
use a KERNEL_VERSION based mechanism to select
appropriate call
Define new macro NVGPU_USE_NEW_ALLOCATOR for Kernel3.10
where we want to use new allocator
Bug 200106514
Change-Id: I9af26d555278c40e03fe82b0912961a862c8bf55
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/751353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable re-playable faults based on characteristics
flags passed in channel_setup_ramfc.
Bug 1645628
Change-Id: I7176efb3e5af9fefe5fb92cd5b49eb295e8e2c4a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/743382
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The produced wrappers for HW PM registers access which are required for
cyclestats support for snapshot buffers mapping.
See commit 589e7a9ffe2a5a70f8803a88fcf8429f553e2fba for tools:nvhost
generators update.
Bug 1573150
Bug 1517458
Change-Id: I9c9332a55f2282c0c626bc8ddbcfdce1289f778b
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/747717
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
ZBC is safe to update and GPU is safe to rail gate when units are
in preempted or empty state. Idle may never be reached in case of
graphics preemption, so relax the ZBC update wait condition.
Bug 1640378
Change-Id: I40c59e9af22a7a30b777c6b9f87e69d130042e44
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/745655
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
We were dropping the part of address that span word bounary. The register
generator does not know how to real with multi-word fields, to edit things
in manually.
Bug 1646531
Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/747468
|
|
|
|
|
|
|
|
|
|
|
| |
This reverts commit 30e5947fa1f26ed6bb4f137fd76c8869e91b9829.
The original commit was actually fine.
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Change-Id: I0454415981d29ed0b877f7a21db6f54bc4c30470
Reviewed-on: http://git-master/r/743302
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
| |
This reverts commit 3a4f0285c7e9212b394b2c1b151987a7084de927.
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I886e434ce98e85f99b0a77749179e31c0bd00620
Reviewed-on: http://git-master/r/741468
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The comptag allocator is made in the chip-specific init code
for the comptags. Thus, a t18x change needs to be made to make
sure the new allocator code compiles and works on t18x.
Change-Id: I57a34f3c61ebd31f875caa577378e829812f2d4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/721171
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
| |
bug 200080684
Change-Id: I5888939017877a50b9bd596393ee8ad1547c18e5
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/732535
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
VPR allocator needs to be used when allocating graphics context for
VPR channels. Define it for gp10b.
Bug 1625090
Change-Id: Ie2e3a865c310c34c629627891ac0b579f299983f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737846
Reviewed-by: Automatic_Commit_Validation_User
|
|
|
|
|
|
|
|
|
|
| |
Used 128k comptag spacing, when 64k is the correct one.
Bug 1525976
Change-Id: Ie2f926929fa89cf715b86a57ffbf4dd1e4920473
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737947
|
|
|
|
|
|
|
|
|
|
| |
Enable new page table format for all platforms.
Bug 1525976
Change-Id: I9a3cfabdef7dc6ec33e18a8a4f32063c40f680fa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737364
|
|
|
|
|
|
|
|
|
|
| |
Fix caching attribute on 5-level page tables.
Bug 1525976
Change-Id: I5c5bf336d87c642f42a387206a55a889e6e07ba6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737923
|
|
|
|
|
|
|
|
|
|
| |
Calculate GFXP attrib cb buffer size from the global buffer size.
Bug 1628352
Change-Id: If4edfbf5700334b791dbf8e5cf38fd0208ee7fa1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/735717
|
|
|
|
|
|
|
|
|
|
|
| |
If betacb size has been given via debugfs, use that instead of the
calculated number.
Bug 1628352
Change-Id: I8c68c27a2bfdd7f013776734ef846377a89b0033
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/733332
|
|
|
|
|
|
|
|
|
| |
Change-Id: I05b2554588e5e1001cdbb54551cf8a064ea531bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/711303
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: I222bebd958e29b3a95d161f05a3052389200fc10
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/736663
GVS: Gerrit_Virtual_Submit
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
|
|
|
|
| |
Change-Id: I1fcc7e93d3e31bfbb5d540b43b655566f6dc13cd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/732010
|
|
|
|
|
|
|
| |
Change-Id: I4931958c21692306d6c78bffdc45e21c553b913c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/731494
|
|
|
|
|
|
|
|
|
|
|
| |
Augment new page mapping code to be aware of scattered
buffers.
Bug 1605769
Change-Id: Ifdb326563d28ccf07fc4d3d76a24492a68493fe3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/734355
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Added final elpg sequencing value
- by default elpg is disabled.
Bug 1525971
Change-Id: I2c306d9f03e361560a95fcfa723eafe14d004191
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/732574
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- set "privsecurity" to 1 to enable secure boot else
set to 0.
Bug 200085428
Change-Id: Ia4bf214f4a4bb2573c8869ea2182bbe680f67782
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/729101
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
-method gm20b_pmu_init_acr() used for gp10b
acr init wpr region
Bug 200085428
Change-Id: I897aa42b0a8ef7478d4b3f64fe1834532d35b303
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/732213
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
|