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* gpu: nvgpu: t18x, gp10b frameworkKenneth Adams2016-12-27
| | | | | | | | | | | This change adds gp10b to the nvgpu build as well as enabling CMA for buffer allocation. Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76 Signed-off-by: Ken Adams <kadams@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/553324 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Synchronize gp10b headers with gm20bTerje Bergstrom2016-12-27
| | | | | | | | | | | | Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: headers for linsim CL 33759297Adeel Raza2016-12-27
| | | | | Change-Id: Iaafb651875481b7fa31504642df86311ec9933a5 Signed-off-by: Adeel Raza <araza@nvidia.com>
* gpu: nvgpu: headers for linsim CL 33688874Adeel Raza2016-12-27
| | | | | | | | | | Bug 1561645 Change-Id: Iccd909d54fc5b1d1c8fbc903b5908bf6f7f22ec8 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/553151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: gp10b headersKen Adams2016-12-27
| | | | | | | | first cut. just to get started... Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d Signed-off-by: Ken Adams <kadams@nvidia.com> Reviewed-on: http://git-master/r/447753
* gpu: nvgpu: acquire mutex for notifier readDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use &ch->error_notifier_mutex to protect writes and free of error notifier But we currently do not protect reading of notifier in gk20a_fifo_set_ctx_mmu_error() and vgpu_fifo_set_ctx_mmu_error() Add new API gk20a_set_error_notifier_locked() which is same as gk20a_set_error_notifier() but without the locks. In *_fifo_set_ctx_mmu_error() APIs, acquire the mutex explicitly, and then use this new API gk20a_set_error_notifier() will now just call gk20a_set_error_notifier_locked() within a mutex Bug 1824788 Bug 1844312 Change-Id: I1f3831dc63fe1daa761b2e17e4de3c155f505d6f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1273471 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: set driver unload flag in shutdownDeepak Nibade2016-12-27
| | | | | | | | | | | | | | Call gk20a_driver_start_unload() in the beginning of gk20a_pm_shutdown() so that we prevent new calls to gk20a_busy() Bug 200265373 Change-Id: I240cab4b505be4928341ab3deb13f37241d27aeb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1275486 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gk20a: Allow regops lists longer than 128Sami Kiminki2016-12-26
| | | | | | | | | | | | | | | | Process long regops lists in 4-kB fragments, overcoming the overly low limit of 128 reg ops per IOCTL call. Bump the list limit to 1024 and report the limit in GPU characteristics. Bug 200248726 Change-Id: I3ad49139409f32aea8b1226d6562e88edccc8053 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1253716 (cherry picked from commit 22314619b28f52610cb8769cd4c3f9eb01904eab) Reviewed-on: http://git-master/r/1266652 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PG statistics updateMahantesh Kumbar2016-12-26
| | | | | | | | | | | | | | | | | | | | - PG statistics read support for multiple engines - updated stat_dmem_offset member to array to hold dmem offset of PG engines - PMU allocates memory in DMEM for each PG engine requested, updated gk20a_pmu_get_elpg_residency_gating() to get engine statistics for requested PG engine JIRA DNVGPU-71 Change-Id: I2ddade37f85716f757bf33034dbff816184577eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1250506 (cherry picked from commit 68ba7a97d6662b87d0e489365d8afb8e2d237a03) Reviewed-on: http://git-master/r/1270972 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: MSCG supportMahantesh Kumbar2016-12-26
| | | | | | | | | | | | | | | | | | | | | | | | | - Added enable_mscg, mscg_enabled & mscg_stat flags, mscg_enabled flag can be used to controll mscg enable/disable at runtime along with mscg_stat flag. - Added defines & interface to support ms/mclk-change/post-init-param - Added defines for lpwr tables read from vbios. - HAL to support post init param which is require to setup clockgating interface in PMU & interfaces used during mscg state machine. - gk20a_pmu_pg_global_enable() can be called when pg support required to enable/disable, this also checks & wait if pstate switch is in progress till it complets - pg_mutex to protect PG-RPPG/MSCG enable/disable JIRA DNVGPU-71 Change-Id: If312cefc888a4de0a5c96898baeaac1a76e53e46 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247554 (cherry picked from commit e6c94948b8058ba642ea56677ad798fc56b8a28a) Reviewed-on: http://git-master/r/1270971 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rppg supportMahantesh Kumbar2016-12-26
| | | | | | | | | | | | | | | Add defines and interface structures used for sending PMU messages to control RPPG. JIRA DNVGPU-71 Change-Id: Ibec975f3c976619542d8f088b24271796a03f03c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247487 (cherry picked from commit dd3826abca0a51d473d5d9cb25dc84cada9e7878) Reviewed-on: http://git-master/r/1270793 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make preemption modes unsignedDeepak Nibade2016-12-21
| | | | | | | | | | | | | | | | | | | | graphics and compute preemption modes are currently defined as int But it is more logical to have them as unsigned int Also, we treat preemption modes as unsigned almost everywhere in the code Fix prints in gk20a_fifo_sched_debugfs_seq_show() to print U32_MAX with %d which is same as printing -1 Bug 200263471 Change-Id: Iabd0ee3923b76d81620898e90a9b1fc5dd75b530 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1272514 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: define common API to write fusesDeepak Nibade2016-12-21
| | | | | | | | | | | | | | | | | | | | | | | We use tegra_fuse_control_write() on k4.4 and tegra_fuse_writel() on previous versions But gr_gm20b_set_gpc_tpc_mask() currently broken since we use tegra_fuse_writel() always to update fuses Hence define tegra_fuse_control_write() on previous kernel versions as well and use it everywhere Bug 200262155 Change-Id: I116ed77d24018dae21884344373c9eaa1750c2bd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1270168 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove clk writel from TPC FSDeepak Nibade2016-12-21
| | | | | | | | | | | | | | | | | | | | To floorsweep any TPC on gm20b, we first have to set BIT(28) in CLK_RST_CONTROLLER_MISC_CLK_ENB_0 from nvgpu driver But now this bit is set by default from clock driver, hence remove clk_writel() from nvgpu driver Bug 200262155 Change-Id: I65bc60cb017109bdb882d83637f2a06d27586f18 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1265752 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix round_rate ops for CCFSrikar Srimath Tirumala2016-12-21
| | | | | | | | | | | | | | | | | Make round_rate return max freq when called with a value greater than the max clock frequency. Bug 200233943 Change-Id: Id128611f2d09b17a0a0edfefd4b526fd8c215bce Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1272305 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
* gpu: nvgpu: fix build breakSrikar Srimath Tirumala2016-12-20
| | | | | | | | | | | Fix the build break caused by "commit : I88d94542092f92e68dc63c40444a70991d1f6129" Change-Id: Id457c26b17ba8fc05e26fb5ad3b3a4873362b950 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1274496 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
* gpu: nvgpu: Fix coverity defect in page allocatorAlex Waterman2016-12-20
| | | | | | | | | | | | | | | Fix use-after-free overity defect in page allocator. The alloc struct was getting used after a call for __gk20a_free_pages() which frees the alloc struct passed in. Coverity ID: 468942 Bug 200192125 Change-Id: I4f5d32f245efae967050f93c7806290b4bf3591c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1272730 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix gpcclk for K4.4Srikar Srimath Tirumala2016-12-20
| | | | | | | | | | | | | | | Move the sw initialization of the gpcclk from gpu rail ungate path to the nvgpu probe path. This allows gpcclk to register itself successfully with CCF and makes it discoverable for other clients early on during boot. Bug 200233943 Bug 200259437 Change-Id: I88d94542092f92e68dc63c40444a70991d1f6129 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1265549 Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
* gpu: nvgpu: gm20b pass correct clk to tegra_dvfsPeter Boonstoppel2016-12-20
| | | | | | | | | | | | | | | | | | | Restoring original behavior. Use gbus instead of gpu_ref clk as the argument to tegra_dvfs_get_fmax_at_vmin_safe_t(). Bug was introduced due to refactoring in 01e61860fafbc0ee045c2db931a79f6c0d5300aa, changing behavior when nvgpu is compiled with CONFIG_TEGRA_CLK_FRAMEWORK. Bug 200233943 Change-Id: Id2deec0107bd0c26a12feb511db22fc69e09a985 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1269848 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
* gpu: nvgpu: replace tsg list mutex with rwsemKonsta Holtta2016-12-20
| | | | | | | | | | | | | | Lock only for modifications to the tsg channel list, and allow multiple concurrent readers. Bug 1848834 Bug 1814773 Change-Id: Ie3938d4239cfe36a14211f4649ce72b7fc3e2fa4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1269579 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PG engines init/allow/disallow updateMahantesh Kumbar2016-12-20
| | | | | | | | | | | | | | | | | | | | | | | - pmu_init_powergating loops & init multiple PG engines based on PG engines supported - generalize pg init param HAL to support multiple PG-engine init based on PG engine parameter - HAL's to return supported PG engines on chip & its sub features of engine. - Send Allow/Disallow for PG engines which are enabled & supported. - Added defines for pg engines JIRA DNVGPU-71 Change-Id: I236601e092e519a269fcb17c7d1c523a4b51405f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247409 (cherry-picked from commit 1c138cc475bac7d3c3fbbd5fb18cfcb2e7fdf67a) Reviewed-on: http://git-master/r/1269319 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: copy data into channel context headerseshendra Gadagottu2016-12-20
| | | | | | | | | | | | | | If channel context has separate context header then copy required info into context header instead of main context header. JIRA GV11B-21 Change-Id: I5e0bdde132fb83956fd6ac473148ad4de498e830 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1229243 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename timeout_check to timeout_expiredKonsta Holtta2016-12-19
| | | | | | | | | | | | | | Change "check" to "expired" in nvgpu_timeout_check* and append _expired to nvgpu_timeout_peek to clarify what the boolean-like return value means and thus avoid bugs. Bug 200260715 Change-Id: I47e097ee922e856005a79fa9e27eddb1c8d77f8b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1269366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support noise unaware vmin pmu cmdVijayakumar2016-12-19
| | | | | | | | | | | | | | | | JIRA DNVGPU-184 Add structures and commands to send noise unware vmin value to pmu. This is needed to enable closed loop frequency controller support Change-Id: If2dfd5e76752a25765ba68821460b7fd2df23aed Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248208 (cherry picked from commit fcd73e0f0bca755ea745f62b52b9e641bc3aa1ae) Reviewed-on: http://git-master/r/1267434 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add clk freq controller supportVijayakumar2016-12-19
| | | | | | | | | | | | | | JIRA DNVGPU-127 Add pmu interface structure and command definitions Change-Id: I5bb84f47057094f55f3adf2c5755416f430aba89 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248207 (cherry picked from commit ad385eb3ce8ffb2d55ae312901c9dcc4e1543b14) Reviewed-on: http://git-master/r/1267433 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Fix memory leaksAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | Fix a memory leak introduced when making the priv struct for TSGs. Fix another memory leak when introducing a priv struct for channels. Bug 1816516 Change-Id: I7b0e62bb6352f7e65acb5501cab9cef055d1f535 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1266889 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove BUG_ON from _IOC_SIZE checksKonsta Holtta2016-12-19
| | | | | | | | | | | | | | When the user-supplied ioctl argument size is too large, just return -EINVAL from the ioctl instead of crashing on a BUG_ON (for as, ctrl, ctxsw, dbg and tsg nodes - channel and sched nodes are already okay). Bug 1849661 Change-Id: I5b0d1d0c4ee47ce0136c424dda5975353f110c7e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1266606 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Store pending sema waitsAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | Store pending sema waits so that they can be explicitly handled when the driver dies. If the sema_wait is freed before the pending wait is either handled or canceled problems occur. Internally the sync_fence_wait_async() function uses the kernel timers. That uses a linked list of possible events. That means every so often the kernel iterates through this list. If the list node that is in the sync_fence_waiter struct is freed before it can be removed from the pending timers list then the kernel timers list can be corrupted. When the kernel then iterates through this list crashes and other related problems can happen. Bug 1816516 Bug 1807277 Change-Id: Iddc4be64583c19bfdd2d88b9098aafc6ae5c6475 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250025 (cherry picked from commit 01889e21bd31dbd7ee85313e98079138ed1d63be) Reviewed-on: http://git-master/r/1261920 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Close channels before freeing themAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | Ensure that any open channel is definitely closed before freeing it. Bug 1816516 Bug 1807277 Change-Id: I7f100db5ab6834176ec97d22374646d3336f2856 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250023 (cherry picked from commit 56f1b4b4312c5900f1c27eba55ad970c4b264f24) Reviewed-on: http://git-master/r/1261919 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Allow channel free to be forcedAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | | | Allow forced channel freeing. This is useful when the driver is being cleaned up and the gk20a_wait_until_counter_is_N() could potentially hang. Bug 1816516 Bug 1807277 Change-Id: I711f5f3f6413d0bb30b4857e785ca3b504b494ee Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250022 (cherry picked from commit e132d0e5ae77d758680ac708622a4883bbd69ba3) Reviewed-on: http://git-master/r/1261918 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reboot when GPU disappearsAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | | Reboot the GPU when it disappears instead of just printing a warning message. Bug 1805082 Bug 1816516 Bug 1807277 Change-Id: Ifd23c7e6876d5ea86032a82b7181e31d54e877b5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1260898 (cherry picked from commit 4fdc48c4e6dddf4299a49f387ac90404dd38950f) Reviewed-on: http://git-master/r/1261917 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Check for dead GPUAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | | | | | | Check if the GPU is present after each register read. If the a register read returns 0xffffffff then it's possible the GPU has fallen off the bus for some reason or another. However, to confirm that a register read is due to a dead GPU vs just a 0xffffffff being returned by happenstance the chip ID register is read which should never return 0xffffffff. If that read returns 0xffffffff as well then certainly the GPU is dead. Bug 1805082 Bug 1816516 Bug 1807277 Change-Id: I4de61b56289217d9c0d8167e84615a67c8bde8a9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1239518 (cherry picked from commit bd50828de20aba9b2887ee99c2269602c21a793f) Reviewed-on: http://git-master/r/1261916 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Allow semaphores to be force releasedAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow SW to force a semaphore release. Typically SW waits for a semaphore to reach the value right before the semaphore release value before doing a release. For example, assuming a semaphore is to be released by SW by writing a 10 into the semaphore, the code waits for the semaphore to get to 9 before writing 10. The problem with this happens when trying to shutdown the GPU unexpectedly. When aborting a channel after the GPU has terminated the GPU is potantially no longer processing anything. If a SW semaphore release is waiting on the semaphore to reach N-1 before writing N to the semaphore N-1 may never get written by the GPU. This obviously causes a hang in the SW shutdown. The solution is to let SW force a semaphore release in the channel_abort case. Bug 1816516 Bug 1807277 Change-Id: Ib8b4afd86102eacf372362b1748fb6ca04e6fa66 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250021 (cherry picked from commit 2e9fa40902d2c4d5a1febe0bf2db420ce14bc633) Reviewed-on: http://git-master/r/1261915 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add tsg private structAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | | Add a private tsg struct for the TSG file descriptors. This allows the TSG files to retain access to the gk20a struct without the TSG data structure still being available. Bug 1816516 Bug 1807277 Change-Id: If0e41d912bebb7906d72e7eee641f47604a16494 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250020 (cherry picked from commit 5d8dbbb939e10fecde341891807a0201a63b2b23) Reviewed-on: http://git-master/r/1261914 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use struct to hold gk20a pointerAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | | | | | | | The private_data field in the file pointer passed to release() for channels originally pointed directly to the referenced channel. The problem with this is that when the driver is killed and the channel mmeory is freed that pointer becomes invalid. The necessity of that channel is to get access to the gk20a struct that owns the channel. This can instead be accomplished by making a new private data struct that has a pointer to the gk20a struct directly instead of requiring the channel to be valid. This lets the release() function work even if the channels are gone (though in such cases the release function doesn't do very much). Change-Id: I5e50bb5b6dd08d38974f8e7b46ba125e9a3f1922 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1246586 (cherry picked from commit 14b7c380c74d2caeb04c47ad3e33332a423a84bb) Reviewed-on: http://git-master/r/1261913 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add busy/idle ref countingAlex Waterman2016-12-19
| | | | | | | | | | | | | | | | Add reference counting for gk20a_busy() and gk20a_idle() so that the driver can keep track of whether the driver is active. Bug 1816516 Bug 1807277 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250019 (cherry picked from commit 7f558019735bb34cf00dd1ec17df1797501cff60) Change-Id: I64c2ff1719673912ae127707e58ee557966c4d4d Reviewed-on: http://git-master/r/1261922 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add tsg_open HAL interfaceSachit Kadle2016-12-19
| | | | | | | | | | | | | | | | | | Add HAL interface for TSG open, which is intended to be called from the exisiting gk20a_tsg_open function. The tsg_open entryoint is only implemented for vgpu, as the server needs to clear metadata when a tsg is opened. Bug 200215060 Change-Id: Icc8fd602f31e52d9fa9b2e7786b665b9e7b9294e Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1249218 (cherry picked from commit 35c86f7c796c6574d3dc336e20012ea5c16d7cb4) Reviewed-on: http://git-master/r/1256468 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pci: disable elcg for dGPUsVijayakumar2016-12-19
| | | | | | | | | | | | bug 200245907 Change-Id: Ia10faf764a4b2378115c41d5e3a19a65b7bf2ddd Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1240623 (cherry picked from commit be278f2913c92ec1dfb83f9f5224d3de10a8defc) Reviewed-on: http://git-master/r/1248740 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: update vsms_mapping ioctlPeter Daifuku2016-12-17
| | | | | | | | | | | | | | | Update vsms_mapping ioctl to copy from the internal sm_to_cluster array to new nvgpu_gpu_vsms_mapping_entry array before copying the latter back to user. Bug 200260086 Change-Id: I0fccc6fb6e0d6b6f737b3a44818d2b47438cd3c8 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1266174 (cherry picked from commit e28882c05491cb8f9573ff71c2d7309e5714e385) Reviewed-on: http://git-master/r/1269623 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle vf curve change due to tempVijayakumar2016-12-15
| | | | | | | | | | | | | | | | | | | JIRA DNVGPU-129 1)Add function hook for PMU VFE event handler which will do for VF curve re-evaluation 2)Add function hook to send temperature limit of GPU sensor 3)Call VFE event handler from PMU's event handle function Change-Id: I2e3577d3d895e97e6ad06e92f0f4827f9855d0b6 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1245393 (cherry picked from commit 1a5c6c32cdec73fb23735430f43577eda675e5af) Reviewed-on: http://git-master/r/1268060 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add device alarmsThomas Fleury2016-12-15
| | | | | | | | | | | | | | | | | | | Add event definitions for: - Clock alarm (target frequency not met) - Thermal alarm (temperature above threshold) - Power alarm (power above threshold) - GPU shut down Jira DNVGPU-186 Change-Id: I52edd44352ed0cba83033949272f41cc9e1c630f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1249342 (cherry picked from commit 67a6681aade241ff24982771778f7e2193d1cd7f) Reviewed-on: http://git-master/r/1267157 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support negative temperaturesThomas Fleury2016-12-15
| | | | | | | | | | | | | Jira DNVGPU-166 Change-Id: Id0561d49c64096ad5cbcd23bd371b49b2e0db57c Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1245557 (cherry picked from commit 2e0269c76fdda5c8e1a30ca7ef73a08ebe644f88) Reviewed-on: http://git-master/r/1267156 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: store last_freq in gk20a structDeepak Nibade2016-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_scale_target(), to check for duplicate freq requests we compare current frequency with devfreq->previous_freq But for very first request after boot, we have devfreq->previous_freq set to MIN freq And in case we evaluate new frew as MIN freq then we skip calling postscale() and scaling of EMC clock This results in keeping EMC at MAX value To fix this, add new variable last_freq in gk20a structure. Use this variable to store frequency value and to compare for duplicate requests Bug 200255163 Bug 200257544 Change-Id: Icfc57234c63f68cce8ccf8221237105272dad853 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1263747 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: read effective frequency from counterDavid Nieto2016-12-09
| | | | | | | | | | | | | | | JIRA DNVGPU-164 Adding export functions to gk20a and gk20a_clk structure Change-Id: Ia448f17a6c456139544c1d36a3e17ceec0edd2f6 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239465 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1268000 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: pmu version updateMahantesh Kumbar2016-12-09
| | | | | | | | | | | | | JIRA DNVGPU-71 Change-Id: I08668e17a258fe7c025c79ee2e00a0f4d7cb8a2d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1243834 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267999 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: get voltage, current, power and temperatureThomas Fleury2016-12-09
| | | | | | | | | | | | | | | | Add ioctls to retrieve voltage, current, power and temperature. Add flags in GPU characteristics to indicate if feature is supported. Jira DNVGPU-166 Change-Id: Idd5a767326c9d43630e8289ca7d2c27bb96a9f14 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1241862 Tested-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1267153
* nvgpu: gpu: arbiter for vf switch managementDavid Nieto2016-12-09
| | | | | | | | | | | | | | | | | | | JIRA DNVGPU-143 (1) Added conversion routines in ctrl_gk20a.c to do conversions between Hz and MHZ (2) Use new api to prevent corruption of requests is multiple threads on same session commit simultaneously Change-Id: I87875e593d2cc90647d5c4f60a4e293ed3ea6b83 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239460 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267152 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: add clocks control capabilityThomas Fleury2016-12-09
| | | | | | | | | | | | | | | Add NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS bit to allow user library to determine if GPU supports clock control ioctls. Jira DNVGPU-125 Change-Id: Ia09808ed36aa85a7c520039bb336888e2b467076 Signed-off-by: David Martine Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239379 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267154 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Use end of vidmem as bootstrap regionTerje Bergstrom2016-12-09
| | | | | | | | | | | | | | | | | Instead of hard coding bootstrap region, it should always be set to the last 256MB of vidmem. Bug 200244445 Change-Id: I91779d1bf861f4f23a0b646f70b1febbbc4581b5 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1242409 Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/1267124 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix timeout retry usage in mm_gk20a.cKonsta Holtta2016-12-09
| | | | | | | | | | | | | | | | | | | | | | | Loop conditions of timeout checking introduced in commit 21094783114b9314d57f412196544a34b3a40f4a ("gpu: nvgpu: Use timeout retry API in mm_gk20a.c") were flipped by accident, so each usage in a loop actually did not wait enough but ran only one iteration. Fix the conditions to loop as long as the timeout is NOT expired. Also restore l2 flush timeout to 10 ms from 1, which was done in commit 030ef82bdd474ef4261a2f40995b8db57857899e ("gpu: nvgpu: increase l2 flush timeout") but overwritten by the above "use timeout" commit. Bug 200260715 Change-Id: I0db16be79a1a27caa3d97fac9d4361582cc232e8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1268482 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 06:54:02 -0400