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* gpu: nvgpu: vgpu: Fix vgpu mm code build breakTerje Bergstrom2015-03-18
| | | | | | | | | | | | Some fields were moved to vm specific fields from global mm fields. Fix vgpu's mm code to follow that. Zero page is never allocated in vgpu, so don't free it. Change-Id: Ieabb33f1f004c9ffeeceabf61029b5bafc391889 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/559818 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: remove register from whitelistKirill Artamonov2015-03-18
| | | | | | | | | | | | | | | Userspace access to gr_pri_bes_crop_hww_esr removed on Tegra platform. Remove gr_pri_bes_crop_hww_esr register from gk20a whitelist. bug 1456562 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: Id9c3f85e39c970182283a0cdbb87ac5b6b83a534 Reviewed-on: http://git-master/r/553636 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cde: set err properly in oom conditionKonsta Holtta2015-03-18
| | | | | | | | | | | | When gk20a_gmmu_map runs out of memory, set the error code before returning early, so that caller knows about that cde load didn't succeed and wouldn't use the bad context. Change-Id: I1e166c78e39f07df941a29fc4e392a853d97a5c6 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/557273 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement 64k large page supportTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Implement support for 64kB large page size. Add an API to create an address space via IOCTL so that we can accept flags, and assign one flag for enabling 64kB large page size. Also adds APIs to set per-context large page size. This is possible only on Maxwell, so return error if caller tries to set large page size on Kepler. Default large page size is still 128kB. Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Common VM initializerTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | Merge initialization code from gk20a_init_system_vm(), gk20a_init_bar1_vm() and gk20a_vm_alloc_share() into gk20a_init_vm(). Remove redundant page size data, and move the page size fields to be VM specific. Bug 1558739 Bug 1560370 Change-Id: I4557d9e04d65ccb48fe1f2b116dd1bfa74cae98e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove unused symbolsTerje Bergstrom2015-03-18
| | | | | | | | | Remove unused symbols in platform file and gk20a.c. Bug 1558739 Change-Id: If160a75061ecb4ad9cbc4abfb9bc409457299738 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gk20a: Moved bind fecs to init_gr_supportMahantesh Kumbar2015-03-18
| | | | | | | | | | | | | | | -Moved bind fecs from work queue to init_gr_support. -It makes all CPU->FECS communication to happen before booting PMU, and after we boot PMU, only PMU talks to FECS. So it removes possibility to race between CPU and PMU talking to FECS. Bug 200032923 Change-Id: I01d6d7f61f5e3c0e788d9d77fcabe5a91fe86c84 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/559733
* gpu: nvgpu: gk20a: Fix non static symbolAmit Sharma2015-03-18
| | | | | | | | | | | | | Fixed sparse non static symbol warning by making the following symbol 'static': - to_gk20a_sync_pt - to_gk20a_timeline Bug 200032218 Change-Id: Ie0310116aa1500ae8e4838b8a9ad4943a61cfc24 Signed-off-by: Amit Sharma <amisharma@nvidia.com> Reviewed-on: http://git-master/r/552052 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Report error on failed mapSami Kiminki2015-03-18
| | | | | | | | | | | gk20a_vm_map_buffer() used to ignore silently map requests for non-dmabuf fd:s. Fix this by returning the error code from dma_buf_get(). Bug 1566862 Change-Id: If01b03f43b67b17d9fb997d914db871520f50c6e Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
* gpu: nvgpu: gm20b: write gpccs start only onceVijayakumar2015-03-18
| | | | | | | | | | | Writing start bit twice can confuse falcon and results in random behavior. Bug 200040021 Change-Id: I62eb8e4632ac4fc471d931155471084ee0f9d0a4 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: fix issue with rail gating ref countSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | gpu rail gating reference count is going wrong because "can_railgate" is set to false during probe(). For rail-gating to work no gpu re-work is needed and by default rail-gating is enabled with INT_MAX delay. Bug 200044987 Change-Id: I9367275cd18c34cb19a51193353585789ba44c03 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/556568 Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: send ELPG init cmd after GR is readyVijayakumar2015-03-18
| | | | | | | | | | | | bug 200040021 bug 200032923 Change-Id: I5aa7f4efb1b675e9a3faaf73a80452e55cded89e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Change-Id: Ic162902bd2f05abab9ebd37392ed56dc4c164ba8 Reviewed-on: http://git-master/r/539995 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: require mapped buffer be inside vaKonsta Holtta2015-03-18
| | | | | | | | | | When validating buffers to be mapped, check that the buffer end does not overflow over the virtual address node space. Bug 1562361 Change-Id: I3c78ec7380584ae55f1e6bf576f524abee846ddd Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: cde: CDE optimizationsJussi Rasanen2015-03-18
| | | | | | | | | | | | | | | | | -Change cde_buf to use writecombined cpu mapping. -Since reading writecombined cpu data is still slow, avoid reads in gk20a_replace_data by checking whether a patch overwrites a whole word. -Remove unused distinction between src and dst buffers in cde_convert. -Remove cde debug dump code as it causes a perf hit. Bug 1546619 Change-Id: Ibd45d9c3a3dd3936184c2a2a0ba29e919569b328 Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/553233 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Remove usage of KEPLER_C syncpt incrTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | Using KEPLER_C for doing sync point increment has side effects. It adds a SetObject method, which changes channel state that not all user space accounts for. Bug 1462255 Bug 1497928 Bug 1559462 Change-Id: I5c422ad8ca94fba15cad9bd232f7a10d94aa0973 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/554478 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: disable GK20A PMU supportHaley Teng2015-03-18
| | | | | | | | | | | | | | | | GK20A PMU is not supported in GPU client for virtualization. However, to make native case and virtualization case can share same defconfig and kernel image, we need to enable CONFIG_GK20A_PMU and CONFIG_GK20A_DEVFREQ in defconfig. This commit changes to detect if we should disable GK20A PMU support in run time. Bug 200041597 Change-Id: I292c647303ed57af6faa1c5671037ca27b48e31e Signed-off-by: Haley Teng <hteng@nvidia.com> Reviewed-on: http://git-master/r/553653 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu:gm20b: disable irqs when hs pmu executesVijayakumar2015-03-18
| | | | | | | | | | | | | bug 200040021 polling halt irq to check for hs bin completion keep irqs disabled to avoid executing irq handler Change-Id: Ic245d89580444dcbf1cf5ec34bfe0f8b0c5bbc0f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/554659 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Override GM20b RAM SVOP PDP fusesAlex Frid2015-03-18
| | | | | | | | | | | | | | | Override GM20b RAM SVOP PDP fuses with 0x2 setting during clock initialization. Bug 1550997 Change-Id: I9a873b892a2db4af384a9a7af4470562cdcb1572 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499554 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GM20b RAM SVOP PDP fuse registersAlex Frid2015-03-18
| | | | | | | | | | | | Bug 1550997 Change-Id: I25551fdcb9f7d43dc8631305b784aa9c04040139 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Improve error handing in fifoTerje Bergstrom2015-03-18
| | | | | | | | | When initializing fifo, we ignore several error conditions. Add checks for them. Change-Id: Id67f3ea51e3d4444b61a3be19553a5541b1d1e3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/553269
* gpu: nvgpu: dump falcon stats in mmu fault handlerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | If engine status is in context switch in the fifo mmu fault handler, dump falcon stats and gr stats for each engine. Bug 1544766 Change-Id: Idfa9772b7e67072941144ac3bdd73e791fdc2b23 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/553205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: fix build breakAingara Paramakuru2015-03-18
| | | | | | | | | | | | | Switch struct definitions to use nvgpu version instead of nvhost one. Bug 1509608 Change-Id: Id8c1b0c198536766f0399437bdf2c35c6a6bfe85 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/554027 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: calculate zcull_sm_num_rcp using tpc_countDavid Li2015-03-18
| | | | | | | | | | | | old value is for 1 SMs so on gm20b with 2 SMs it resulted in half zcull coverage bug 1553171 Change-Id: I269f9a333a059b2ef533672df63ccaa90b2d00c7 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/500517 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix gpu identification for 3demcSamuel Russell2015-03-18
| | | | | | | | | | | | | | Modify GPU detection in 3demc-bw-ratio to use the SOC Id. Bug 1364894 Change-Id: If52e8c5153e76b29d67d28c52303b095df2e8bf0 Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/542770 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add no-op stubs for vgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | Implement empty or -ENOSYS functions for vgpu if CONFIG_TEGRA_GR_VIRTUALIZATION is not enabled, and remove ifdefs around the calling code. Change-Id: Idc75c9bc486d661786bc222bd9e0380aa7766e78 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/552898 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: support new pmu ucode revisionVijayakumar2015-03-18
| | | | | | | | | | bug 200042729 Change-Id: Ic4b4fa4c25f4017a69355e7f03a3f25d4ce92cff Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552554 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not reset ctxsw & wait for fe_giTerje Bergstrom2015-03-18
| | | | | | | | | | | | | At this stage, ctxsw is always in reset state, because we're powering GPU up, or we have reset the whole GR partition. Remove the code to invoke a second reset. Fix waiting for FE idle. We should wait after each bundle, and break if any iteration fails. Change-Id: I0846f67c6d860a485dea62ff870deafe55a47365 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/552799
* gpu: nvgpu: Update GM20b GPCPLL NA mode settingsAlex Frid2015-03-18
| | | | | | | | | | | | | - Updated DFS_COEFF slope/intercept parameters - Specified VCO control gain - Increased safe DVFS margin to 10% Bug 1555318 Change-Id: I619704b7ba029d77ea1019a86003c3e8d80d04d8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552446 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Change quantize order in GPCPLL NA modeAlex Frid2015-03-18
| | | | | | | | | | | | When calculating fractional divider in GPCPLL NA mode quantize voltage before (used to do it after) applying DFS_COEFF, to follow h/w order. Bug 1555318 Change-Id: I37be2bc73cd1f849695b94acc4ff21caf26e8b97 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552741 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: add __must_check to gk20a_busyKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | The return value of gk20a_busy must be checked since it may not succeed in some cases. Add the __must_check attribute that generates a compiler warning for code that does not read the return value and fix all uses of the function to take error cases into account. Bug 200040921 Change-Id: Ibc2b119985fa230324c88026fe94fc5f1894fe4f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542552 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable aelpgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Adaptive Engine Level Power Gating power feature for gm20b. Bug 1552466 Change-Id: I2659f80a567699eff64307800710d4978d02adc1 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/501343 Reviewed-by: Mitch Luban <mluban@nvidia.com> Tested-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Update GM20b clock initializationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | - Removed unnecessary static "initialized" variable (sw_ready flag is protecting from multiple initializations, anyway). - Used max frequency at min voltage to set initial configuration of GPCPLL in both NA and non-NA mode. For backward compatibility made sure initial PLL output rate do not exceed 1/3 of VCO minimum. Bug 1555318 Change-Id: If970c27442ea1109d4503a322998a6a26159c345 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552370 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: vgpu: fix build breakAingara Paramakuru2015-03-18
| | | | | | | | | | | | | runlist_wq has been removed. Bug 1535380 Change-Id: I830037232d6767993dc88a79f540f89239b0334d Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/552567 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Expose PMU security mode in debugfsTerje Bergstrom2015-03-18
| | | | | | | | | Expose a debugfs entry pmu_security. It allows checking if PMU was booted in secure or non-secure mode. Change-Id: Iea584b696440779bee0900edccabd4e5b2997805 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/552456
* gpu: nvgpu: gm20b: fix dbg msg from secure pmuVijayakumar2015-03-18
| | | | | | | | | | dma params for dbg msgs not passed correctly Change-Id: Ic4ba2bf282b8c339a8c8f6fecd297394fd5771dd Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552073 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: create new nvgpu ioctl headerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | Move nvgpu ioctls from the many user space interface headers to a new single nvgpu.h header under include/uapi. No new code or replaced names are introduced; this change only moves the definitions and changes include directives accordingly. Bug 1434573 Change-Id: I4d02415148e437a4e3edad221e08785fac377e91 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542651 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename gpu ioctls and structs to nvgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | | | To help remove the nvhost dependency from nvgpu, rename ioctl defines and structures used by nvgpu such that nvhost is replaced by nvgpu. Duplicate some structures as needed. Update header guards and such accordingly. Change-Id: Ifc3a867713072bae70256502735583ab38381877 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542620 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Prepare for GPCPLL NA data integrationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | In preparation for GM20B GPCPLL NA data integration: - Added VCO control initialization code (no data, yet) - Replaced absolute safe margin with relative percentage (preliminary 8%) - Retrieved maximum safe frequency at minimum voltage from GPU DVFS table, instead of hard-coded macro (also fix the name of the limit: maximum instead of minimum) - Updated comments Bug 1555318 Change-Id: I49a7a90cc4bc29e181065ebd2cf9d214edae6465 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/542462 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: fix -EINVAL retval in ioctlsKonsta Holtta2015-03-18
| | | | | | | | | | | | Proper error number for invalid request number is EINVAL instead of EFAULT, so change it in ioctl calls. Change-Id: I8fddd34e012700550e9e30fe17ba7152b3a0417b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542563 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cde: check return values from busyKonsta Holtta2015-03-18
| | | | | | | | | | | check gk20a_busy return value in cde converter code paths. Bug 200040921 Change-Id: Ibad36df5877e325636a0a6ccc30c0d3d076ca941 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/540006
* gpu: nvgpu: cde: CDE swizzling optimizationsJussi Rasanen2015-03-18
| | | | | | | | | | | | | | | | | Change CDE swizzling shader kernel size to 8x8 to avoid waste with relatively small surfaces. Map compbit backing store and destination surface as cacheable. Clean up kernel size calculation. Bug 1546619 Change-Id: Ie97c019b4137d2f2230da6ba3034387b1ab1468a Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/501158 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Add option to enable GPCPLL NA modeAlex Frid2015-03-18
| | | | | | | | | | | | | | | Added configuration option to enable GM20b GPCPLL noise aware (NA) mode. In this mode PLL output frequency is automatically adjusted when GM20b voltage is fluctuating. NA mode is disabled by default. Bug 1555318 Change-Id: Ia9741fd02ddacaf4743e5397b729293fa5181f84 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/534079 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Change GPCPLL NA rate in flightAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL frequency change in NA mode outside of bypass. In this case the respective PLL DVFS detection settings are updated in flight. The implemented algorithm relies on characterization providing two frequency limits at the same voltage: max frequency on the F/V curve (Fmax@V) in NA mode with characterized DVFS coefficient, and safe frequency under the curve when DVFS coefficient is zero (Fsafe@V, which is effectively the same as Fmax@V in legacy/non-DVFS mode). Transition between two Fmax@V points on the curve includes: - Lowering frequency to Fsafe@V for the minimum V of the transition end-points - Setting DVFS coefficient to zero - Changing DVFS calibration point to the new voltage - Setting DVFS coefficient characterized for the new voltage - Setting final target frequency Note that voltage is changed by Tegra SoC DVFS before (when voltage increases), or after (whet voltage decreases) the above procedure. This commit kept NA mode disabled. Bug 1555318 Change-Id: Ib5620aaa113dc1caa69ecd402d9c6f68e39c472c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/501042 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Support GPCPLL dynamic ramp in NA modeAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL dynamic ramp in NA mode that requires ramping of both integer NDIV and fractional SDM_DIN controls. If NA mode is enabled, dynamic ramp is used only for transition to / from disabled state. PLL frequency in NA mode is still changed under bypass only. This commit kept NA mode disabled. Bug 1555318 Change-Id: I91f5722a485d1b66b6113aa9c35a2fe36c38ea80 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/500637 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GM20b GPCPLL NA mode basic supportAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | Added basic support for GM20b GPCPLL noise-aware(NA) mode. In this mode PLL internal DVFS mechanism is engaged, and output frequency is scaled with voltage automatically. The scaling coefficients in this commit are preliminary, pending characterization. If NA mode is enabled, any frequency change is done under PLL bypass, with no dynamic ramp allowed. This commit kept NA mode disabled. Bug 1555318 Change-Id: I8d96a10006155635797331bae522fb048d3dc4a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499488 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: require bound as before gpfifo submitKonsta Holtta2015-03-18
| | | | | | | | | | | | Channel gpfifo cannot be submitted if the channel has no vm, so add a check for it and bail out if no as is bound. Clean up other similar checks too. Change-Id: Ibb0fe08e44e34bbaaa00ebd02dce6cc4d93ca5d9 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/538887 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add debug events in open and ioctlKonsta Holtta2015-03-18
| | | | | | | | | | | | | Add debug events for measuring the duration of gk20a channel open and channel ioctl calls. Bug 200035111 Change-Id: Ib4837c745e73ee1690814d60bdca021821567153 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/538768 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gk20a: Unlock mutex upon queue full.Mahantesh Kumbar2015-03-18
| | | | | | | | | | | | | | Unlock mutex upon queue full then return -EAGAIN. Bug 1551294 Change-Id: I2a06a99028f98e6602a4cc27d15015bfe1db4eda Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/501235 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Tested-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix fence creation error checkKonsta Holtta2015-03-18
| | | | | | | | | | | | nvhost_sync_create_fence returns ERR_PTRs instead of NULLs on error; check for its errors with IS_ERR. Change-Id: I9752e0d8fa703b2872918b23721ae973be58bf35 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/533794 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Support 512 channels in gm20bTerje Bergstrom2015-03-18
| | | | | | | | | Retrieve channel count from gm20b specific header instead of the gk20a header. This increases channel count from 128 to 512. Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500623
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 04:45:57 -0500