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* gpu: nvgpu: use timeout API in ch poll workerKonsta Holtta2017-06-19
| | | | | | | | | | | | | Instead of using raw jiffies, use milliseconds and the nvgpu timeout API. The COND_WAIT API uses also just milliseconds. Jira NVGPU-83 Change-Id: I21b5e0880f0b6aa02856d7c207be97861e423b6b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1502999 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timeout retry API in xveKonsta Holtta2017-06-19
| | | | | | | | | | | | | | | Get rid of manual timeout tracking with jiffies in xve_gp106.c by using the timeout API instead. Jira NVGPU-83 Change-Id: Ida45539e05ac4de2a9d747170627c7104f27a544 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1502998 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: changed log level for defer_probeDebarshi Dutta2017-06-19
| | | | | | | | | | | | | | | If platform probe fails as a result of DEFER_PROBE, it should be reported as dev_info instead of dev_err. Bug 1926777 Change-Id: Iba4392abdd6089da9678695b8ee7f2c92bea1505 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: http://git-master/r/1492711 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
* gpu: nvgpu: exit pmu thread after bootKonsta Holtta2017-06-19
| | | | | | | | | | | | | | | When the pmu reaches PMU_STATE_STARTED, exit from the nvgpu_pg_init_task thread as it's no longer necessary. This prevents a possibly long wait on the signaling condition, which would make Linux think that the thread has been blocked and print a warning. Bug 200317814 Change-Id: I4104896867ee13eb9d53b1b19b659a7839adb73f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1501504 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mark thread stopped when it independently quitsKonsta Holtta2017-06-19
| | | | | | | | | | | | | | | | | | | | | | | It's technically possible for a thread to exit without first calling nvgpu_thread_stop() in another, so mark the thread exit status from the thread after it has finished instead of in nvgpu_thread_stop(). Do this by starting the thread as a proxy function which calls the actual thread function and then sets the flag. Also, add a new flag to actually signify the running state because the thread->task going null abruptly would break nvgpu_thread_stop(). This does not guarantee that the kernel thread itself has stopped, but the function which can be considered as an "nvgpu thread" will be. Change-Id: Ib911b02bd51342ddeb8e6b9533ef7943f2606d2d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1501571 Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: hal for timestamps correlationThomas Fleury2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | In order to perform timestamps correlation for FECS traces, we need to collect GPU / GPU timestamps samples. In virtualization case, it is possible for a guest to get GPU timestamps by using read_ptimer. However, if the CPU timestamp is read on guest side, and the GPU timestamp is read on vm-server side, then it introduces some latency that will create an artificial offset for GPU timestamps (~2 us in average). For better CPU / GPU timestamps correlation, Added a command to collect all timestamps on vm-server side. Bug 1900475 Change-Id: Idfdc6ae4c16c501dc5e00053a5b75932c55148d6 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1472447 (cherry picked from commit 56f56b5cd9d2e75cf7d2613b5e115bfebdbee0ce) Reviewed-on: http://git-master/r/1489183 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reorganize PMU perfmonMahantesh Kumbar2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | -Moved perfmon code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c" file -Moved below related methods perfmon init, start/stop sampling, load counter read/write/reset, perfmon event handler - prepend with nvgpu_ for perfmon global methods by replacing gk20a_ JURA NVGPU-56 JURA NVGPU-98 Change-Id: Idbcdf63ebd76da170e609cc401b320a42110cd7b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1501418 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>Deepak Nibade2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | Remove <soc/tegra/fuse.h> includes and include <nvgpu/fuse.h> header to remove direct dependency on platform specific header Use specific APIs like below to read/write fuses nvgpu_tegra_fuse_write_bypass() nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable() Remove old code which was compiled for kernel versions less than 4.4 since we support only k4.4 and greater versions now Jira NVGPU-75 Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: add APIs to export fuse offsetsDeepak Nibade2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add below new APIs in common/linux/fuse.c and export them from include/nvgpu/fuse.h to read/write specific tegra fuse offsets void nvgpu_tegra_fuse_write_bypass(u32 val); void nvgpu_tegra_fuse_write_access_sw(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val); int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val); int nvgpu_tegra_fuse_read_reserved_calib(u32 *val); These APIs are needed to remove nvgpu's direct dependency on platform specific <soc/tegra/fuse.h> header Remove below generic APIs since they are no longer needed : nvgpu_tegra_fuse_read() nvgpu_tegra_fuse_write() Jira NVGPU-75 Change-Id: I366e6a3382f0c392b2132f4d3a7e286306bb2ec2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497517 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: bring back tegra idle registrationKonsta Holtta2017-06-15
| | | | | | | | | | | | | | | | | | | | To make do_idle work when nvgpu is built as a module, reverse the order of call dependencies for do_idle. Don't provide visible gk20a_do_{idle,unidle}() functions for the kernel but instead call the kernel for registering and unregistering pointers to them when the driver loads and unloads. Refactor the internal __gk20a_do_{idle,unidle} functions to take a struct gk20a * instead of struct device *, and use the callback api for providing that g instead of retrieving the plat device from device tree. Bug 200290850 Change-Id: Ibef8b069302e547b298069cbb97734f461a10cc3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1493774 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: hold power ref for deterministic channelsKonsta Holtta2017-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support deterministic channels even with platforms where railgating is supported, have each deterministic-marked channel hold a power reference during their lifetime, and skip taking power refs for jobs in submit path for those. Previously, railgating blocked deterministic submits in general because of gk20a_busy()/gk20a_idle() calls in submit path possibly taking time and more significantly because the gpu may need turning on which takes a nondeterministic and long amount of time. As an exception, gk20a_do_idle() can still block deterministic submits until gk20a_do_unidle() is called. Add a rwsem to guard this. VPR resize needs do_idle, which conflicts with deterministic channels' requirement to keep the GPU on. This is documented in the ioctl header now. Make NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING always set in the gpu characteristics now that it's supported. The only thing left now blocking NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL is the sync framework. Make the channel debug dump show which channels are deterministic. Bug 200291300 Jira NVGPU-70 Change-Id: I47b6f3a8517cd6e4255f6ca2855e3dd912e4f5f3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1483038 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add prints for ioctl numbersSeema Khowala2017-06-14
| | | | | | | | | | | | ioctl function name and number are printed if gk20a_dbg_fn is enabled. This is good to have for debugging. Change-Id: I4d0f99affaba493a4c586559d699f86174e4c64d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1498750 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fixup formatting in VM codeAlex Waterman2017-06-13
| | | | | | | | | | | | Fixup a minor spacing issue in the VM code. Change-Id: Ia4aaa3cdd7cb63958870cebb51821bf640d56123 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1499446 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: moved pg out from pmu_gk20a.c/hMahantesh Kumbar2017-06-13
| | | | | | | | | | | | | | | | | | | - moved pg related code to pmu_pg.c under common/pmu folder PG state machine support methods PG ACK handlers AELPG methods PG enable/disable methods -prepended with nvgpu_ for elpg/aelpg global methods by replacing gk20a_ JIRA NVGPU-97 Change-Id: I2148a69ff86b5c5d43c521ff6e241db84afafd82 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1498363 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use hww_esr_reset field to reset hwww_esrSeema Khowala2017-06-13
| | | | | | | | | | | Use hww_esr_reset field to clear hww errors Change-Id: I4b5da20c8a4bcfe2dea357d3d2ebd53678673b48 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1500965 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add sked exception detection and handlingSeema Khowala2017-06-13
| | | | | | | | | | | | | Needed to detect and clear sked exception Bug 200315442 Change-Id: Ia85e8827e563addf7b9d0f95ef192379bb808638 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1500860 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU F/W supportMahantesh Kumbar2017-06-13
| | | | | | | | | | | | | | | | | | | | - Moved pmu f/w related support from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu_fw.c" file - Prepended with nvgpu_ for global functions & replaced wherever used - Moved below list related to PMU f/w init/remove, PMU version specific ops, non-secure ucode blob prepare, JIRA NVGPU-56 Change-Id: Ifdad8c560bd233e98728717d5868119e9d8e8d90 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480636 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: reorganize PMU FB alloc/freeMahantesh Kumbar2017-06-13
| | | | | | | | | | | | | | | | | | Moved PMU FB access related code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu.c" file - Prepended with nvgpu_ for global functions & replaced wherever used. JIRA NVGPU-56 JIRA NVGPU-94 Change-Id: I42bfd9d216e6b35672a9738f01302d954b32b69e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480551 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: reorganize PMU initMahantesh Kumbar2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | - Moved PMU init code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu.c" file - Moved below related methods SW/HW init, init msg handler, deinit/destroy, PMU state machine -Created HAL methods to read message queue tail & supported mutex count. -prepend with nvgpu_ for pmu init global mehtods JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: Iea9efc194fefa74fb5641d2b2f4633577d2c3a47 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480002 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: move TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE to constantsRichard Zhao2017-06-09
| | | | | | | | | | | | | | Also removed deprecated TEGRA_VGPU_ATTRIB_*, but leave a place holder in case someone wants to use this command in future. Jira VFND-3796 Change-Id: Ic36a59db238d276b0e3dd68a9d8ec5834a04333d Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1457497 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU IPCMahantesh Kumbar2017-06-09
| | | | | | | | | | | | | | | | | | | | - Moved PMU IPC related code to drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file, -Below is the list which are moved seq mutex queue cmd/msg post & process event handling NVGPU-56 Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1478167 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move error notifier free to Linux moduleTerje Bergstrom2017-06-08
| | | | | | | | | | | | | | | Freeing error notifier involves calling dma_buf API, which is Linux specific. Move the free to happen in Linux specific channel close path. JIRA NVGPU-65 Change-Id: Ifd8b31bb8c8af13975c34add00f51dd869cfd76a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1498583 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Update PMU firmware version.Deepak Goyal2017-06-08
| | | | | | | | | | | | | | | This patch also updates PMU cmdline args as required by updated firmware. GPUT19x-30 Change-Id: I44214007046081a44acc7284eb2854d0548a8da8 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1498188 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: use nvgpu specific nvhost APIsDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove use of linux specifix header files <linux/nvhost.h> and <linux/nvhost_ioctl.h> and use nvgpu specific header file <nvgpu/nvhost.h> instead This is needed to remove all Linux dependencies from nvgpu driver Replace all nvhost_*() calls by nvgpu_nvhost_*() calls from new nvgpu library Remove platform device pointer host1x_dev from struct gk20a and add struct nvgpu_nvhost_dev instead Jira NVGPU-29 Change-Id: Ia7af70602cfc16f9ccc380752538c05a9cbb8a67 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1489726 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: add nvhost abstraction filesDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | Add new abstraction file common/linux/nvhost.c for all nvhost APIs and operations and export them from header <nvgpu/nvhost.h> This file will be compiled only if config CONFIG_TEGRA_GK20A_NVHOST is set Define struct nvgpu_nvhost_dev in a separate private header nvhost_priv.h Jira NVGPU-29 Change-Id: I17e1f7836d4854feadff0c339bc093e78ba7f3eb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1489725 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Split non-stall interrupt handlingTerje Bergstrom2017-06-07
| | | | | | | | | | | | | | | | | | | | | | Split handling of stalling interrupt to Linux specific chip agnostic and OS independent chip specific parts. Linux specific chip independent part contains handler for ISR and passing the control to a bottom half worker. It uses the new MC HALs intr_nonstall (query interrupt status), intr_nonstall_pause (pause interrupts), intr_nonstall_resume (resume interrupts), and is_intr1_pending (query per-engine interrupt bit). MC HAL isr_nonstall is removed, because its work is now handled in chip independent code. JIRA NVGPU-26 Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497048 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add MC HAL is_intr1_pendingTerje Bergstrom2017-06-07
| | | | | | | | | | | | | | | Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit that is passed as parameter to is_intr1_pending. The API is passed contents of intr1 register and an engine number, and returns true if there's an interrupt pending for the engine. JIRA NVGPU-26 Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497870 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: implement chip specific fb cbc_initseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | Add function pointer in fb to add chip specific cbc init. GPUT19X-70 Change-Id: I12f73945d99498de965a671fd8e258b5c95bbabe Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1484524 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Separate GMMU mapping impl from mm_gk20a.cAlex Waterman2017-06-06
| | | | | | | | | | | | | | | Separate the non-chip specific GMMU mapping implementation code out of mm_gk20a.c. This puts all of the chip-agnostic code into common/mm/gmmu.c in preparation for rewriting it. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I6f7fdac3422703f5e80bb22ad304dc27bba4814d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1480228 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove extraneous VM init/deinit APIsAlex Waterman2017-06-06
| | | | | | | | | | | | | | | | | | | | Support only VM pointers and ref-counting for maintaining VMs. This dramatically reduces the complexity of the APIs, avoids the API abuse that has existed, and ensures that future VM usage is consistent with current usage. Also remove the combined VM free/instance block deletion. Any place where this was done is now replaced with an explict free of the instance block and a nvgpu_vm_put(). JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: Ib73e8d574ecc9abf6dad0b40a2c5795d6396cc8c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1480227 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Unify vm_init for vGPU and regular GPUAlex Waterman2017-06-06
| | | | | | | | | | | | | | | | | Unify the initialization routines for the vGPU and regular GPU paths. This helps avoid any further code divergence. This also assumes that the code running on the regular GPU essentially works for the vGPU. The only addition is that the regular GPU path calls an API in the vGPU code that sends the necessary RM server message. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I37af1993fd8b50f666ae27524d382cce49cf28f7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1480226 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix big_pages logic in nvgpu_vm_initAlex Waterman2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | Fix the way big_pages is handled in nvgpu_vm_init(). Prior to this patch big_pages could wind up being true even if disable_bigpages is set in the mm struct. Clearly this is wrong. The logic is now simplified a little bit and makes it so that if the disable_bigpages field is set then the resulting VM created by nvgpu_vm_init() has only one user area (no need for a second LP user area) and the big_pages field for the VM is set to false. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: If5dc7fcf3fa4e070f87295406f0afe414269b702 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1493318 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: split vidmem_is_vidmemKonsta Holtta2017-06-06
| | | | | | | | | | | | | | | | | | | | | As the vidmem_is_vidmem flag has got two separate meanings in one bit, split it in two bits into the enabled() API: Add NVGPU_MM_HONORS_APERTURE bit, which is the same as vidmem_is_vidmem with its original meaning, and use it to test which aperture bits to write to hardware. Add NVGPU_MM_UNIFIED_MEMORY bit, which has the opposite meaning: that the GPU shares the SoC memory. When this flag is false, the GPU has its own local video memory. Jira NVGPU-86 Change-Id: I2d0bed3b1ede5a712be99323d3035b154bb23c3a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1496080 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move clk_gm20b debugfs to Linux moduleDeepak Nibade2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move debugfs code from clk_gm20b.c to file in Linux module common/linux/debug_clk.c This file will be compiled only if CONFIG_DEBUG_FS is set Define below new HAL APIs for various clock operations which can be accessed from debug file init_debugfs() get_voltage() get_gpcclk_clock_counter() pll_reg_write() get_pll_debug_data() Export nvgpu_pl_to_div() and nvgpu_div_to_pl() so that these can be accessed from debug_clk.c Add new structure nvgpu_clk_pll_debug_data so that all required register values for debugging can be made available in debug_clk.c Add new API gm20b_get_gpc_pll_parms() so that statically defined variable can be accessed in debug_clk.c too Remove global variable dvfs_safe_max_freq and add it to struct clk_gk20a so that it can accessed from both clk_gm20b.c and debug_clk.c Jira NVGPU-62 Change-Id: I3ae70b40235e78141a686686930e1f178ad59453 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1488903 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix use of untrusted scalar valueDeepak Nibade2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | Kind value can be passed to API nvgpu_vm_map() from User space (through IOCTL NVGPU_AS_IOCTL_MAP_BUFFER_EX) But kind value is not checked for sane values before storing it in bfr.kind_v And then we use this kind value as array index in gk20a_kind_is_supported() which is incorrect Fix this by ensuring in nvgpu_vm_map() that the kind value is well within range Bug 200291879 Coverity id : 2567923 Coverity id : 2567924 Change-Id: Ic57395018727cbd2260c929581db256e427316c6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1496597 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove logically dead codeDeepak Nibade2017-06-06
| | | | | | | | | | | | | | | | | In nvgpu_vm_map(), variable "inserted" can never be true in error path Hence remove the logically dead code Bug 200291879 Coverity id : 2567920 Change-Id: I5428f7d52f1d4f815c04d90ea651668dd72ba985 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1495906 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: fix resource leakDeepak Nibade2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | We pass (struct device_attribute *) to gp10b_ecc_stat_create() and gr_gp10b_ecc_stat_create() and then assign a memory allocation to this pointer But since this pointer is local copy to function, static pointer variables are never set in gr_gp10b_create_sysfs() This also results in a resource leak since we never free the storage assigned to local variable Fix this by adding correct parameter (struct device_attribute **) so that the address of the allocation is returned to the caller correctly Bug 200291879 Coverity id : 2567934 Change-Id: I7ac79810d9e22a568ae3cd1a69eb3f59a8d356ac Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1495905 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: fix recursive include from clk.hDeepak Nibade2017-06-06
| | | | | | | | | | | | | | | | | | | | Fix recursion in header include sequence : gk20a.h -> clk.h -> gk20a.h by removing gk20a.h include from clk/clk.h Fix the compile time error by forward declaring struct gk20a Coverity id : 2567917 Bug 200291879 Change-Id: I8fc3a8787dae91ae1a070c63bae6550596734603 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1495904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: remove duplicate \n from log messagesStephen Warren2017-06-06
| | | | | | | | | | | | | | | | | | nvgpu_log/info/warn/err() internally add a \n to the end of the message. Hence, callers should not include a \n at the end of the message. Doing so results in duplicate \n being printed, which ends up creating empty log messages. Remove the duplicate \n from all err/warn messages. (This message was updated in parallel with the previous change to fix this particular issue) Bug 1928311 Change-Id: I789f8c4b4084539ac901ed0f6b815518900cee90 Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: http://git-master/r/1495020 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_cond in notifier wqTerje Bergstrom2017-06-05
| | | | | | | | | | | | | Change notifier wait queue to use nvgpu_cond instead of Linux wait queue. JIRA NVGPU-14 Change-Id: I197a0ef6c0a2331ca0dbb3480bdb89d45ba73020 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1469853 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: moved & renamed "struct pmu_gk20a"Mahantesh Kumbar2017-06-05
| | | | | | | | | | | | | | | | | | | - Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for engine specific countersDavid Nieto2017-06-04
| | | | | | | | | | | | | Add support for chip engine specific error counters JIRA: GPUT19X-82 Change-Id: I1b2686bd58c2d4e060a0a79c6b9e505811490a90 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1490824 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu : GPC MMU ECC supportDavid Nieto2017-06-04
| | | | | | | | | | | | | | Adding support for handling of GPC MMU errors JIRA: GPUT19X-112 Change-Id: Iadeef017587e5dce3698026eef4ad94676c3c02b Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1490771 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: chip specific L2 ECC error supportDavid Nieto2017-06-04
| | | | | | | | | | | | | Adding support for handling of chip specific ECC memory errors JIRA: GPUT19X-112 Change-Id: I1c04ac1d5233c332b300540eade1b73527c46ff7 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1489020 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: nvgpu_thread to handle PMU state changesMahantesh Kumbar2017-06-02
| | | | | | | | | | | | | | | | | | | | | | | | | - Replaced schedule_worker() with nvgpu_thread along with nvgpu_cond_wait() to handle PMU state machine changes during boot. - Added new state "PMU_STATE_EXIT" to exit PMU state machine loop & wait for the thread stop signal. - In gk20a_init_pmu_setup_sw() thread creates & starts thread execution to handle PMU state changes. - In pmu_destroy() thread post PMU_STATE_EXIT & waits for pending operation to complete before thread destroy. JIRA NVGPU-56 Change-Id: I951208bf88e82c281e3e678ddc603d58aec5ab10 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1487882 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move debugfs code to linux moduleDeepak Nibade2017-06-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all debugfs code is Linux specific, remove it from common code and move it to Linux module Debugfs code is now divided into below module specific files : common/linux/debug.c common/linux/debug_cde.c common/linux/debug_ce.c common/linux/debug_fifo.c common/linux/debug_gr.c common/linux/debug_mm.c common/linux/debug_allocator.c common/linux/debug_kmem.c common/linux/debug_pmu.c common/linux/debug_sched.c Add corresponding header files for above modules too And compile all of above files only if CONFIG_DEBUG_FS is set Some more details of the changes made - Move and rename gk20a/debug_gk20a.c to common/linux/debug.c - Move and rename gk20a/debug_gk20a.h to include/nvgpu/debug.h - Remove gm20b/debug_gm20b.c and gm20b/debug_gm20b.h and call gk20a_init_debug_ops() directly from gm20b_init_hal() - Update all debug APIs to receive struct gk20a as parameter instead of receiving struct device pointer - Update API gk20a_dmabuf_get_state() to receive struct gk20a pointer instead of struct device - Include <nvgpu/debug.h> explicitly in all files where debug operations are used - Remove "gk20a/platform_gk20a.h" include from HAL files which no longer need this include - Add new API gk20a_debug_deinit() to deinitialize debugfs and call it from gk20a_remove() - Move API gk20a_debug_dump_all_channel_status_ramfc() to gk20a/fifo_gk20a.c Jira NVGPU-62 Change-Id: I076975d3d7f669bdbe9212fa33d98529377feeb6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1488902 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: use nvgpu specific lock APIs in kmemDeepak Nibade2017-06-02
| | | | | | | | | | | | | | | | | Use lock/mutex APIs from nvgpu/lock.h instead of using Linux specific APIs in kmem.c This patch is needed in order to remove Linux dependency from nvgpu driver Jira NVGPU-62 Change-Id: Ic3484857bc2fa1917724681f68c1626c1235baea Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1492107 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: *gr_bind_fecs_elpg called only if can_elpg setSeema Khowala2017-06-01
| | | | | | | | | | | | | | | gk20a_init_gr_bind_fecs_elpg(g) should not be called if system does not support gpmu Bug 200306035 Change-Id: Ifdc3bb326993cd42bfa9aece06881c8426b83a8b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1486043 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pass right data to aelpg control callsVijayakumar2017-06-01
| | | | | | | | | | | | | | | | | | Fill aelpg controller id explicitly and use right structure within command union bug 1932265 Change-Id: Ie06bf8b1b124e67871dd1443e14a1080473a7ab1 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1493125 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Tested-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: Avoid NULL dereference of flcnMahantesh Kumbar2017-05-31
| | | | | | | | | | | | | | | | | | | | | | | | -issue: flcn pointer in nvgpu_flcn_sw_init() will be NULL in default case of switch, and that results in NULL pointer dereference on flcn->flcn_id. -Fix: Used flcn_id parameter to print falcon id in default case. Coverity ID: 2514311 Coverity ID: 2514313 Bug 200291879 Change-Id: I7008817c22cdf8d9d9027cc1b724e2424b4a3d8e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1491694 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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