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* gpu: nvgpu: fix memory leak of dbg_sessionDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | In gk20a_dbg_gpu_dev_release() (when we close nvhost-dgb-gpu sysfs), we return from function if there is no channel bound to dbg_session without freeing the dbg_session memory. If there is no channel bound then do not call dbg_unbind_channel_gk20a() and then free dbg_session memory always. Bug 200010382 Change-Id: I90dd2ed3cd72fbc5d429799660daf2a09b974fda Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/419306 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Rewrite PMU boot-up sequenceTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Rewrite PMU boot sequence as a state machine. At PMU power-up send initial messages, and reset state machine. At each reply from PMU, do the next stage of PMU boot and set state. As now PMU and FECS boot are independent, we need to ensure engine idle before saving ZBC. Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410205
* gpu: nvgpu: Set ch error before channel disableTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | | | | In error case we first disabled the channel, and reset sync point to max. After this we set channel error state. This causes a race if channel is closed between setting sync point and setting channel state. Rearrange the code so that error state is set first, and only then channel is disabled. Bug 1519646 Change-Id: I20550f6a2708f892b6ba4ee714e90bdecdd128ad Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/418948 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: Reload ZBC values on rail gate exitTerje Bergstrom2015-03-18
| | | | | | | | | | | When exiting rail gate, we reloaded default ZBC values. The correct behavior is to reload the values. Bug 1447255 Change-Id: I7aad3586dda91a91a3629062a27001af281b955e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/418346
* gpu: nvgpu: On FECS error, dump ARB statusTerje Bergstrom2015-03-18
| | | | | | | | On FECS arbiter timeout, dump ARB status. Change-Id: I4f8c4d38c99e35ce751172a8695e950f0ce594c8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/417753
* gpu: nvgpu: update gpmu supported versionsSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Updated gmpu ucode versions supported for gm20b. Bug 1514021 Change-Id: If9cbde60449f5cc2b9c39c36ab5c79985d320bf8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/418479 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: fix compression sharingKevin Huang2015-03-18
| | | | | | | | | | | | | | | | For GM20B alone, the LTC count is already accounted for the HW logic for the CBC base calculation from the postDivide address. So SW doesn't have to explicity divide it by the LTC count in the postDivide address calculation. Bug 1477079 Change-Id: I558bbe66bbcfb7edfa21210d0dc22c6170149260 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/414264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fault engines on PBDMA errorTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | On PBDMA error even though the engine might not be wedged, we need to kick the channel out of engine. Add that logic. Also when channel is not in engine, we need to remove it from runlist. Bug 1498688 Change-Id: I5939feb41d0a90635ba313b265c7e3b5d3f48622 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/417682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Remove extraneous FB flush callsTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | gk20a_mm_fb_flush() invoked G_ELPG_FLUSH and FB_FLUSH. Remove the invokation of G_ELPG_FLUSH. Replace calls to gk20a_mm_fb_flush() with gk20a_mm_l2_flush() when appropriate. Bug 1421824 Change-Id: I02af4bdc3b7bd26d0f6a8d610f70349269775a36 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/408210 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: select NETA for gm20bSeshendra Gadagottu2015-03-18
| | | | | | | | | | Bug 1514021 Change-Id: I5bf942245a42881a418eb9e18c148287b6901ca0 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/415531 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Create trace events lastDan Willemsen2015-03-18
| | | | | | | Otherwise other trace event headers included may also be created, which leads to duplicate definition issues in the 3.14 kernel. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
* gpu: nvgpu: add support to Maxwell sparse textureKevin Huang2015-03-18
| | | | | | | Bug 1442531 Change-Id: Ie927cca905b2ea9811417e7a1fdfdf9d48f015e2 Signed-off-by: Kevin Huang <kevinh@nvidia.com>
* gpu: nvgpu: add generic api for sparse memoryKevin Huang2015-03-18
| | | | | | | Bug 1442531 Change-Id: I97408b54e27f5ed6411792e73f079a6f86cbe5f6 Signed-off-by: Kevin Huang <kevinh@nvidia.com>
* gpu: nvgpu: implement mapping for sparse allocationKirill Artamonov2015-03-18
| | | | | | | | | | | | | | | | Implement support for partial buffer mappings. Whitelist gr_pri_bes_crop_hww_esr accessed by fec during sparse texture initialization. bug 1456562 bug 1369014 bug 1361532 Change-Id: Ib0d1ec6438257ac14b40c8466b37856b67e7e34d Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/375012 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Handle PBDMA errorsTerje Bergstrom2015-03-18
| | | | | | | | | Add handling for PBDMA errors. Bug 1498688 Change-Id: Iff391110db1c270c05c76e6a14b7c666da8e3751 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add is_railgated() callbackDeepak Nibade2015-03-18
| | | | | | | | | | | Add is_railgated() platform callback to check status of gk20a power rail Bug 1376916 Bug 1487804 Change-Id: Ia0d909210dc409ab684eb6f20528b81500aecd5c Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: sysfs to put gpu into idleDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | - Add a sysfs "force_idle" to forcibly idle the GPU - read on this sysfs will return the current status 0 : not in idle (running) 1 : in forced idle state "echo 1 > force_idle" will force the gpu into idle "echo 0 > force_idle" will cause the gpu to resume Bug 1376916 Bug 1487804 Change-Id: I48dfd52e0d14561220bc4baea0776d1bdfaa7ea5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: add railgate check in do_idle()Deepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | In gk20a_do_idle(), check gk20a rail status before returning. If rail is off, then only return success otherwise return failure Bug 1376916 Bug 1487804 Change-Id: I6280bf06c686b8baa4d6f49e90f47148411c3e02 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/415281 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Support sync framework with semaphoresLauri Peltonen2015-03-18
| | | | | | | | | | | | | Add sync_gk20a.c/h that support creating Android sync fence fd's from gk20a semaphores. Bug 1445450 Change-Id: I42272996721ceec38ba5510eae6770720bc9dd10 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/374843 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement ELPG flush for gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | ELPG flush is initiated from a common broadcast register, but must be waited on via per-L2 registers. Split gk20a and gm20b versions of the flush. Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/401545 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Initialize FECS explicitly on recoveryTerje Bergstrom2015-03-18
| | | | | | | | | Instead of calling second phase of PMU boot sequence, initialize FECS directly. Change-Id: I7f9de0c5ec42049033839d244979f3f3daabf317 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410204
* gpu: nvgpu: Add gm20b fecs/gpccs bootloader supportTerje Bergstrom2015-03-18
| | | | | | | | | Add support for booting FECS and GPCCS via faster bootloader method. We leave this disabled until the bootloader binaries are checked in. Change-Id: I39df5d116f7a33486407518c743638b01923970d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/413005
* gpu: nvgpu: Remove deferred ELPG enableTerje Bergstrom2015-03-18
| | | | | | | | | | | Prevent the disable ELPG routine from calling deferred re enablement of ELPG. Remove code related to deferred ELPG enable.. Change-Id: I9401e6e0f26a4e332e50eb38439e2ef6fcb4225d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410203 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Add PMU sent/recvd messages to dbg logTerje Bergstrom2015-03-18
| | | | | | | | | Add debug log entries for received and sent PMU messages. Change-Id: I94cecca76257d74785c13f1c5f97a7233361019f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410202 Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: gk20a: add do_{idle()/unidle()} APIsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | Add below two new APIs for gk20a : 1) gk20a_do_idle() this API will force GPU to idle and railgate 2) gk20a_do_unidle() this API will unblock all the tasks blocked by do_idle() Bug 1487804 Change-Id: Ic5e7f2d19fb8d35f43666d0e309dde3022349d92 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/412061 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: add busy lockDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | - add rw_semaphore busy_lock for gpu busy() path - take read lock on busy_lock inside gk20a_busy() so that all usual requests can execute simultaneously - write lock can be taken when we need to block all of the gk20a_busy() calls Bug 1487804 Change-Id: I1b162b38bce9621723d3e45280c6076816cf771a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/412060 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: export wait_channel_idle()Deepak Nibade2015-03-18
| | | | | | | | | | | | | | - Export gk20a_wait_channel_idle() function from channel_gk20a.h - also, return error -EBUSY from this function when channel is found to be not idle Bug 1487804 Change-Id: Ia7425e9b1332260ee9a53dca55ab07541f2755a9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/412059 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: When rail gating, flush only onceTerje Bergstrom2015-03-18
| | | | | | | | | | When rail gating invoke G_ELPG_FLUSH only once. Bug 1421824 Change-Id: Ibde0e32b212e3b030e69a9cb837c87789887aabb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/408209
* gpu: nvgpu: Allow suppressing WFI on submitTerje Bergstrom2015-03-18
| | | | | | | | | | | Allow suppressing WFI when submitting work and requesting a fence back. Bug 1491545 Change-Id: Ic3d061bb4f116cf7ea68dbd6a1b2ace9f11d0ab5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/390457
* gpu: nvgpu: Use old ctxsw boot method on gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Boot FECS/GPCCS with old method on gm20b. We don't yet have bootloader for it. Change-Id: I09046960cd86b0402d3ea2cd8e4c92597766fa10 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/412604 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Add gk20a semaphore APIsLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add semaphore_gk20a.c/h that implement a new semaphore management API for the gk20a driver. The API introduces two entities, 'semaphore pools' and 'semaphores'. Semaphore pools are memory areas dedicated for hosting one or more semaphores. Typically, one pool equals one 4K page. A semaphore pool is always mapped to the kernel memory, and it can be mapped and unmapped to gpu address spaces using gk20a_semaphore_pool_map/unmap. Semaphores are backed by 16 bytes of memory allocated from a semaphore pool. The value of a semaphore can be 0=acuired or 1=released. When allocated, the semaphores are initialized to the acquired state. They can be released, or their releasing can be waited for by the CPU or GPU. Semaphores are intended to be used only once, and after they are released they should be freed so that the slot within the semaphore pool can be reused. However GPU jobs must take references to the semaphores that they use (similarly as they take references on memory buffers that they use) so that the semaphore backing memory is not reused too soon. Bug 1450122 Bug 1445450 Change-Id: I3fd35f34ca55035decc3e06a9c0ede20c1d48db9 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/374842 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: fix syncpt names for gk20aDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | nvhost_get_syncpt_host_managed() creates syncpt name based on platform_device pointer passed to it Passing host1x's pointer to this API results in setting gk20a syncpt names as "host1x_0" which is conflicting Hence to restore this pass gk20a's device pointer which gives syncpt names as "gk20a.0_0" Also, add a syncpt check for sycnpt received. Bug 1305024 Change-Id: I4ff96c7c9ebff2dca385c5787a85b4a9451b9514 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/410121 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Prune redundant cache maintenanceTerje Bergstrom2015-03-18
| | | | | | | | | | | | Remove redundant cache maintenance operations. Instance blocks and graphics context buffers are uncached, so they do not need any cache maintenance. Bug 1421824 Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406948
* gpu: nvgpu: Always initialize system vmTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | PMU, FECS and GPCCS use the same address space. We used to initialize the address space only if PMU is enabled. Create the system address space always. FECS and GPCCS used to have slower bit bang and faster DMA method for loading ucode. Slower method is needed when FECS and GPCCS do not have an address space. Remove the slower method as not anymore needed. Change-Id: I155619741ecc36aa6bf13a9c1ccb03c7c1330f0a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406771
* gpu: nvgpu: gk20a: free syncpt if last submit is completeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | In channel_update(), we detect if channel is idle and if it is idle then we free the syncpt. We do not free the syncpt if WFI is scheduled on some other path. Instead of checking for WFI, we can check if last submit is complete or not (it can be WFI as well) and if last submit is complete then we can free the syncpt. Locking mechanism using submit lock will take care that syncpt is kept alive until last submit or WFI completes Bug 1305024 Change-Id: Ieafb82e1f924a01236ca73ed151eb03e88729835 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/405201 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not realloc perfmon sample bufferTerje Bergstrom2015-03-18
| | | | | | | | | | | | Allocate perfmon sample buffer only once. Bug 1512840 Change-Id: I3f2a62b0fa28e6ba984ae3068a1d56ba461a0c29 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/408180 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
* gpu: nvgpu: Register as subdomain of host1xTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Add gk20a as a sub power domain of host1x. This enforces keeping host1x on when using gk20a. Bug 200003112 Change-Id: I08db595bc7b819d86d33fb98af0d8fb4de369463 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/407006 (cherry picked from commit 009812b3e510518740e9c7e89b8b8b80439fe26a) Reviewed-on: http://git-master/r/408013 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: add ltc isrKevin Huang2015-03-18
| | | | | | | | | | Bug 1507804 Change-Id: Ic58e21f4d995cf4f4fc7bb5fc6ec84a6c4d25d46 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403214 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: halize ltc isrKevin Huang2015-03-18
| | | | | | | | | | Bug 1507804 Change-Id: I3cca0e83dbf911c94422f8bb0b2df675a170b990 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403213 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: Keep host1x on when GPU on"Matt Pedro2015-03-18
| | | | | | | | | | | This reverts commit 20d48a759b032116e3092e1df76518065da59879. Change-Id: I93718a314b70ee9284a83ca69964883e670ad78d Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/407969 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not clear PMU state on rail gateTerje Bergstrom2015-03-18
| | | | | | | | | When rail gating, we cleared all PMU status. Clear only the relevant fields. Change-Id: I5b4e8d74339aae6f1c6b945f45b8378bb563e8be Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406843
* gpu: nvgpu: Keep host1x on when GPU onTerje Bergstrom2015-03-18
| | | | | | | | | Remove the path for turning on only gk20a. Always when turning on hardware, turn both host1x and GPU on. Change-Id: I5f972a487d3348bf2254bdb0fadb42ca600a559e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406405
* gpu: nvgpu: Fixes to static offset mappingsArto Merilainen2015-03-18
| | | | | | | | | | | | | | This patch addresses two issues in fixes offset mappings: - VA unmapping did not use lists safely. This caused an application hang if the application did not free all (fixed offset) buffers before quiting. - GPU was not powered closing AS node. If the address space had areas that were not freed, the driver tried to access hw without powering it up first. Change-Id: Ida526d222ea4e03b8d765eca16574ddc1823e60d Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/405872 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Generic platformArto Merilainen2015-03-18
| | | | | | | | | | | | | This patch adds minimal t124 generic platform configuration to platform_gk20a_generic.c to allow testing the minimal configuration. Bug 1434573 Change-Id: I1a3f00e14661023c8ff77d7576ba70cf98a95db5 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/381427 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fall-back to generic platformArto Merilainen2015-03-18
| | | | | | | | | | | | | | | | | Currently the generic platform is used only if the device tree defines that we have a generic platform available, however, the generic platform is fully compatible with the gk20a we have in tegra. This patch modifies the definitions so that we use generic platform also for tegra - even if if tegra configuration option is not enabled. Bug 1434573 Change-Id: Ib35ce0ab935d27764e960bf4d74a5016ae047a1f Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/396867 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: Control powergating on regopsSandarbh Jain2015-03-18
| | | | | | | | | | | | | | | Enable/disable powergating around regops so that the user need not call the powergating IOCTLs with the regops IOCTL. If the user does call the powergating IOCTL then the ref-counting will ensure the correct behavior. Bug 1451949 Change-Id: I1746f7d7cd1d2c0c497c213939df44a59d5d2834 Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/395131 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Create sysfs symlinksArto Merilainen2015-03-18
| | | | | | | | | | | | | | | gk20a is going to be moved under platform bus, however, the sysfs interface should remain stable over the transition period. This patch adds a symlink to keep current interfaces stable. Bug 1311528 Bug 1434573 Change-Id: I951000f4b25285ff96e93eb726342d5b76cc84f1 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/396926 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Get host1x device from DTSArto Merilainen2015-03-18
| | | | | | | | | | | | | | | Currently the gpu driver assumes that the GPU is a child of host1x. This is an invalid assumption and therefore we need to get the host1x device from device tree based on nvidia,host1x property. Bug 1311528 Bug 1434573 Change-Id: I097e39369aaa15ab6652cd23f353f88f7c2b9c48 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/395664 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable timeout if not on siliconTerje Bergstrom2015-03-18
| | | | | | | | Change-Id: I0add505d4f5c4b136f9f0228adbdc9aba960fcba Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/404276 Reviewed-by: Antoine Chauveau <achauveau@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Add support for SMSKED kindTerje Bergstrom2015-03-18
| | | | | | | | | | | Bug 1470957 Change-Id: Ief7c8970dafcc386a3a954593d4bb3a53be1b2a0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/404261 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 14:39:08 -0500