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* gpu: nvgpu: tegra: Fix EMC frequency scalingAlex Frid2017-05-12
| | | | | | | | | | | | | | Before this commit call to EMC BWMGR in postscale procedure was skipped when GPU rail is ON (= GPU is running). It should be the other way around - call should be skipped when GPU is rail-gated. Bug 200267304 Change-Id: Id4da84b3d0ed0606017cc53a58e2917d486fa13e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1479769 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_cond for channel refcountTerje Bergstrom2017-05-12
| | | | | | | | | | | | | | | Use nvgpu_cond for waiting for all channel accesses to finalize before closing a channel, and for signalling for the same event. JIRA NVGPU-14 Change-Id: Ifac14ad9afe5c44d4443b4a4a94a4d0ad2ea7053 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1469764 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Abstract condition variableTerje Bergstrom2017-05-12
| | | | | | | | | | | | | Add implementation for an abstracted condition variable. Implement it using wait queue in Linux. JIRA NVGPU-14 Change-Id: I211c590cca940ffc31d6c52141689f23f231e7da Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1469763 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_thread for VGPU interruptsTerje Bergstrom2017-05-12
| | | | | | | | | | | | | | | Use nvgpu_thread for launching the thread for polling VGPU interrupts. JIRA NVGPU-14 Change-Id: I7114336bb37c407ee7365c4442e1826d80575771 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1469650 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove TCF & gk20a clock supportTerje Bergstrom2017-05-12
| | | | | | | | | | | | Remove support for legacy Tegra Clock Framework. gk20a clocks were implemented only for TCF, so delete that at the same time, too. Change-Id: Ia46254f5113aa3ec392bf38b33d288a55b2fb475 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1480213 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Introduce priv ring HAL and define ISRTerje Bergstrom2017-05-12
| | | | | | | | | | | | | | | Introduce a priv ring HAL and define ISR as the only function in it. Introduce a gp10b version of the ISR that writes error message to UART for every priv ring error, and leave the old chips with silent error handling. Bug 1846641 Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473696 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu: add check before enabling elpg.Deepak Goyal2017-05-12
| | | | | | | | | | | | Do not enable/disable elpg if platform->can_elpg is false. Bug 1870556 Change-Id: I82d1fc4efdccc518827a6150fd3c17f6112e2f4a Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1465816 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix resource leak in error pathDeepak Nibade2017-05-12
| | | | | | | | | | | | | | | | | | | In nvgpu_request_firmware(), if fw->data is NULL, we jump to label "err" and leak the storage pointed by linux_fw Fix this by releasing firmware in error path if fw->data is NULL Coverity id : 2513066 Bug 200291879 Change-Id: Ieb5e22137cebb4cd02415b805941969b95a38668 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1479884 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: fix recursion in included headers from boardobjgrp_e32.hDeepak Nibade2017-05-12
| | | | | | | | | | | | | | | | | | | | | We have this recursion in headers as pointed by Coverity gk20a/gk20a.h" includes itself: gk20a.h -> clk.h -> clk_vin.h -> boardobjgrp_e32.h -> gk20a.h Fix this by removing gk20a.h header from boardobjgrp_e32.h Also remove unused header gk20a.h from boardobjgrp_e255.h too Coverity id : 2513065 Bug 200291879 Change-Id: I4bee04f064dfb8b02026de9b5a07429b1f48d0a0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1479883 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: pmu: export elpg stats function.Deepak Goyal2017-05-12
| | | | | | | | | | | | | | | | | gp106_pmu_elpg_statistics() can be re-used by other chips. The function is changed to non-static & exposed outside gp106 scope. Bug 200305607 Change-Id: I4ba660509ce816bebc59855227a8d409ed8f84f8 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1476005 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Fix mem-API usage bug in ACRAlex Waterman2017-05-11
| | | | | | | | | | | | | | | | The __nvgpu_mem_create_from_pages() API takes a number of pages from which to create a buffer. In the ACR code only 1 page was passed. If the WPR region (what the ACR code creates an nvgpu_mem from) is larger than 1 page then the current code will truncate that region down to only a single page. Change-Id: I11833619c4f35a076f72071cc5b98ae2d192c5d0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1477672 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: change debugfs to use g->ch_wdt_timeout_msRichard Zhao2017-05-11
| | | | | | | | | | | | Since ch_wdt_timeout_ms was moved to gk20a, set debugfs accordingly. Jira VFND-3796 Change-Id: Id0c69bf5c15fc4efe672348273b24f23fb52aa29 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1478679 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move secure_alloc to struct gk20aTerje Bergstrom2017-05-11
| | | | | | | | | | | | | | | | | | Move the function pointer for VPR page allocation to struct gk20a and use it from there. At the same time remove secure_page_alloc pointer and add a direct call to it in probe. Move platform_tegra.h as tegra/linux/platform_gk20a_tegra.h, as it's only declaring functions defined in platform_gk20a_tegra.c to other files in the same directory. JIRA NVGPU-16 Change-Id: I19ac9ee0b2f6734203ae32a1f51d67fd51aced9f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473706 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Separate GMMU out of mm_gk20a.cAlex Waterman2017-05-11
| | | | | | | | | | | | | | | Begin moving (and renaming) the GMMU code into common/mm/gmmu.c. This block of code will be responsible for handling the platform/OS independent GMMU operations. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: Ide761bab75e5d84be3dcb977c4842ae4b3a7c1b3 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1464083 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: init ch_wdt_timeout_ms with platfrom valueRichard Zhao2017-05-10
| | | | | | | | | | | | | | Since ch_wdt_timeout_ms was moved to struct gk20a, vgpu needs to init it with default platform value. Jira VFND-3796 Change-Id: I61aca06989ae6b9ad5b3a264ce21d885ca769349 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1478670 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Bump CBC clean timeoutTerje Bergstrom2017-05-10
| | | | | | | | | | | | | | CBC clean timeout is set to 1ms. We're seeing longer times taken in 3dtex_deep_image, so bump the timeout significantly. Change-Id: I16febbe663f130236c455d169c6eab47e4f73b52 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1478334 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: changes related to preemptionseshendra Gadagottu2017-05-10
| | | | | | | | | | | | | | Added function pointers to check chip specific valid gfx class and compute class. Also added function pointer to update ctx header with preemption buffer pointers. Bug 200292090 Change-Id: I8119ee082e2abb67186a8ac07088f8db7f410ba1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1293502 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: create t18x debugfs nodesseshendra Gadagottu2017-05-10
| | | | | | | | | | | | | | | | Modifed code to create debugfs nodes correctly by moving relevant code from gp10b_tegra_probe() to gk20a_debug_init(). Bug 200292090 Change-Id: Ib5d0a57d8b600cd30dc2a37794d8208b5c57ccfa Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1476484 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix error for static code analysisVijayakumar2017-05-05
| | | | | | | | | | | | | | | | mark functions local to the file as static fixing errors in volt and flcn modules. Bug 200299572 Change-Id: Ibacbd83649fee3066a90694a3df90bb909b24aa5 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1475357 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: expose deterministic submit supportKonsta Holtta2017-05-05
| | | | | | | | | | | | | | | | | | | | | | | | | Add these bits in the gpu characteristics flags: NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING - fast submits with no in-kernel job tracking are supported. NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL - deterministic submits also with job tracking and num_inflight_jobs set are supported. Either of these may get disabled if the particular channel or submit still requires features that block these. Make gk20a_channel_sync_needs_sync_framework() take a gk20a pointer instead of a channel pointer so that it can be called without a channel. It does not need any per-channel data. Bug 200291300 Change-Id: I5f82510b6d39b53bcf6f1006dd83bdd9053963a0 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1456845 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add flag gk20a->is_virtualTerje Bergstrom2017-05-04
| | | | | | | | | | | | | Instead of calling gk20a_gpu_is_virtual() which requires struct device pointer fill in flag gk20a->is_virtual and use that. JIRA NVGPU-16 Change-Id: I24382c041ee69940c703ca1ea7f5c667c5731cd1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473707 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_thread for channel workerTerje Bergstrom2017-05-04
| | | | | | | | | | | | Use nvgpu_thread for channel worker. JIRA NVGPU-14 Change-Id: Idcb93d3096de06a1569dc3ea69890745b5805d67 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1472870 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
* gpu: nvgpu: Abstract threadsTerje Bergstrom2017-05-04
| | | | | | | | | | | | Add abstraction for threads. Implement them using kthreads in Linux kernel. JIRA NVGPU-14 Change-Id: I26996d844db6bdc4b5e6f3230514a1dadb3fb07c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1469636 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: zcull settings during golden ctx loadseshendra Gadagottu2017-05-03
| | | | | | | | | | | | Don't configure zcull setting during golden context loading. Zcull setting will be configured through explicit API. Change-Id: I648aea8a8db9132fc81d61dbbff46edf7bfca6d7 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1474021 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: fix sparse warningseshendra Gadagottu2017-05-03
| | | | | | | | | | | | | | | | | Fixed following sparse warning by including relevant header: $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/therm_gp10b.c:127:6: warning: symbol 'gp10b_init_therm_ops' was not declared. Should it be static? Bug 200299572 Change-Id: I2caff721e98739f0c5978cca54d374cd959ac94a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1474004 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Access ptimer_src_freq from struct gk20aTerje Bergstrom2017-05-03
| | | | | | | | | | | | | Fix the last place where ptimer_src_freq is accessed directly from platform structure. JIRA NVGPU-16 Change-Id: I41b924779e1e639bf585cd96cb8c11de6eeb18bb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473704 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Program CE clock gating list after resetTerje Bergstrom2017-05-03
| | | | | | | | | | | | | | | Clock gating list for CE was programmed at GR init, but at that time CE has not yet been brought out of reset. This causes a priv ring error and the clock gating setting does not take place. Move programming of CE clock gating list to CE initialization. Bug 1846641 Change-Id: Ibc9fe2487408358304f80cd679d3b1ecac7cebe8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473301 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: Prune clock gating listTerje Bergstrom2017-05-03
| | | | | | | | | | | | | | Clock gating list contains a register which does not exist on gm20b. Remove it from the list. Bug 1846641 Change-Id: Ifb6f5c46482bcaad626bc875e9858d486d3dfa1c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473223 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: Move ch_wdt_timeout to gk20aTerje Bergstrom2017-05-03
| | | | | | | | | | | | | Copy watchdog timeout from platform structure to gk20a and use it from gk20a. JIRA NVGPU-16 Change-Id: Iab70253a7f0e1d28f2e3209285b3f4c476ce9279 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473705 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix KASAN slab-out-of-bounds errorDavid Pu2017-05-03
| | | | | | | | | | | | | | | | | | | | | | | KASAN reports below slab-out-of-bounds error when accessing gr->map_tiles since gr->map_tiles is allocated with wrong(small) size. fixing it by passing correct size to nvgpu_kzalloc. BUG: KASAN: slab-out-of-bounds in gr_gk20a_init_map_tiles+0x6f0/0x7b0 ... .... BUG: KASAN: slab-out-of-bounds in gr_gk20a_zcull_init_hw+0x184/0x848 ... ... BUG: KASAN: slab-out-of-bounds in gr_gk20a_setup_rop_mapping+0x108/0x1740 ... ... BUG: KASAN: slab-out-of-bounds in gr_gk20a_setup_rop_mapping+0x108/0x1740 ... Bug 1918671 Change-Id: I667ac80b20a3d8539ed3eaae6e0f98e91f917819 Signed-off-by: David Pu <dpu@nvidia.com> Reviewed-on: http://git-master/r/1472491 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: init interface layer support for PMU falconMahantesh Kumbar2017-05-03
| | | | | | | | | Change-Id: I210267265fa38777115d5b49cc8f78f2599e3f9e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1469458 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: falcon controller HAL initMahantesh Kumbar2017-05-03
| | | | | | | | | | | | | - Assign base address for falcon based on falcon id. - Init mutex for falcon - Init ops with NULL Change-Id: I9efee5c2b15106c7dfc6e55c996f62c7f7b85fc2 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1468452 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: interface layer for falconMahantesh Kumbar2017-05-03
| | | | | | | | | | | | | | | | - struct nvgpu_falcon to hold properties of falcon controller - falcon controller interface layer which establish access to required falcon controller HAL based on struct nvgpu_falcon member flcn_id & flcn_base parameter. - each falcon nvgpu_falcon struct initialized during init with id, base-address along with other properties at HAL. - Added defines related to flacon controller. Change-Id: Ia7777c01ecc542150ddd72f8603b7b4475522b58 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1467523 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix sparse warningSrikar Srimath Tirumala2017-05-03
| | | | | | | | | | | | Declare bwmgr_set_rate as static since it is not used globally. Bug 200067946 Change-Id: Ic853ff34b88aae90d0f8821478bcabeaa0cbd7ac Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1469946 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove Linux include from allocator.hAlex Waterman2017-05-02
| | | | | | | | | | | | Remove an unnecessary Linux include from allocator.h. Change-Id: I737944746ffbcc6f20f2fa5c87f112f9393ed6bc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1472366 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove unused variable and do_div()Alex Waterman2017-05-02
| | | | | | | | | | | | | | Remove an unused variable that missed compilation checks because it gets assigned to by do_div(). This same issue was propagated to multiple places. Change-Id: Ica2f675abbb3c08107ea4e6bc19044c0537a7484 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1472365 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add bitmap.h to nvgpu's bitops.hAlex Waterman2017-05-02
| | | | | | | | | | | | | | | | In the Linux kernel many bitmap operations are included in bitmap.h and not in bitops.h. In nvgpu it seems we assume that these two sets of functions are contained in the same header. This patch ensures then when including bitops.h we get both bitmap declarations and bit ops declarations. Change-Id: I9fea75d6c920e1a2992922f927f2d91bbdbdedd3 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1472364 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove gk20a_reset_priv_ringSeema Khowala2017-05-02
| | | | | | | | | | | | | gk20a_reset_priv_ring does not help resetting priv ring. Chip reset is the only way to recover. Bug 200300756 Change-Id: Ia913d46b0e71cd42e9ce242b2393c50f4d12e002 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1471445 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix error for static code analysisVijayakumar2017-05-02
| | | | | | | | | | | | | | | | | | use memset to fill structures with zero instead of assigning zero. mark functions local to the file as static fixing errors in clk, perf and therm modules. Bug 200299572 Change-Id: I0470298803c35b6faed2edc2a0c1dbf0e47e842e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1472940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: include hal.h from hal.cKonsta Holtta2017-05-02
| | | | | | | | | | | | | | | Bring the declarations visible to where they're defined. Bug 200299572 Change-Id: I6261433a754ae20fed4dd7fcde15a4bbaacc2249 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1471353 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Add new flag support_pmu to gk20aTerje Bergstrom2017-05-02
| | | | | | | | | | | | | | Add new flag support_pmu to struct gk20a at probe time, and access it from gk20a instead of support_gk20a_pmu() which depends on struct device *. JIRA NVGPU-16 Change-Id: I721f1a532e949c98346086abdc2630a8df6eba7b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463546 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: Dump error on priv ring intr"Terje Bergstrom2017-05-01
| | | | | | | | | | | | This reverts commit 69d7652aaa9cf94873cccae13c7b6f6a4eb224af. Bug 1918711 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Change-Id: Ie28c668729c4956f18e6fa3c820f476d2e4424a4 Reviewed-on: http://git-master/r/1473044 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
* gpu: nvgpu: gp10b: fix error for static code analysisSeema Khowala2017-04-28
| | | | | | | | | | | | | Include platform_gp10b.h for declared functions Bug 200299572 Change-Id: I5e52fab2750d6fad09d286afa94b8aae67fe1b4c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1472264 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix K4.9 sparse messagesDavid Nieto2017-04-28
| | | | | | | | | | | | | | | | | Fix issues related with wrong storage type for 64 bit variables. (1) Fixed width of HZ_TO_MHZ constant (2) changed fence_wait timeout to store unsigned long bug 200299572 Change-Id: Ie8f2386b738f3aafce75fc2440947e36befac273 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1471611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use correct register for ROM controlTerje Bergstrom2017-04-28
| | | | | | | | | | | | | | We access ROM control register with xve_writel, but we also add the base register address. This leads to adding the base address twice, and the access goes to wrong register. Bug 1846641 Change-Id: I46ef277aac661a08049935b08505120cad1a5e76 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1471505 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gp106: Disable MMU write violation reportingTerje Bergstrom2017-04-28
| | | | | | | | | | | | | Disable reporting of write privilege violation on FB MMU registers. Bug 1846641 Change-Id: I011385c5b06bbb2dcc8d4521236a04a8be5dd34e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1471463 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Dump error on priv ring intrTerje Bergstrom2017-04-28
| | | | | | | | | | | | | Write an error to UART on priv ring error. This uncovers any accesses to missing registers or illegal accesses to registers. Bug 1846641 Change-Id: Ic1e5ecadcd95777f2b3f7bd77accf98ddce97282 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294683 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Use nvgpu_mem instead of custom sgtAlex Waterman2017-04-28
| | | | | | | | | | | | | | | | | | | | Use an nvgpu_mem created from a page in the ACR code instead of a scatter gather table created by the Linux SGT APIs. The ACR code needs to have the GPU map a physical page queried from an external API (other than the regular DMA API). Note that this code used to explicitly mark the SGT it makes as bypassing the SMMU. However, that is now taken care of implicitly by the __nvgpu_mem_create_from_pages() function. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: Ie40152a7611e985e1b97ac2ddc7e27664b71917c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1464082 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ptimer_src_freq to gk20aTerje Bergstrom2017-04-28
| | | | | | | | | | | | | Copy ptimer_src_freq to struct gk20a at probe time, and access it from gk20a instead of platform_gk20a. JIRA NVGPU-16 Change-Id: I92c1b83d6e2305a19eb2cd267b7dd8d97c1fdc44 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463544 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use correct flags for secure allocsKonsta Holtta2017-04-26
| | | | | | | | | | | | | | | | The gfp_t argument for dma_alloc_attrs() cannot take DMA_MEMORY_NOMAP - it's interpreted as __GFP_RECLAIMABLE which has the same integer value. Use GFP_KERNEL for the flag argument and set DMA_ATTR_NO_KERNEL_MAPPING for dma attrs which the code was trying to do with the flag that is meant for the coherent allocation API. Bug 200299572 Change-Id: Ie4d988fbeeb954f6f7ccd4f9fb438968d76f0c6c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1468315 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-28 19:45:55 -0400