| Commit message (Collapse) | Author | Age |
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bug 1648908
Change-Id: I32211b13489b21eba25f7473a18b9d1a303d2642
Signed-off-by: Arul Sekar <aruls@nvidia.com>
Reviewed-on: http://git-master/r/1029733
Reviewed-by: Arun Gona <agona@nvidia.com>
Tested-by: Arun Gona <agona@nvidia.com>
Reviewed-on: http://git-master/r/1111716
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Update regops whitelist with two new registers.
Bug 1734151
Change-Id: Id09bdfb1733620bb75d4558299c5e9c7f66bb00b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1029772
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
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Add/update following prod settings:
blcg ce
slcg ce2
Change-Id: I10a62d980479ad23efd7033d29e269c4aac08834
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1030986
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Refactor makefiles so that there is one makefile, and that file
can be included in the main nvgpu build.
Bug 1476801
Change-Id: I23ac451d695fc64064de2300e83b9d9487c52743
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1028353
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Update prod settings to disable stall blcg.
Bug 1729471
Change-Id: I1123bf47159fc9dbb1223aebcacf37361b90743f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1026611
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The ECC sysfs stat creation function is called on GR init. GR can get
initialized multiple times but we only need to create the ECC stats
once. Therefore, add a check to avoid creating duplicate stat sysfs
nodes.
Change-Id: Ifb338e57643f2f15492df137d2a7521e0c990cf2
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/1021660
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fixed the following sparse warning by making local symbol static:
- platform_gp10b_tegra.c:365: warning: symbol 'ecc_hash_table' was not declared.
Should it be static?
Bug 200088648
Change-Id: Iea1a682c3ee0609730366d44fab91849cd59c9ad
Signed-off-by: Amit Sharma <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/1022410
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
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Update prod settings to disable slcg pbdma related
domains.
Bug 1703083
Change-Id: I9f9192da69d07c5cea5bc7d79a031e5d2428b685
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1022219
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 7c1f6f0b2998c354f315b431e00f3c8f861cb190.
Bug 200176691
Change-Id: Ia546513ec5c61999f6eb4d56ccd7e45ae072167c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1020813
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-sysfs functions to call into LS PMU and modify
ECC overide register
Bug 1699676
Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/921252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 71b59d75fc49e2159830026bce387ef4d829faa8
since it causes suspend_sanity to fail on quill platform.
On system resume, we see the following error dump from GPU
gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 501 timed out
gk20a 17000000.gp10b: gk20a_fifo_set_ctx_mmu_error_ch: channel 501 generated a mmu fault
gk20a 17000000.gp10b: gk20a_set_error_notifier: error notifier set to 31 for ch 501
gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 509 timed out
Change-Id: I61bc3b0745fe136675ab79b13f54e9126602f51c
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/1017967
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 1698618
Change-Id: Iabfd726891165d7879376ab96445b7b81b907153
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/841856
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ELPG is enabled on TOT.
Bug 200144583
Change-Id: Icbdcb5f575a4ca37becf47b098fbd6a1f89feec7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1013845
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add sysfs nodes for querying ECC single/double bit error counts.
Bug 1699676
Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935363
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Pass faulting channel pointer to gr_gk20a_handle_sm_exception()
instead of NULL
Bug 200156699
Change-Id: I909327e2a000bea8bc91cfd0820a759960664b46
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1011289
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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fix below sparse warning :
drivers/gpu/nvgpu/gp10b/gr_gp10b.c:1364:5: warning: symbol
'gr_gp10b_pre_process_sm_exception' was not declared. Should it be
static?
Bug 200088648
Change-Id: Ie55ffc12eb653b10358001e2aef8766562fd0df9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1009938
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Bug 200088648
Change-Id: I61be7b4787e9bc9bac310a8739977f43c38a67ee
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1000174
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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While posting CILP preemption complete event to
user space, raise the event to all channels of TSG
(if channel is part of TSG)
This is a WAR until we have proper sync mechanism
with user space to raise CILP events
Bug 200156699
Change-Id: Ieedc866498a8c5464cf65962257a803b37da6826
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1001696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add CILP support for gp10b by defining below function
pointers (with detailed explanation)
pre_process_sm_exception()
- for CILP enabled channels, get the mask of errors
- if we need to broadcast the stop_trigger, suspend all SMs
- otherwise suspend only current SM
- clear hww_global_esr values in h/w
- gr_gp10b_set_cilp_preempt_pending()
- get ctx_id
- using sideband method, program FECS to generate
interrupt on next ctxsw
- disable and preempt the channel/TSG
- set cilp_preempt_pending = true
- clear single step mode
- resume current SM
handle_fecs_error()
- we get ctxsw_intr1 upon next ctxsw
- clear this interrupt
- get handle of channel on which we first
triggered SM exception
- gr_gp10b_clear_cilp_preempt_pending()
- set cilp_preempt_pending = false
- send events to channel and debug session fd
Bug 200156699
Change-Id: Ia765db47e68fb968fada6409609af505c079df53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/925897
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add API gp10b_mask_hww_warp_esr() to mask
hww_warp_esr appropriately on gp10b
Bug 200156699
Change-Id: I451b5e949bd4e6d286e5d0c7cd7616e6cfaf3ea9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/927129
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add ECC exception handling support for SM, TEX, and LTC.
Bug 1635727
Bug 1637486
Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935362
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Removed unwanted initlization of function pointer.
Bug 200157852
Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/843218
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Enable engine level power gating(elpg)
Bug 200144583
Change-Id: I66f3be841625c2c9e07cafbf19af8f1dbdbfd390
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/818637
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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For copy engine, add 16 clock cycle delay
before engine clock gating.
Bug 1717152
Change-Id: Ife92299c052f44000bc0d900f0129a2eab13f3b5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/998408
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Enable gradual slowdown for gp10b and also correct
thermal slowdown factors with extended mode.
Bug 1719974
Change-Id: I31a5d7df71c98135273a980c49b70bc76fac0b40
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/933279
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Restore comptags to be bitmap-allocated, like they were before we had
the buddy allocator.
Bug 200145635
Change-Id: I681493871096f437014b7eca1182fefbaf7f6a74
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/839240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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It'll detect dead semaphore acquire. The worst case is when
ACQUIRE_SWITCH is disabled, semaphore acquire will poll and
consume full gpu timeslicees.
The timeout value is set to half of channel WDT.
Bug 1636800
Change-Id: Idbd4bfa52981e8a849b62a168e3a6828330112f5
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/928830
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Context & global whitelists are same, so delete second copy. Update
the list.
Bug 200164983
Change-Id: I440ce04316120b8128baeabc002c55436cf41d5b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/931178
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandarbh Jain <sanjain@nvidia.com>
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
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The server only releases ownership of the ctxsw buffer mappings
after the GR ctx has been released. Update the sequence to
account for this.
JIRA VFND-1117
Bug 1708163
Change-Id: I3aed015805b4ca51433e7d37ad32de2f8353999f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/922817
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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gr_*__set_alpha_circular_buffer_size() left max_batches field of
gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta
transitions and poor performance when tessellation or geometry
shaders are used
Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/840079
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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It didn't set gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r
causing a GPU MMU fault when used.
Bug 200141640
Bug 200141981
Bug 200141640
Change-Id: I8b9f71e480553ead2827ff1f1dde2ba2e6efe697
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/807694
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add gradual slowdown registers, and fix names for L2 flush registers.
Change-Id: If085c4febef494ae299d2147ca5201cd373bee0b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/839369
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Add tile caching registers to access map.
Bug 1692373
Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Bug 1692373
Change-Id: I63bb1f8a40fe5d2c7b61440c989b78e4cb3ece98
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812351
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Make gp10b_freq_table static to fix sparse warning
Bug 200088648
Change-Id: Ibaaabd145e37685e049ac3a49e2b276fb6545d0e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/837421
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 200151348
Change-Id: I44851b69adfe9c6bf5d4c897730d6da7df9bedd8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/836877
(cherry picked from commit 69de3f3c439f544fd5f9223f5663010f5ec80193)
Reviewed-on: http://git-master/r/837228
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for gp10b freq scaling.
Bug 200147662
Reviewed-on: http://git-master/r/816962
(cherry picked from commit 62de7dba758e46ee80c896dcfcbccb0f8b979438)
Change-Id: I71ddfa394d490c002761d2a8bbb95090a4c0e799
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/834758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Tell gk20a_init_vm() that bar2 VM is kernel-managed.
Bug 200077571
Change-Id: I151c540a6dec76238e7959f745cfca280927f2d4
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/746803
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Set initial gpcclk rate to 1GHz.
Bug 200151332
Reviewed-on: http://git-master/r/834113
(cherry picked from commit 9ed69164da7afeec20c3a557885f74db4cbea9cb)
Change-Id: I85107eb5852b25977b30663f6ae173b271ecafeb
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/834322
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Do ZBC updates without forcing engine idle first.
Bug 1698013
Change-Id: I188563dd60ba511b087e9b9bdacd7f9445efd7a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829146
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This reverts commit cc9bd2dc24f562e97a87641e7436594fd3b469f2.
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: Ic4493bc7b71a2ebfb49644c91b34222dd15a9be1
Reviewed-on: http://git-master/r/830854
GVS: Gerrit_Virtual_Submit
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Use bindings more specific to the ARM SMMU.
Change-Id: I0e2df8e8e7bfa51036a84e923fa06e42bbed3cd7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/812438
(cherry picked from commit 98cb259c87e9531b0a21dfd3132a3f3db07ff6f0)
Reviewed-on: http://git-master/r/831515
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
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Some of the allocated buffers are used during normal graphics
processing. Mark them as GPU cacheable to improve performance.
Bug 1695718
Change-Id: I71d5d1538516e966526abe5e38a557776321597f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/827087
(cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed)
Reviewed-on: http://git-master/r/828493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1698618
Change-Id: I5bad939d94171d2296897260043f0e67e43802e7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829097
(cherry picked from commit a067cfeb8dda03641ba981d86bef93fa9041e18e)
Reviewed-on: http://git-master/r/829414
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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VM server only know big page and small page, so convert
gmmu_page_size_kernel to according page size index.
JIRA VFND-890
Change-Id: Id1f932752b8ca33d14635ac9d71019364aa89dc4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/816359
(cherry picked from commit 5bfc4a2a55889f5457bd34aa06861c042ee67421)
Reviewed-on: http://git-master/r/827131
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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This reverts commit c2707054192b058eec24a52c7f586b030f9ff007. It
introduces regression in T124.
Bug 1702063
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I8516c0bfe129bb1ac3d7a1983846061df8ae967b
Reviewed-on: http://git-master/r/830787
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Set platform data with ptimer source frequency.
Removed ptimerscaling10x platform data, and use
ptimer source frequency to calculate ptimerscaling
factor.
Reviewed-on: http://git-master/r/819031
(cherry picked from commit 6849603024943184b0463233bedd95934c353663)
Change-Id: I14b0735fcb602cda2e692f6b842a5ecf469ab724
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/827301
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I260958d8dea1b445f91b8d15bf76d5321bdc76d1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/758653
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Add required fileds and values for thermal slow-down
settings in thermal header file and corrected
thermal register programming with correct values.
Bug 1695567
Reviewed-on: http://git-master/r/822200
(cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981)
Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/823013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement function to support bar2 vm clean-up.
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/814573
Change-Id: If5d884e4e1ed87bec6284719d90e9e1963c69bed
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/815428
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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