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* gpu: nvgpu: gv11b: MMU parity HWW error intrDavid Nieto2017-05-11
| | | | | | | | | | | | | | | | | Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Separate GMMU out of mm_gk20a.cAlex Waterman2017-05-11
| | | | | | | | | | | | | t19x version of same named patch in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I0b176577c0edcdcc587f22a6908045a960f830e2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1464111 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: changes related to preemeptionseshendra Gadagottu2017-05-10
| | | | | | | | | | | | | | | | | | | Added function pointers to check chip specific valid gfx class and compute class. Also added function pointer to update ctx header with preemption buffer pointers. Also fall back to gp10b functions, where nothing is changed from gp10b to gv11b. Bug 200292090 Change-Id: I69900e32bbcce4576c4c0f7a7119c7dd8e984928 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1293503 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: gv11b: enable big pages"Seema Khowala2017-05-04
| | | | | | | | | | | | This reverts commit 90d029fd28c25904bb84f929f1a65075a8d9b6e4. Bug 200305653 Change-Id: I2baa4b286e14ce57e68ab1e9cc15630ee24f5bc9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1475515 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix sparse warningseshendra Gadagottu2017-05-04
| | | | | | | | | | | | | | | | | | | | Fixed following sparse warning by including relevant header: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c:82:23: warning: symbol 't19x_gpu_tegra_platform' was not declared. Should it be static? Bug 200299572 Change-Id: Ibf7b69da9b76e72d610571135bd412c865b69a5f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1474940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: init interface layer support for PMU falconMahantesh Kumbar2017-05-03
| | | | | | | | | Change-Id: Iadd72196ed7df7384b1ecdc06ecd98828061fd3e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1473685 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: hw header update for CL38424879Seema Khowala2017-05-02
| | | | | | | | | | | | | Bug 200300756 Change-Id: I2991d306905d2681cfb3031301e1b45a215ff89b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1466955 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Use new support_pmu flagTerje Bergstrom2017-05-02
| | | | | | | | | | | | | | Use new gk20a->support_pmu flag instead of using the old support_gk20a_pmu() macro. The latter depends on access to Linux device structure. JIRA NVGPU-16 Change-Id: I6b843305b15b29893a1e3b0d60f37c44bdb3b2cb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463535 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix error for static code analysisSeema Khowala2017-04-28
| | | | | | | | | | | | | Functions that are not declared in header files are made static Bug 200299572 Change-Id: Ibf9e9cc9f48ad9ceaa202d1bb7ed57724057cda0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1471538 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Access ptimer_src_freq from gk20aTerje Bergstrom2017-04-28
| | | | | | | | | | | | Access ptimer_src_freq from gk20a instead of gk20a_platform. JIRA NVGPU-16 Change-Id: I3f2fcd22eb8a14c83ee2d481ff9f5acdf00f9c07 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move semaphore impl to nvgpu_memAlex Waterman2017-04-25
| | | | | | | | | | | | | | | t19x version of similarly named patch in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I5b0ce285a25a456d019670fc25b25ed564444643 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1464110 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Use new clk HALTerje Bergstrom2017-04-24
| | | | | | | | | | | | | | | | | | Use the new clk HAL to request clock rate instead of direct calls to Clock Framework. This cuts one direct dependency to Linux APIs. Also change the HAL to not clear clk ops after they've been initialized. JIRA NVGPU-16 Change-Id: I1ab3eac8268f1f3f3305d49782c6a0eb57c6d617 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463536 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Move Linux nvgpu_mem fieldsAlex Waterman2017-04-20
| | | | | | | | | | | | | | | | t19x part for this change in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I31116b4241076b39a6638273281630a1527bcd35 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1464109 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: enable big pagesSeema Khowala2017-04-19
| | | | | | | | | | | | | | Do not depend on bypass_smmu to set disable_bigpage Bug 1805409 Change-Id: Ie602e3567162896acbc6a2da5f7f2db5cfb8021f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1465071 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init css opsSeema Khowala2017-04-19
| | | | | | | | | | | | Bug 1870532 Change-Id: Ib8d61e92ad825b9ae5345f62ed2df343b50231b0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1464994 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set soc credits after fs_hub is out of resetSeema Khowala2017-04-18
| | | | | | | | | | | | Without these credits, gpu mmu binds over nvlink to soc are hanging. Also add l2_enabled for mc_elpg_enable. Bug 1899460 Change-Id: I0b26410d5c8ec9b4c88b319ddd9442f2fd91b321 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1463204 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Use new error macrosTerje Bergstrom2017-04-17
| | | | | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert the last remaining user of old macros to new ones. JIRA NVGPU-16 Change-Id: Ib665cfb395fe46ac988ed14d67adef885098e524 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1462968 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: function to get max veidseshendra Gadagottu2017-04-16
| | | | | | | | | | | | | | | Defined function to get max number of subcontexs supported and used it where max subcontext count required. JIRA GV11B-23 Change-Id: I4f6307162486bab1e91cbf66abfee7763c70fe7b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1318146 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init pbdma_intr_0 handlerSeema Khowala2017-04-12
| | | | | | | | | | | | | | | | | | Add handling for below two interrupts on top of legacy ones. When pending, PBDMA is stalled and s/w is expected to execute teardown. clear_faulted_error: host is asked to clear fault status when no fault has been asserted. eng_reset: An engine was reset while the PBDMA unit was processing a channel from a runlist which serves the engine. JIRA GPUT19X-47 Change-Id: I776e5799a73a1b63c394048fa61b597e621cf544 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1306558 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix *get_runlists_mask*Seema Khowala2017-04-12
| | | | | | | | | | | | | | | if ch/tsg id is unknown and bit mask for the engines that need to be recovered is not set, runlist mask should correspond to max number of supported runlists JIRA GPUT19X-7 Change-Id: I08e67af0846784a7918510d68de34e9162a42bf6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1458155 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout opsSeema Khowala2017-04-12
| | | | | | | | | | | | | | | | | | | - detect and decode sched_error type. Any sched error starting with xxx_* is not supported in h/w and should never be seen by s/w - for bad_tsg sched error, preempt all runlists to recover as faulted ch/tsg is unknown. For other errors, just report error. - ctxsw timeout is not part of sched error fifo interrupt. A new fifo interrupt, ctxsw timeout is added in gv11b. Add s/w handling. Bug 1856152 JIRA GPUT19X-74 Change-Id: I474e1a3cda29a450691fe2ea1dc1e239ce57df1a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1317615 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Enable PMU support for T19X.Deepak Goyal2017-04-11
| | | | | | | | | | | | JIRA GPUT19X-30 Change-Id: Ib9cb19eb1850c70f3e6db60660184569f5165263 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1253565 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Use new error macrosTerje Bergstrom2017-04-10
| | | | | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I8c0d8944f625e3c5b16a9f5a2a59d95a680f4e55 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1459822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Rename nvgpu DMA APIsAlex Waterman2017-04-06
| | | | | | | | | | | | | | | | | | | gv11b changes to go along with gpu: nvgpu: Rename nvgpu DMA APIs In the main nvgpu repo. JIRA NVGPU-12 Change-Id: I5e28b13448d171e1511ace0842e53700385f8489 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1455213 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move DMA API to dma.hAlex Waterman2017-04-06
| | | | | | | | | | | | | | | | | | | Handle gv11b specific of gpu: nvgpu: Move DMA API to dma.h In the main nvgpu repository. JIRA NVGPU-12 Change-Id: I9645c4eedc5f61585d15caeee54db92bc4cca079 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1455212 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: rename mem_desc to nvgpu_memAlex Waterman2017-04-06
| | | | | | | | | | | | | $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' JIRA NVGPU-12 Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1326194 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rename gk20a_mem_* functionsAlex Waterman2017-04-06
| | | | | | | | | | | | Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: I5a1180c9a08d33c3dfc361ce8579c3c767fa5656 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1326193 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: implement teardown_ch_tsg fifo opsSeema Khowala2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Context TSG teardown procedure: 1. Disable scheduling for the engine's runlist via NV_PFIFO_SCHED_DISABLE. This enables SW to determine whether a context has hung later in the process: otherwise, ongoing work on the runlist may keep ENG_STATUS from reaching a steady state. 2. Disable all channels in the TSG being torn down or submit a new runlist that does not contain the TSG. This is to prevent the TSG from being rescheduled once scheduling is reenabled in step 6. 3. Initiate a preempt of the engine by writing the bit associated with its runlist to NV_PFIFO_RUNLIST_PREEMPT. This allows to begin the preempt process prior to doing the slow register reads needed to determine whether the context has hit any interrupts or is hung. Do not poll NV_PFIFO_RUNLIST_PREEMPT for the preempt to complete. 4. Check for interrupts or hangs while waiting for the preempt to complete. During the pbdma/eng preempt finish polling, any stalling interrupts relating to runlist must be detected and handled in order for the preemption to complete. 5. If a reset is needed as determined by step 4: a. Halt the memory interface for the engine (as per the relevant engine procedure). b. Reset the engine via NV_PMC_ENABLE. c. Take the engine out of reset and reinit the engine (as per relevant engine procedure) 6. Re-enable scheduling for the engine's runlist via NV_PFIFO_SCHED_ENABLE. JIRA GPUT19X-7 Change-Id: I1354dd12b4a4f0e4b4a8d9721581126c02288a85 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1327931 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: ngpu: gv11b: support hub interruptSeema Khowala2017-03-30
| | | | | | | | | | | | | | Hub interrupt handler will be added later JIRA GPUT19X-7 Change-Id: I892e392c6c1fe7d92795b2cab2301f2e68e787c3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313453 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move programming of host registers to fifoTerje Bergstrom2017-03-28
| | | | | | | | | | | Move code that touches host registers to fifo HAL. This sorts out some of the dependencies between fifo HAL and channel HAL. Change-Id: I2bff0443ae1c1fa5608e620974b440696d1cfdc4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323385 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove unnecessary use of dev_name()Terje Bergstrom2017-03-28
| | | | | | | | | | | | | | | Move the name field from struct gpu_ops up to struct gk20a. The field is not a function op, so it doesn't belong in gpu_ops. Replace all uses of dev_name() with use of g->name when possible. JIRA NVGPU-16 Change-Id: I053aeb256f591af2ea9ef5094a20e33a395cdd33 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1328535 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: init and implement reset_enable_hwSeema Khowala2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -implement gv11b specific reset_enable_hw fifo ops -timeout period in fifo_fb_timeout_r() is set to init instead of max This register specifies the number of microseconds Host should wait for a response from FB before initiating a timeout interrupt. For bringup, this value should be set to a lower value than usual, such as ~.5 milliseconds (500), to help find out bugs in the memory subsystem. -timeout period in pbdma_timeout_r() is set to init instead of max This register contains a value used for detecting timeouts. The timeout value is in microsecond ticks. The timeouts that use this value are: GPfifo fetch timeouts to FB for acks, reqs, rdats. PBDMA connection to LB. GPfifo processor timeouts to FB for acks, reqs, rdats. Method processor timeouts to FB for acks, reqs, rdats. The init value is changed to 64K us based on bug 1816557. JIRA GPUT19X-74 JIRA GPUT19X-47 Change-Id: I6f818e129c3ea67571d206c5e735607cbfcf6ec6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1325352 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix engine context preempt completionSeema Khowala2017-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CTX_STATUS_SWITCH: Engine save hasn't started yet, continue to poll CTX_STATUS_INVALID: The engine context has switched off. The preemption step for this engine is complete. CTX_STATUS_VALID or CTX_STATUS_CTXSW_SAVE: check the ID field: * If ID matches the TSG for the context being torn down, the engine reset procedure can be performed, or SW can continue waiting for preempt to finish if id is not being torn down. * If ID does NOT match, the context isn't running on the engine. CTX_STATUS_LOAD: check the NEXT_ID field: * If NEXT_ID matches the TSG of the context being torn down, the engine is loading the context and reset can be performed immediately or after a delay to allow the context a chance to load and be saved off, or sw can continue waiting for preempt to finish if id is not being torn down. * If NEXT_ID does not match the TSG ID or CHID then the context is no longer on the engine. SW may alternatively wait for the CTX_STATUS to reach INVALID, but this may take longer if an unrelated context is currently on the engine or being switched to. JIRA GPUT19X-7 Change-Id: I61499f932019de32e0200084c4c41b21a7cbbd2b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1327164 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: hal should use gv11b_init_busSeema Khowala2017-03-24
| | | | | | | | | | | | | | | gk20a_init_bus should not be used for gv11b hal init as bar1_bind is not supported. Change-Id: I59b6e991b12d8355b1f54ae3eaf78dc94ca6d767 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1327171 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Enable CE alwaysTerje Bergstrom2017-03-24
| | | | | | | | | | | | | All GPUs have a copy engine. So delete the flag has_ce, because it's always true. JIRA NVGPU-16 Change-Id: I6daa77ff70ccc0195352109916cb98b43a2109de Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1325357 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: null check for fault_chSeema Khowala2017-03-23
| | | | | | | | | | | | | | | gk20a_gr_get_channel_from_ctx() could return NULL as a result fault_ch could be null JIRA GPUT19X-7 Change-Id: If89507d3d3fa5a95ba75c4a90eb212d0c8b2214a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1323255 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: implement init_pbdma_intr_desc fifo opsSeema Khowala2017-03-23
| | | | | | | | | | | | | | | | | | | | | Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w variables for pbdma_intr_0 interrupt masks. pbdma_intr_0 field changes for gv11b:- bit 8(lbreq) does not exists in hw. bit 28 (syncpoint_illegal)is removed in hw. bit 20 is reused for clear_faulted_error in hw. bit 24 (eng_reset) and bit 25 (semaphore) always existed in hw but never handled in s/w. These are added as channel fatal. JIRA GPUT19X-47 Change-Id: I13673430408f1cf7ef762075a29b94196f79a349 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1325401 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add bus HALTerje Bergstrom2017-03-23
| | | | | | | | | | | Add bus HAL and separate bus related functions from mm_gv11b: timer access. Change-Id: I311f258857238233103688fb653d27e4e79005a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323354 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: remove unnecessary tegra_edp headerKonsta Holtta2017-03-23
| | | | | | | | | | | | Drop one #include, its contents are not used. Bug 1853519 Change-Id: I51480b1d75b36c993af3a5005ee9b7fc6dee8a54 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1326127 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: remove .late_probe and .removeKonsta Holtta2017-03-23
| | | | | | | | | | | | | | | | | | The calls to nvhost_{register,unregister}_client_domain don't do anything, so remove the platform device's late_probe and remove ops that serve no other purpose than calling those empty functions. Remove also the corresponding #includes which are now unused. Bug 1853519 Change-Id: I67149d1575be5b3cacc60e6c28e6f2debfabf71c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1326126 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init mm ops for mmu_fault_pendingSeema Khowala2017-03-22
| | | | | | | | | | | | mmu fault reporting is moved from fifo* to fb* and gmmu* hw registers. JIRA GPUT19X-7 Change-Id: If2040ab661229c2e734042f2eec1592030615fee Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1315203 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: abstract away dma alloc attrsKonsta Holtta2017-03-21
| | | | | | | | | | | | | | Don't use gk20a_gmmu_free_attr because the attrs are embedded in struct mem_desc now. Bug 1853519 Change-Id: Iaa4309d4c2cd334346e09c4fbf15ce826f2ff640 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321314 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: implement is_preempt_pendingSeema Khowala2017-03-21
| | | | | | | | | | | | | | | | | | | preempt completion should be decided based on pbdma and engine status. preempt_pending field is no longer used to detect if preempt finished. add a new function to to be used for preeempting ch and tsg during recovery. If preempt timeouts while in recovery, do not issue recovery. JIRA GPUT19X-7 Change-Id: I0d69d12ee6a118f6628b33be5ba387c72983b32a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1309850 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: init intr_0_error_mask fifo opsSeema Khowala2017-03-20
| | | | | | | | | | | mmu fault is now part of hub interrupt Change-Id: I9ce523d5f11955ac9552510d154eaa2f17a6cbf6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313484 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix stall interrupt enablementSeema Khowala2017-03-14
| | | | | | | | | | | | | Currently priv, pbus and ltc interrupts are enabled as non-stall but being handled in stall isr. Fix is to configure them as stall interrupt. Change-Id: I86adc04f480d5f4befe7e9255b582ce13fa4efc1 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1319018 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add tpc floor sweeping codeseshendra Gadagottu2017-03-14
| | | | | | | | | | | | | | Added TPC floor sweeping code for gv11b. JIRA GV11B-73 Change-Id: Ib0d05e2d606fe13dff119948fbc9022e8af0fa7f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1315257 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: gv11b: support debug dumpSeema Khowala2017-03-09
| | | | | | | | | | | | | | Added dump for pbdma, engine status, channel status and ramfc JIRA GV11B-45 Change-Id: I25442932c61310005fea481455f68ba10c361381 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1302425 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: ltc related changesseshendra Gadagottu2017-03-08
| | | | | | | | | | | | | | | | | | There is no peermem access for gv11b nvlink. So no need to enable peermem access through l2. Implemented gv11b specific ltc_cbc_fix_config function to read correct num_active_ltcs. JIRA GV11B-71 Change-Id: I348ce3bbf42e864341494e386b6f33478badb3a8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1315148 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: trigger mmu fault is not supportedSeema Khowala2017-03-08
| | | | | | | | | | | | | For gv11b fifo recovery, triggering fake mmu fault is not required. JIRA GV11B-7 Change-Id: I6c8c9672085dbbbd77e0d991d840c4cc75c2ab43 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313496 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init is_fault_engine_subid_gpc opsSeema Khowala2017-03-07
| | | | | | | | | | | | | *client_type_gpc_v moved from fifo to gmmu JIRA GV11B-7 Change-Id: Icd28a2ac8c0d0ae212cfca9410dfe781972367df Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313435 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 12:02:55 -0500