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* gpu: nvgpu: disable/preempt TSG for hwpm updateDeepak Nibade2016-05-30
| | | | | | | | | | | | | | | | | To update hwpm, we currently disable/preempt only one channel without considering if channel could be part of a TSG Hence, use proper APIs to disable/preempt/enable which will internally handle channel/TSG case Bug 200203191 Change-Id: I329a3c02d635265775f2081abba8e047f491fe7d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1155838 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-05-30
| | | | | | | | | | | | | | Fix below sparse warning : $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pci.c:145:14: warning: symbol 'nvgpu_pci_class' was not declared. Should it be static? Bug 200088648 Change-Id: Ia3e8f1ae426fa72254b5204da0f6f85502b4670c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1155981 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Add device_info_data supportLakshmanan M2016-05-27
| | | | | | | | | | | | | Added device_info_data parsing support for maxwell GPU series. JIRA DNVGPU-26 Change-Id: I06dbec6056d4c26501e607c2c3d67ef468d206f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151602 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use correct IO register pointerTerje Bergstrom2016-05-27
| | | | | | | | | | | | | Use correct IO register pointer in cyclestats code. The code used reg_mem which is not supposed to be used. It is defined only on iGPU. Change-Id: I03cdaf5d2add2bf2c7cc6d7b3c41ac3be0f9a768 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1154708 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: align DMA base in chip HAL methodMahantesh Kumbar2016-05-27
| | | | | | | | | | | | | | | align DMA base in chip HAL method instead in generic method. Bug N/A Change-Id: I47a250380e083f393677b65c13d0c2c894214ca7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1154909 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ELPG init based on flagMahantesh Kumbar2016-05-26
| | | | | | | | | | | | flag helps to enable/disable ELPG init in SW Bug N/A Change-Id: I73eb592b789c2c29db8a75018cbd1617dcf16df8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1152430 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move & rename acr_gm20b to acr_descMahantesh Kumbar2016-05-26
| | | | | | | | | | | | | acr_gm20b renamed to acr_desc to support multiple gpu chips JIRA DNVGPU-10 Change-Id: Ib3b38d5845043f026ddc365a682b7bb454463326 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1152401 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: secure boot HAL updateMahantesh Kumbar2016-05-26
| | | | | | | | | | | | | Updated/added secure boot HAL with methods required to support multiple GPU chips. JIRA DNVGPU-10 Change-Id: I343b289f2236fd6a6b0ecf9115367ce19990e7d5 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1151784 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Validate regops num_ops argumentTerje Bergstrom2016-05-26
| | | | | | | | | | | | Check that num_ops is not too big. We have a hard limit of 1 page allocated for the operations. Bug 200192125 Change-Id: I724039c9dd6e0e93d9df0f5b3a797158fdb5e687 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1132965 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Use kernel bitmap ops for perfmon idsTerje Bergstrom2016-05-26
| | | | | | | | | | Bug 200192125 Change-Id: I44418fbbe393d5b9463dc3c9e62f3673da2a06c5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1132967 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: reorder disable_irqSeshendra Gadagottu2016-05-25
| | | | | | | | | | | | Disable irqs before suspending gpu sub-units. This is to prevent potential races between irq threads and suspend routines. Change-Id: Icc60f517db8ae8129bcf10be53d37d34b6d9242c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1152844 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not reallocate pes_tpc_mask arrayTerje Bergstrom2016-05-25
| | | | | | | | | We allocated a new pes_tpc_mask for each PES on each GPC. This causes us to forget masks for all GPCs but the last one. Change-Id: I825788ad75333d4aecd93c78d1b277c0d9d65f15 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1152703
* gpu: nvgpu: Validate perfmon id countTerje Bergstrom2016-05-25
| | | | | | | | | | | Add a check against a too big perfmon id count. Bug 200192125 Coverity ID 24285 Change-Id: I9b17081a1ea7243e6b57c0a95c59913cd8daf98b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1132966
* gpu: nvgpu: Move PCI devnodes to own directoryTerje Bergstrom2016-05-25
| | | | | | | | | | | | | | | | | | To be able to scan, PCI devnodes need to be in a directory with read permission. By default /dev is read protected by SELinux policy. Move the devnodes to their own directory so that reading this one directory can be allowed. At the same time rename the nodes to start with string "card-". JIRA DNVGPU-54 Change-Id: I0df4ced08afd1f3a468e983d07395ffcb8050365 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1152745 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: change kernel pathPritesh Raithatha2016-05-25
| | | | | | | | | | | | | All kernel versions are getting moved inside $TOP/kernel folder. Changing kernel paths accordingly. Bug 200190733 Change-Id: I0ed2aa6d4ae75e6fc2c3adf4ae541ecb5f4fb9a9 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/1143380 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sridhar Lavu <slavu@nvidia.com>
* gpu:nvgpu:gm20b: update elpg prod settingsVijayakumar2016-05-24
| | | | | | | | | | | | | | | | | | | | | bug 1764398 PGSequencer settings use index to writ to PSORDER register setting. HW has implementation for 28 PSORDER (PSORDER0 - 27). Every write will auto increment index and index will wrap around after it reaches 27. In PROD settings we are writing enable for 0 to 27 and zero for 28 to 65. This overwrites enables written to 0 to 27. Effectively those partitions are never power gated. P4 SWCL# 20744424 Change-Id: I45826e98dd6a84e9c4fe119fbe7ca75acfd8a4ea Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1149055 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add PRAMIN support for mem accessorsKonsta Holtta2016-05-24
| | | | | | | | | | | | | | | | | | | | To support vidmem, implement a way to access buffers via the PRAMIN window instead of just kernel-mapped sysmem buffers for iGPU as of now. Depending on the buffer aperture, choose between the two access types in the buffer memory accessor functions. vmap()/vunmap() pairs are no-ops for buffers that can't be cpu-mapped. Two uses of DMA_ATTR_READ_ONLY are removed in the ucode loading path to support writing to them too via the indirection in addition to cpu. JIRA DNVGPU-23 Change-Id: I282dba6741c6b8224bc12e69c1fb3936bde7e6ed Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1141314 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: suppress prints in submit pathDeepak Nibade2016-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | When we run out of gpfifo space or private command buffer space, we have error spew like below : __gk20a_channel_syncpt_incr: not enough priv cmd buffer space gk20a_submit_channel_gpfifo: fail Dumping these prints to UART cause increase in submit latencies But on these failures, we return -ENOSPC to UMD and then UMD retries the submit, hence it might be unnecessary to dump these prints Hence, remove the error prints of insufficient space and use gk20a_dbg_fn() instead of gk20a_err() to print failure in gk20a_submit_channel_gpfifo() Bug 200202653 Change-Id: I49efd7c6c554dd4fbfa4e66d196eb352e69f92c6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1152378 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix compilation issuesSri Krishna chowdary2016-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | compiling kernel with clang pointed out below issues in nvgpu. Fixing them. gr_gk20a.c:1185:12: error: stack frame size of 3152 bytes in function 'gr_gk20a_setup_alpha_beta_tables' cde_gk20a.c:1376:22: error: duplicate 'const' declaration cde_gk20a.c:1377:22: error: duplicate 'const' declaration cde_gk20a.c:1378:22: error: duplicate 'const' declaration ctxsw_trace_gk20a.c:71:19: error: unused function 'ring_space' platform_gk20a_tegra.c:55:19: error: unused function 'pmc_read' platform_gk20a_tegra.c:60:20: error: unused function 'pmc_write' bug 1745660 Change-Id: I8cd4383cb898307bbeb162ca00b3e20d04de2c90 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/1150486 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add checks for tracing enabledTerje Bergstrom2016-05-23
| | | | | | | | | | | | Add checks for all ctxsw trace functions declared in header. This makes sure chips without tracing support continue to work. Change-Id: Ic658a00821b589a7b770c1fde52afede02dc1c9c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1151918 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add support for gm204 and gm206Terje Bergstrom2016-05-23
| | | | | | | | | | | Add support for chips gm204 and gm206. Adds also support for reading VBIOS and booting devinit and pre-os images on PMU. Change-Id: I4824b44245611e5379ace62793cc37158048f432 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120467 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gk20a: Do not program L2 interruptsTerje Bergstrom2016-05-23
| | | | | | | | | | | | | In gk20a L2 is off when we run L2 floorsweeping function, and the register accesses cause an error. Remove the code to disable L2 comptag interrupt on gk20a. Bug 1741521 Change-Id: I58ee425adf46e80ce4d045750190e930439d419b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1151323
* gpu: nvgpu: Disable big pages for dGPUsTerje Bergstrom2016-05-23
| | | | | | | | | | | | Big pages are not supported by all dGPUs on sysmem. Disable support for all dGPUs for now. Change-Id: I7bdcd9b18845c3d32d40e33220bf9afaf2d8c28e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1150547 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gk20a: fix elpg sysfs controlVijayakumar2016-05-23
| | | | | | | | | | | | | | | | | | bug 200200943 When we enable ELPG through sysfs there is a possibility of refcounting twice as enable ELPG function is done in scheduled work during rail gating exit and also called from sysfs write. Just updating elpg enable/disable flag is good enough as ELPG code uses it during rail gating exit Change-Id: Ibb267d4ce30b9848abcde29882b90d884ef213bb Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1149587 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
* gpu: nvgpu: update trace for sched paramsThomas Fleury2016-05-21
| | | | | | | | | | | | | | Use an inline function instead of a macro to "expand" all channel parameters. Jira EVLR-244 Jira EVLR-318 Change-Id: I4e8c5ee6bc9da36564af171be809f50dd2dfd439 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1150050 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove SOF event generationThomas Fleury2016-05-21
| | | | | | | | | | | | | | | | | | | | | | | | FECS trace are currently collected using periodic polling every 16.66 ms. Whenever polling thread finds some events from FECS, it generates a SOF event with current PTIMER value. These events may introduce out of order timestamps, and extra processing would be required in driver to insert them in the right order. This change removes SOF event generation, as they is currently no use case for them. Bug 1757714 Change-Id: I4343e3b6ab0f0ce03d89244b3195115b3e4a2802 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1139307 (cherry picked from commit 10f0df0a100709ff6fd2cf4ed59f1b04fda837da) Reviewed-on: http://git-master/r/1150049 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix out-of-bound idx for FECS traceThomas Fleury2016-05-21
| | | | | | | | | | | | | | | | | | | Fix a case where user space could potentially see an out of bounds write index for user facing context switch buffer. Check if write_idx is valid, and disable FECS tracing if corrupted. Bug 1757714 Change-Id: I5710c40121fa6935dba3918adf5290488e31e9f6 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1139305 (cherry picked from commit 47b65e5b59037932777be4911fe040e6acbc5651) Reviewed-on: http://git-master/r/1150048 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix deadlock on FECS trace disableThomas Fleury2016-05-21
| | | | | | | | | | | | | | | | | | | | | fecs_trace.disable() method kills polling thread and waits until it completes. dev->lock must not be held while calling this function, as polling thread may attempt to acquire it, leading to a deadlock. Also fixed potential deadlock in ioctl to disable trace. Bug 1758405 Change-Id: I8f6baaba8093ce92961413f6152ee8b81beca3e4 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1139296 (cherry picked from commit 3391a911e1fa9170a5aa989c81bcba6a2f79a9d4) Reviewed-on: http://git-master/r/1150047 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix engine reset in FECS traceThomas Fleury2016-05-21
| | | | | | | | | | | | | | | | | | | In virtualization case, VM server is the only one allowed to write to ctxsw ring buffer. It will also generate an event in case of engine reset. Only generate a tracepoint on Guest OS side. EVLR-314 Change-Id: I2cb09780a9b41237fe196ef1f3515923f36a24a4 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1130743 (cherry picked from commit 4bbf9538e2a3375eb86b2feea6c605c3eec2ca40) Reviewed-on: http://git-master/r/1133614 (cherry picked from commit 2076d944db41b37143c27795b3cffd88e99e0b00) Reviewed-on: http://git-master/r/1150046 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add ctxsw channel reset eventThomas Fleury2016-05-21
| | | | | | | | | | | | | | | | | | Generate a ctxsw channel reset when engine needs to be reset. This event is generated by the driver, while other events are generated by FECS. JIRA ELVR-314 Change-Id: I7791cf3e538782464c37c442c871acb177484566 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1129029 (cherry picked from commit 114038a1a5d9e8941bc53f3e95115b01dd1f8c6e) Reviewed-on: http://git-master/r/1134379 (cherry picked from commit 15fa2a7b48a0937dfd449ca0c4ed5ad3a863d6bf) Reviewed-on: http://git-master/r/1123916 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Enable CE in GR resetTerje Bergstrom2016-05-20
| | | | | | | | | Enable GRCE when enabling GR. Also use the reset mask read from device info instead of using the hard coded value. Change-Id: I4812c32d09ea8b5e07abd1b2c6f1efdbe00cb36e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1149359
* gpu: nvgpu: gp10b: Fix SM number when more than 4 TPCsTerje Bergstrom2016-05-20
| | | | | | | | Use multiplication instead of division to come up with an SM id. Change-Id: I01b76bf1ba5f64e34b6a283306fcd7687c1302ed Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1150600
* gpu: nvgpu: Add HAL op for PMU resetTerje Bergstrom2016-05-20
| | | | | | | | | Sequence to reset PMU is different for iGPU and dGPU. Specialize and implement iGPU version. Change-Id: I5b9ff2c018a736bc9e27b90d0942c52706b12a12 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1150540
* gpu: nvgpu: vgpu: add support for VSM ioctlsPeter Daifuku2016-05-20
| | | | | | | | | | | | | | | | | | Add virtualized support for NUM_VSMS and VSMS_MAPPING ioctls. This requires adding an attribute request for the RM server, GPC0_TPC_COUNT JIRASW EVLR-253 Change-Id: Icaab4fadbbc9eab5d00cf78132928686944162df Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1130615 (cherry picked from commit 78514079382b0de48457db340e3479e99a012040) Reviewed-on: http://git-master/r/1133865 (cherry picked from commit 27a8e645e2787a43d0073f0be6e8f64c0f183228) Reviewed-on: http://git-master/r/1122553 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: hwpm broadcast register supportPeter Daifuku2016-05-19
| | | | | | | | | | | | | | | | | | | | | | | Add support for hwpm broadcast registers (ltc and lts) In gr_gk20a_find_priv_offset_in_buffer, replace "Unknown address type" error with informational message: gr_gk20a_exec_ctx_ops calls gk20a_get_ctx_buffer_offsets and if that fails, calls gr_gk20a_get_pm_ctx_buffer_offsets; HWPM registers will fail the first call, so an error or warning is overkill. Bug 1648200 Change-Id: I197b82579e9894652add4ff254418f818981415a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1131365 (cherry picked from commit 9f30a92c5d87f6dadd34cc37396a6b10e3a72751) Reviewed-on: http://git-master/r/1133628 (cherry picked from commit 7eb7cfd998852ba7f7c4c40d3db286f66e83ab3a) Reviewed-on: http://git-master/r/1127749 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: fix Oops when dt have no mempool-fecs-traceRichard Zhao2016-05-18
| | | | | | | | | | | | | | Avoid unreserving mempool when it didn't reserve successfully. Bug 1757733 Change-Id: I39d36492a54c2e71afff3221505196a463c06776 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1132057 (cherry picked from commit b18060ea30b924c4ef39c05a70d4f03759061128) Reviewed-on: http://git-master/r/1132129 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use mem_desc for semaphoresKonsta Holtta2016-05-18
| | | | | | | | | | | | | | Replace manual buffer allocation and cpu_va pointer accesses with gk20a_gmmu_{alloc,free}() and gk20a_mem_{rd,wr}() using a struct mem_desc in gk20a_semaphore_pool, for buffer aperture flexibility. JIRA DNVGPU-23 Change-Id: I394c38f407a9da02480bfd35062a892eec242ea3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1146684 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use mem_desc in priv_cmd_entryKonsta Holtta2016-05-18
| | | | | | | | | | | | | | | | | Replace the plain cpu pointer accesses with gk20a_mem_wr32(), and use a reference to the underlying mem_desc (within priv_cmd_queue) paired with an offset, for buffer aperture flexibility. JIRA DNVGPU-21 JIRA DNVGPU-23 Change-Id: I317672c94bb682bb895f9ed3e8116729c8bb7f4b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1145922 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Read all fields of device_infoTerje Bergstrom2016-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | | We were not using the engine_type field in device info, and the code did not handle chained entries properly. The code assumed that first entry is for graphics and second for CE, which is not always true. Improve the code to go through all entries of device_info, and preserve values across entries until we reach the last entry. Only last entry triggers a write to fifo engine info. There can also be multiple engines with same type, so accumulate interrupts and reset ids from all of them. As the code got fixed, now it reads the engine enum correctly from hardware. We used to compare that against CE0, but we should compare against CE2. gk20a_fifo_reset_engine() uses wrong constants - it is passed a internal numbering of engines, but it compares them against hardware engine enum. Change-Id: Ia59273921c602d2a090f7a5b1404afb0fca2532c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1147746 Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: remove unbind from debug session bind callDeepak Nibade2016-05-18
| | | | | | | | | | | | | | | | While binding a channel to debug session in dbg_bind_channel_gk20a(), we unbind the channel if channel fd is ~0 But UMD has already moved to use separate IOCTL to unbind a channel from debug session Hence this code can be removed now Bug 1646259 Change-Id: I9e53e4b4c79fbf5468fe083c5b265a84d9695841 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1146852 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reset TSG timeslice params on openAingara Paramakuru2016-05-16
| | | | | | | | | | | | | | | | | The TSG timeslice params were not being reset on open, resulting in timeslices being incorrectly inherited across close->open cycles. Bug 1617046 Change-Id: I5124634fbf058f9f1b57c5c9cc1428db8df4ad43 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1146849 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix CWD floorsweep programmingTerje Bergstrom2016-05-16
| | | | | | | | | | | | | Program CWD TPC and SM registers correctly. The old code did not work when there are more than 4 TPCs. Refactor init_fs_mask to reduce code duplication. Change-Id: Id93c1f8df24f1b7ee60314c3204e288b91951a88 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1143697 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* Revert "gpu: nvgpu: Enable FB before initializing L2"Terje Bergstrom2016-05-13
| | | | | | | | | | | | | This reverts commit df05d2a7c214bc8cdb887f1609853d0f424ef6f1. It causes intermittent failures on laguna_t124. Bug 1766083 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Change-Id: Idabcf96d2eaddc989b029c429cec213bcabbf28c Reviewed-on: http://git-master/r/1147683 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: Do not program max ways evictTerje Bergstrom2016-05-13
| | | | | | | | | | | Setting max_ways_evict reserves some of L2 for CB. In gk20a CB is in dedicated RAM, so we don't need to reserve space for it. The code gets invoked only on gk20a. Change-Id: Ib8efec8c5e90c135bd0c10bb1eaa3f797ec68698 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1144993
* gpu: nvgpu: Add support for multiple PBDMAsLakshmanan M2016-05-13
| | | | | | | | | | | | | | Added support for multiple PBDMAs handling during fifo_pbdma_isr and gk20a_init_fifo_reset_enable_hw use case. JIRA DNVGPU-26 Change-Id: I5f013c5373f7a4b80a8de8863f0e175576ed4c22 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1145591 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not enable L2 bit CYA15Terje Bergstrom2016-05-13
| | | | | | | | | | | | Enabling L2 CYA15 is necessary only in another GPU for enabling an HW fix. gk20a does not have this problem, so enabling CYA15 is not necessary. Change-Id: I7318e8541ad392f9a34f3650beac05a39d7bba68 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1146086 Reviewed-by: Ken Adams <kadams@nvidia.com> Tested-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: refactor gk20a_mem_{wr,rd} for vidmemKonsta Holtta2016-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support vidmem, pass g and mem_desc to the buffer memory accessor functions. This allows the functions to select the memory access method based on the buffer aperture instead of using the cpu pointer directly (like until now). The selection and aperture support will be in another patch; this patch only refactors these accessors, but keeps the underlying functionality as-is. gk20a_mem_{rd,wr}32() work as previously; add also gk20a_mem_{rd,wr}() for byte-indexed accesses, gk20a_mem_{rd,wr}_n() for memcpy()-like functionality, and gk20a_memset() for filling buffers with a constant. The 8 and 16 bit accessor functions are removed. vmap()/vunmap() pairs are abstracted to gk20a_mem_{begin,end}() to support other types of mappings or conditions where mapping the buffer is unnecessary or different. Several function arguments that would access these buffers are also changed to take a mem_desc instead of a plain cpu pointer. Some relevant occasions are changed to use the accessor functions instead of cpu pointers without them (e.g., memcpying to and from), but the majority of direct accesses will be adjusted later, when the buffers are moved to support vidmem. JIRA DNVGPU-23 Change-Id: I3dd22e14290c4ab742d42e2dd327ebeb5cd3f25a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1121143 Reviewed-by: Ken Adams <kadams@nvidia.com> Tested-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: use correct ltc cnt in hwpm offset mapPeter Daifuku2016-05-12
| | | | | | | | | | | | | | | | Fix the offset calculation code to save/restore proper number of LTCs to conform to FECS microcode Bug 1736910 Change-Id: I46ae1e0b45ffe354693db6ceb0aeeeac3d344b34 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1133896 (cherry picked from commit 97751ee7a44537f5aa5198ac362d9ee416adc172) Reviewed-on: http://git-master/r/1146244 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use num LTCs instead of num FBs in GRTerje Bergstrom2016-05-11
| | | | | | | | | When programming GR ZROP and CROP settings for number of active LTCs we use FB count, which is always 1. Use LTC count instead. Change-Id: I4d6f9b2b59d44b82ba098b243d6390cf321dbc36 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1144698
* gpu: nvgpu: add fuse overrides for tpc disablingRichard Zhao2016-05-10
| | | | | | | | | | | | | | | | | - add fuse_override in gops. Implement it starting from gm20b. - set cwd fs register, so cuda won't use disabled TPCs Bug 1757262 Bug 200169697 Change-Id: If7bac58bd3a6bcf2925197ea5b7c2d10a77e0933 Signed-off-by: Richard Zhao <rizhao@nvidia.com> (cherry picked from commit 66cde7724815e9e5e85ab9b07fc985a78530222f) Reviewed-on: http://git-master/r/1132177 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Tested-by: Adeel Raza <araza@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 12:02:24 -0500