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* gpu: nvgpu: skip channel status verification if TSG has timed outDeepak Nibade2017-10-29
| | | | | | | | | | | | | | | | | | | In gk20a_fifo_tsg_unbind_channel(), we always verify channel status before unbinding a channel from TSG But in case TSG has alread timed out we never re-enable it so it does not make sense to inspect channel status anyways So skip channel status verification in case TSG has timed out Bug 200327095 Change-Id: Iccf601271290643c235c3f2656201549210a6886 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586015 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: unset verify status ctx reloadAparna Das2017-10-29
| | | | | | | | | | | | | | | Native code for verifying tsg status on ctx reload is not possible on vgpu. Unset gops->fifo.tsg_verify_status_faulted operation for vgpu for now. This needs to be implemented separately for vgpu later. Bug 200348087 Change-Id: I73791401de1ce7b7f8644ea4f9ccae3fc51dc7aa Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585783 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: use kernel overlay featuresStephen Warren2017-10-29
| | | | | | | | | | | | | | | | Update all Kconfig files and Makefiles to rely on the kernel overlay feature. In particular, don't include any Kconfig files or Makefiles from other overlays. -I directives in CFLAGS are not yet cleaned up. Bug 1978395 Change-Id: I449ed2f07949785f2dd90a6833f4d8cd1711519a Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566641 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable IRQs before preparing powering downThomas Fleury2017-10-29
| | | | | | | | | | | | | | | | Disable IRQs and wait for completion before preparing powering down. This avoids concurrency with threaded interrupts. JIRA EVLR-1852 Change-Id: Iab4cfb0e796b5748430d38daa2a3be8c03b10fff Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563896 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow suspend when jobs are pendingThomas Fleury2017-10-29
| | | | | | | | | | | | | | | | | | | | | | We currently check that no job is pending before proceeding with suspend. This prevents suspend, when we could simply disable and preempt all channels. Moreover, pending jobs accounting is done using pm_runtime usage count, which is not updated for GPUs with pm_runtime disabled (e.g. vgpu). Replaced the check on pm_runtime usage count, with a check on gk20a handle usage count. Suspend is allowed when there is no task inside a busy/idle sequence. JIRA EVLR-1852 Change-Id: I79e71c8112182622dbd1c7c46cd84befa61a5c4d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1552348 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow suspend when engine is busyThomas Fleury2017-10-29
| | | | | | | | | | | | | | | | | We currently check that engine is idle before proceeding with suspend. This prevents suspend when we could simply disable and preempt all channels. Moreover, doing such a check in virtualization case, would require to query engine status from RM server, before proceeding with suspend. Removed check on engine idle for system suspend. JIRA EVLR-1852 Change-Id: Ic6dc65af14b00f236db20038dfc04fa0928c1fe2 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1552347 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete os_linux.h include in mm_gk20a.cAlex Waterman2017-10-27
| | | | | | | | | | | | | | | | | Delete this Linux include from mm_gk20a.c since it is no longer needed! JIRA NVGPU-30 Change-Id: Idb25fce221dbda0936cad4bae3785f7ecf26a1ed Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586330 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove Linux headers from mm_gk20a.hAlex Waterman2017-10-27
| | | | | | | | | | | | | | | | | | | | | | | | | Delte the Linux headers and make some modifications to get rid of the minor compilation issues that resulted. - Add <linux/iommu.h> to os_linux.h - Delete #if 0 code that "flushed" a buffer in gr_gk20a.c - Delete FLUSH_CPU_DCACHE() macro - Move the cache flush definitions to <nvgpu/linux/vm.h> and include this header in sim_gk20a.c. This file will not be used by QNX so this should be fine. - Add <linux/pci_ids.h> to gp106/bios_gp106.c and gp106/mclk_gp106.c. - Move function to common/linux/dmabuf.h since it is a dmabuf related function and uses a struct device pointer as an argument. JIRA NVGPU-30 Change-Id: I11f56b98524c7fac3efa91b4686592130e5f8a46 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585510 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Protect tegra_clk behind CCF flagTerje Bergstrom2017-10-27
| | | | | | | | | | | | | | | | | | clk_gk20a.h is used for dGPU and iGPU clocks. Because in gm20b the clocks are owned by nvgpu, it has references to Linux CCF. Protect the references behind #ifdef CONFIG_COMMON_CLK to compile it out on non-Linux platforms. JIRA NVGPU-259 Change-Id: I6ff095de7acaf1f828897cf3416acfaf050f8b51 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586414 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gpu clk is supported by bpmpSeema Khowala2017-10-27
| | | | | | | | | | | | | | | | | | gpu clk is supported by bpmp for simulation environment as well Bug 1935618 Change-Id: I2a4139164c31788af6a0ba2d73e356769cd5fa0e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586428 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: halify size of patch bufferDavid Nieto2017-10-26
| | | | | | | | | | | | | Allow per chip calculation of gr patch buffer size and set default to match hw default of 512 data-address pair entries (4K) bug 200350539 Change-Id: I6010c9e0304332825cb02612d3f10523ef27d128 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1584033 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: gp10b: add gfxp_wfi_timeout sysfs nodeJonathan McCaffrey2017-10-26
| | | | | | | | | | | | | | | | | | | | Add a sysfs node to allow root user to set PRI_FE_GFXP_WFI_TIMEOUT, for gp10b only, in units of sysclk cycles. Store the set value in a variable, and write the set value to register after GPU is un-railgated. NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT is engine_reset after Bug 1623341. Change default value to be specified in cycles, rather than time. This value is almost the current value in cycles calculated each boot. Bug 1932782 Change-Id: I0a4207e637cd1413a1be95abe2bcce3adccf76fa Reviewed-on: https://git-master.nvidia.com/r/1540939 Signed-off-by: Jonathan McCaffrey <jmccaffrey@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1580999 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Linux specific GPU characteristics flagsTerje Bergstrom2017-10-26
| | | | | | | | | | | | | Make GPU characteristics flags specific to Linux code only. The rest of driver is moved to using nvgpu_is_enabled() API. JIRA NVGPU-259 Change-Id: I2faf46ef64c964361c267887b28c9d19806d6d51 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583876 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Linux specific sm_error_state_recordTerje Bergstrom2017-10-26
| | | | | | | | | | | | | | Create an nvgpu internal nvgpu_gr_sm_error_state to store and propagate SM error state within driver. Use nvgpu_dbg_gpu_sm_error_state_record only in Linux code. JIRA NVGPU-259 Change-Id: I7365cdf5a1a42cbcdb418dfcef3e0020e02a960f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585645 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Silence extra mm debug messagesTerje Bergstrom2017-10-26
| | | | | | | | | | | | common/mm/mm.c uses nvgpu_info() to log debug events. Replace that with nvgpu_dbg_info() to silence the messages. Change-Id: Iaa5b8192287e8392a32ceff2216faf12fd6d09c3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585440 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: don't re-enable TSG if timed outDeepak Nibade2017-10-26
| | | | | | | | | | | | | | | | | | | | | | | | In gk20a_fifo_tsg_unbind_channel(), we disable/preempt TSG, unbind one channel from TSG, and then re-enable rest of the channels in TSG But it is possible that TSG has already timed out due to some error and is already disabled If we re-enable all channels in such case, it can cause random issues right after re-enabling faulted channel Hence do not re-enable TSG if it has timedout Since we disable all channels of TSG if one channel encounters fatal error, it is safe to assume that TSG has timed out if one channel has timed out Bug 1958308 Bug 200327095 Change-Id: I958ca6a2b408ff1338f2e551a79c072f1e203eda Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585421 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add max_css_buffer_size characteristicPeter Daifuku2017-10-25
| | | | | | | | | | | | | | | | | | | | | | | | Add max_css_buffer_size to gpu characteristics. In the virtual case, the size of the cycle stats snapshot buffer is constrained by the size of the mempool shared between the guest OS and the RM server, so tools need to find out what is the maximum size allowed. In the native case, we return 0xffffffff to indicate that the buffer size is unbounded (subject to memory availability), in the virtual case we return the size of the mempool. Also collapse native init_cyclestats functions to a single version, as each chip had identical versions of the code. JIRA ESRM-54 Bug 200296210 Change-Id: I71764d32c6e71a0d101bd40f274eaa4bea3e5b11 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1578930 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move clk_arb to linux specificMahantesh Kumbar2017-10-25
| | | | | | | | | | | | | | | | | - Clock arbiter has lot of linux dependent code so moved clk_arb.c to common/linux folder & clk_arb.h to include/nvgpu/clk_arb.h, this move helps to unblock QNX. - QNX must implement functions present under clk_arb.h as needed. JIRA NVGPU-33 Change-Id: I38369fafda9c2cb9ba2175b3e530e40d0c746601 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582473 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialize czf_bypass only onceDeepak Nibade2017-10-25
| | | | | | | | | | | | | | | | | | | | We right now initialize czf_bypass value in gr_gp10b_init_preemption_state() which is run at every rail ungate And that results in any user specified value through sysfs getting lost after railgate To fix this, move initialization of czf_bypass to gk20a_init_gr_setup_sw() so that it gets initialized only once Add new HAL g->ops.gr.init_czf_bypass to initialize same and define it for gp10b/gp106/vgpu-gp10b Bug 2008262 Change-Id: I80a38ef527c86e32c6d64d0626b867239db9ea51 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585224 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check gpfifo before submit workDebarshi Dutta2017-10-25
| | | | | | | | | | | | | | User can call submit IOCTL before alloc_gpfifo IOCTL and can easily cause a kernel panic. The fix checks for a valid gpfifo.mem before proceeding with the submitted work. Bug 1968309 Change-Id: I5c1fc6f52b25426cd45e58e8b2e0e5bc6aa0c32f Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1584519 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix race in PMU state transitions.Deepak Goyal2017-10-25
| | | | | | | | | | | | | | | | | | | | | PMU response(intr callback for messages) can run faster than the kthread posting commands to PMU. This causes the PMU message callback to skip important pmu state change(which happens just after the PMU command is posted). Solution: State change should be triggered from only inside the intr callback. Other places can only update the pmu_state variable. This change also adds error check to print in case command post fails. JIRA GPUT19X-20 Change-Id: Ib0a4275440455342a898c93ea9d86c5822e039a7 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583577 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use full system barrier in BAR1 testThomas Fleury2017-10-25
| | | | | | | | | | | | | | | | | BAR1 test could occasionally fail when doing CPU write through userd then reading back through BAR1. This is because nvgpu_smp_mb() only guarantees ordering between cores. Replaced with nvgpu_mb() to ensure the write will be visible to all bus masters in the system. JIRA EVLR-1959 Bug 200352099 Change-Id: Id002e73d135e0805fca2f153a6de77e210a7b226 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582928 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Begin reorganizing VM mapping/unmappingAlex Waterman2017-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move vm_priv.h to <nvgpu/linux/vm.h> and rename nvgpu_vm_map() to nvgpu_vm_map_linux(). Also remove a redundant unmap function from the unmap path. These changes are the beginning of reworking the nvgpu Linux mapping and unmapping code. The rest of this patch is just the necessary changes to use the new map function naming and the new path to the Linux vm header. Patch Series Goal ----------------- There's two major goals for this patch series. Note that these goals are not achieved in this patch. There will be subsequent patches. 1. Remove all last vestiges of Linux code from common/mm/vm.c 2. Implement map caching in the common/mm/vm.c code To accomplish this firstly the VM mapping code needs to have the struct nvgpu_mapped_buf data struct be completely Linux free. That means implementing an abstraction for this to hold the Linux stuff that mapped buffers carry about (SGT, dma_buf). This is why the vm_priv.h code has been moved: it will need to be included by the <nvgpu/vm.h> header so that the OS specific struct can be pulled into struct nvgpu_mapped_buf. Next renaming the nvgpu_vm_map() to nvgpu_vm_map_linux() is in preparation for adding a new nvgpu_vm_map() that handles the map caching with nvgpu_mapped_buf. The mapping code is fairly straight forward: nvgpu_vm_map does OS generic stuff; each OS then calls this function from an nvgpu_vm_map_<OS>() or the like that does any OS specific adjustments/management. Freeing buffers is much more tricky however. The maps are all reference counted since userspace does not track buffers and expects us to handle this instead. Ugh! Since there's ref-counts the free code will require a callback into the OS specific code since the OS specific code cannot free a buffer directly. THis make's the path for freeing a buffer quite convoluted. JIRA NVGPU-30 JIRA NVGPU-71 Change-Id: I5e0975f60663a0d6cf0a6bd90e099f51e02c2395 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1578896 GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Cleanup generic MM code in gk20a/mm_gk20a.cAlex Waterman2017-10-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move much of the remaining generic MM code to a new common location: common/mm/mm.c. Also add a corresponding <nvgpu/mm.h> header. This mostly consists of init and cleanup code to handle the common MM data structures like the VIDMEM code, address spaces for various engines, etc. A few more indepth changes were made as well. 1. alloc_inst_block() has been added to the MM HAL. This used to be defined directly in the gk20a code but it used a register. As a result, if this register hypothetically changes in the future, it would need to become a HAL anyway. This path preempts that and for now just defines all HALs to use the gk20a version. 2. Rename as much as possible: global functions are, for the most part, prepended with nvgpu (there are a few exceptions which I have yet to decide what to do with). Functions that are static are renamed to be as consistent with their functionality as possible since in some cases function effect and function name have diverged. JIRA NVGPU-30 Change-Id: Ic948f1ecc2f7976eba4bb7169a44b7226bb7c0b5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574499 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move preempt query functionsTerje Bergstrom2017-10-23
| | | | | | | | | | | | Move functions to query preemption type names to the user of the function: ioctl_channel.c. This removes a dependency to <uapi/linux/nvgpu.h> from gr_gk20a.h. JIRA NVGPU-259 Change-Id: I6cafda986eb4659fcfc1b19eac77e43aaaeaec76 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1577248
* gpu: nvgpu: Move function to query rl interleaveTerje Bergstrom2017-10-23
| | | | | | | | | | | | Function to query interleave name depends on IOCTL flag definition. Move that code to fifo_gk20a.c to remove Linux dependency in header. Change-Id: I6d6a80e550bf30973b2be09febc2347890b77d25 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1577249 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: enhance class error debug infoseshendra Gadagottu2017-10-23
| | | | | | | | | | | | | | | | | | | | | | | | | Updated gk20a_gr_handle_class_error with sub channel info, mme related info. Also printing the correct method info from isr_data->offset by left shifting it by 2. Generated following hw definitions for gk20a/gm20b/gp10b/gp106 to dump relevant data in gk20a_gr_handle_class_error: gr_trapped_addr_mme_generated_v gr_trapped_addr_datahigh_v gr_trapped_addr_priv_v gr_trapped_data_lo_r gr_trapped_data_mme_r gr_trapped_data_mme_pc_v Bug 2003671 Change-Id: I02e15ef16d7498b6a7dc2af547a14e84d570e8a7 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574061 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix vidmem regressionDavid Nieto2017-10-23
| | | | | | | | | | | | | | Ensures all vidmem mutex are init bug 2004378 Change-Id: I2ffb1d8e99ecb269b36e5ea79d08db2021e54302 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583196 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add cache maintenance timeout overrideDavid Nieto2017-10-23
| | | | | | | | | | | | Add functions to get per-chip cache maintenance timeout overrides. JIRA: NVGPUGV100-GV100 Change-Id: Ie14efc616e7af52ede60031c789bd2ae70857a6e Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582768 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon interface/HAL updateMahantesh Kumbar2017-10-21
| | | | | | | | | | | | | | | | | | | - Add methods to read/write falcon mailbox at interface layer - Created falcon mailbox read/write HAL - Added HAL methods to read/write mailbox - Added macro to get next block based on address - Added macro to get IMEM tag using IMEM address - Added ucode header format Change-Id: I879b1df4538d403cac40fd4ed6e723190f62922c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> (cherry picked from commit 30e8b76a7be9d9e6d8225bdc08e441f408692f63) Reviewed-on: https://git-master.nvidia.com/r/1509469 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: memory unlock HAL supportMahantesh Kumbar2017-10-21
| | | | | | | | | | | | | | | | - Created "mem_unlock" HAL under fb to support memory unlock - Called as part of gk20a_finalize_poweron() if memory unlock support needed by checking HAL - Assigned "mem_unlock" HAL to NULL for chips which don't need memory unlocks. Change-Id: I68d0910f15d293feaacfcbf6bd17ecccd3b5219d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> (cherry picked from commit 586894eb84860bbbe4c75dae4715bdf27432a480) Reviewed-on: https://git-master.nvidia.com/r/1564703 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add nvdec falcon supportMahantesh Kumbar2017-10-21
| | | | | | | | | | | | | | | | - Added "nvgpu_flacon nvdec_flcn" member to gk20a - Added base address & flacon id of NVDEC falcon - Included nvdec falcon to access common falcon code - Enabled nvdec falcon support for GP106 - Disabled nvdec falcon support for iGPU - Made call to enable nvdec falcon support if supported Change-Id: Ia928d082275a720e4e8c6852384e489c8ec444f8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> (cherry picked from commit 3d80aeff295bad8365af6022555ad151f1a32cf6) Reviewed-on: https://git-master.nvidia.com/r/1564305 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reset patch_ctx.data_countSeema Khowala2017-10-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch buffer can hold 128 u32 entries. Each patch write takes total of 2 u32 entries, 1 u32 for addr and 1 u32 for data. Ideally 64 entries could be written before buffer overflows. Driver patch some things when creating the channel, and later when context switch type is changed after channel is loaded. Reset patch_ctx.data_count before beginning patch write otherwise system might not be in a state to accept all patch writes even if patch buffer has valid entries. If the patch buffer has non-zero entries, then the patch buffer would be read and all pri writes would be sent out. Once done, ucode updates the main header patch buffer count to 0. Without this fix, below priv errors seen on t186 platforms SYS Write error for ADR 0, INFO 0d000200 and CODE badf1100 Error info decodes as: NV_PPRIV_SYS_PRIV_ERROR_INFO R[0x00122128] SUBID [29:24] 13 (?) LOCAL_ORDERING [22:22] 0 (I) PRIV_LEVEL [21:20] 0 (I) SENDING_RS [17:12] 0 (I) PENDING [ 9: 9] 1 (?) ORPHAN [ 8: 8] 0 (I) PRIV_MASTER [ 5: 0] 0 (I) Ctxsw ucode(subid 13 i.e. 0xd) makes only few pri transactions at priv level 0. Patch buffer pri writes are one of those. Bug 200350539 Change-Id: If9e71b5fef4d85600d72a8a633a082d9261c3e1b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1581591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use priv_ring.isr gopsSeema Khowala2017-10-21
| | | | | | | | | | | | | | | Use priv_ring.isr gops to call priv ring interrupt handler Bug 200350539 Change-Id: I21b39bd19d281290fee6728286b0a24a32358ae4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570372 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add VIDMEM debuggingAlex Waterman2017-10-20
| | | | | | | | | | | | | | Add some VIDMEM debugging to help track the background free thread and allocs/frees. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I88471b29d2a42c104666b111d0d3014110c9d56c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1576330 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Convert VIDMEM work_struct to threadAlex Waterman2017-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the work_struct used by the vidmem background clearing to a thread to make it more cross platform. The thread waits on a condition variable to determine when work needs to be done. The signal comes from the DMA API when it enqueues a new nvgpu_mem that needs clearing. Add logic for handling suspend: the CE cannot be accessed while the GPU is suspended. As such the background thread must be paused while the GPU is suspended and the CE is not available. Several other changes were also made: o Move the code that enqueues a nvgpu_mem from the DMA API code to a function in the VIDMEM code. o Move nvgpu_vidmem_get_pending_alloc() to the Linux specific code as this function is only used there. It's a trivial function that QNX can easily implement as well. o Remove the was_empty logic from the enqueue. Now just always signal the condition variable when anew nvgpu_mem comes in. o Move CE suspend to after MM suspend. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: Ie9286ae5a127c3fced86dfb9794e7d81eab0491c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574498 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle smid table init failuresDavid Nieto2017-10-20
| | | | | | | | | | | | | | | Handle the possibility of failing gr init due to smid table initialization failures bug 2004378 Change-Id: I904b918a0ea31c32292edb3ab8ac3b1459c38a28 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1581661 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove HAL for restore_context_headerseshendra Gadagottu2017-10-20
| | | | | | | | | | | | | Remove unused HAL for restore_context_header. This function pointer is not getting used since no need for restoring context header during golden context creation. Change-Id: I0fb018226c7560fdb69f77a4f53387d39cc79e97 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1581431 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move sched to be Linux specificTerje Bergstrom2017-10-20
| | | | | | | | | | | | Move sched parameter APIs to be Linux specific implementation. At the same time the sched_ctrl fields were moved to nvgpu_os_linux. JIRA NVGPU-259 Change-Id: I2397e2602e1c4783f2bebf3aec462634b7f86d4a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1580649 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: reset perfmon correctlyseshendra Gadagottu2017-10-20
| | | | | | | | | | | | | Use mc reset HAL function to reset perfmon unit. This will take care of delays after writing to mc_enable register. Change-Id: I6118bdd2a9fc9192f7ffc44617a170b7982c26ba Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1581753 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not #include uapi in ecc_gk20a.hTerje Bergstrom2017-10-19
| | | | | | | | | | | | | | | ecc_gk20a.h has no use for Linux IOCTL interface definitions. Remove the stray #include. JIRA NVGPU-259 Change-Id: I47a837ac86f1f83976d94cb9b30082fee827445a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1580678 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Remove Linux code from BoardobjMahantesh Kumbar2017-10-18
| | | | | | | | | | | | | | | - Removed Linux headers included in boardobj.c JIRA NVGPU-136 Change-Id: I37d4f7134e17f21c83bbff58ae12f52efb1e829f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579670 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Refactoring nvgpu_vm functionsAlex Waterman2017-10-18
| | | | | | | | | | | | | | | | | | | | Refactor the last nvgpu_vm functions from the mm_gk20a.c code. This removes some usages of dma_buf from the mm_gk20a.c code, too, which helps make mm_gk20a.c less Linux specific. Also delete some header files that are no longer necessary in gk20a/mm_gk20a.c which are Linux specific. The mm_gk20a.c code is now quite close to being Linux free. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I72b370bd85a7b029768b0fb4827d6abba42007c3 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566629 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move dma_buf usage from mm_gk20a.cAlex Waterman2017-10-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move most of the dma_buf usage present in the mm_gk20a.c code out to Linux specific code and some commom/mm code. There's two primary groups of code: 1. dma_buf priv field code (for holding comptag data) 2. Comptag usage that relies on dma_buf pointers For (1) the dma_buf code was simply moved to common/linux/dmabuf.c since most of this code is clearly Linux specific. The comptag code was a bit more complicated since there is two parts to the comptag code. Firstly there's the code that manages the comptag memory. This is essentially a simple allocator. This was moved to common/mm/comptags.c since it can be shared across all chips. The second set of code is moved to common/linux/comptags.c since it is the interface between dma_bufs and the comptag memory. Two other fixes were done as well: - Add struct gk20a to the comptag allocator init so that the proper nvgpu_vzalloc() function could be used. - Add necessary includes to common/linux/vm_priv.h. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I96c57f2763e5ebe18a2f2ee4b33e0e1a2597848c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566628 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allocate syncpoint read map only onceseshendra Gadagottu2017-10-18
| | | | | | | | | | | | | | Allocate syncpt_mem only if is not allocated. JIRA GPUT19X-2 Change-Id: I081d27bb784fbe653890b5f8d36a4295c7ccc19b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1580731 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use nvgpu_rwsem as TSG channel lockTerje Bergstrom2017-10-17
| | | | | | | | | | | | | Use abstract nvgpu_rwsem as TSG channel list lock instead of the Linux specific rw_semaphore. JIRA NVGPU-259 Change-Id: I41a38b29d4651838b1962d69f102af1384e12cb6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579935 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: cleanup of dbg_gpu_gk20aDebarshi Dutta2017-10-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change contains a generic cleanup of linux dependent parts of the dbg_gpu_gk20a.* files. The following changes have been made 1) Moving methods into ioctl_dbg.* inside common/linux/ 2) The structures dbg_session_gk20a and dbg_session_channel_data have been split into two parts. struct device *dev is removed from struct dbg_session_gk20a and instead packed into struct dbg_session_gk20a_linux alongwith dbg_session_gk20a and is moved into ioctl_dbg. dbg_session_gk20a is now rid of any linux dependencies and remains in dbg_gpu_gk20a. Similarly, struct file is removed from struct dbg_session_channel_data and is now packed into struct dbg_session_channel_data_linux alongwith dbg_session_channel_data and is moved into ioctl_dbg. struct dbg_session_channel_data is now rid of linux dependencies and remains in dbg_gpu_gk20a. 3) A callback function is added in order to release the dbg_session_channel_data. JIRA NVGPU-205 Change-Id: I853da6dfbf9a96b7cd210beb77f2304445ff7ea6 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1575191 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move rest of CDE structures to LinuxTerje Bergstrom2017-10-17
| | | | | | | | | | | | | | Move rest of CDE structures to common/linux. This includes moving the per-chip firmware file interpretation functions, and removing CDE ops from HAL and adding it to nvgpu_os_linux. JIRA NVGPU-259 Change-Id: I59d8f44bddadecef81ad3c455b363a14034c5e13 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570403 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use internal nvgpu_warpstateTerje Bergstrom2017-10-17
| | | | | | | | | | | | | Replace use of ioctl structure warpstate with internal nvgpu_warptate. JIRA NVGPU-259 Change-Id: I5170364d0443235cee471b87fa332fc09588f5d3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1578684 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: fix multiple build issues for QNXShashank Singh2017-10-17
| | | | | | | | | | | | | | | | | | - timers and bug header files should be included directly. Linux maybe getting it via indirect includes. Also, QNX requires non-static function to be declared explicitly. Change-Id: I2458654f535d8079347e4a0be744530f56388238 Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1577527 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Tested-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 02:08:33 -0500