| Commit message (Collapse) | Author | Age |
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Add a translation layer to convert from the NVGPU_AS_* flags to
to new set of NVGPU_VM_MAP_* and NVGPU_VM_AREA_ALLOC_* flags.
This allows the common MM code to not depend on the UAPI header
defined for Linux.
In addition to this change a couple of other small changes were
made:
1. Deprecate, print a warning, and ignore usage of the
NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS flag.
2. Move the t19x IO coherence flag from the t19x UAPI header
to the regular UAPI header.
JIRA NVGPU-293
Change-Id: I146402b0e8617294374e63e78f8826c57cd3b291
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599802
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Most of VGPU code is linux specific but lies in common code
So until VGPU code is properly abstracted and made os-independent,
move all of VGPU code to linux specific directory
Handle corresponding Makefile changes
Update all #includes to reflect new paths
Add GPL license to newly added linux files
Jira NVGPU-387
Change-Id: Ic133e4c80e570bcc273f0dacf45283fefd678923
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599472
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Commit 81868a187fa3b217368206f17b19309846e8e7fb updated barrier
usage to use the nvgpu wrappers and in doing so downgraded many
plain barriers {mb(), wmb(), rmb()} to the SMP versions of these
barriers.
The SMP version of the barriers in question are only issued
when running on an SMP machine. In most of the cases mentioned
above this is fine since the barriers are present to faciliate
proper ordering across CPUs. A single CPU is always coherent
with itself, so on a non-SMP case we don't need those barriers.
However, there are a few places where the barriers in use (GMMU
page table programming, IO accessors, userd) where the barrier
usage is for communicating and establishing ordering for the
GPU. We need these barriers for both SMP machines and non-SMP
machines. Therefor we must use the plain barrier versions.
Change-Id: I376129840b7dc64af8f3f23f88057e4e81360f89
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599744
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Remove #include of <uapi/linux/nvgpu.h> from gr_gk20a.h.
vgpu_mm_gp10b.c uses UAPI definitions, so add an explicit #include
there.
JIRA NVGPU-363
Change-Id: Ieabd7240d62495d2719d7fdbc25cc238de13c75e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598981
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gk20a.h refers to nvgpu_ctxsw_trace_filter, which is defined in
another header. Add a forward declare to remove the dependency.
JIRA NVGPU-363
Change-Id: I537b6005eb65c4d44799d0f72deced5ec54bc99b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598980
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reg_op_is_* static inline force a dependency to UAPI in
regops_gk20a.h. Change the implementation to be functions
in .c file.
JIRA NVGPU-388
Change-Id: If5cae1ad011a26ee5ff23e1e39aac3d88fd5bb98
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598979
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nvgpu_pde_phys_addr() is only used in gmmu.c and as such can be
marked static.
JIRA NVGPU-402
Change-Id: I7adba6f54ebd4e06d176f23b9a959c04a8770338
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599040
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Remove a forward declaration of dma_buf in <nvgpu/vm.h>. This
forward declaration is no longer necessary since all usage of
dma_bufs has been removed from common code!
JIRA NVGPU-224
JIRA NVGPU-30
Change-Id: I0948d8b99efc6429f7a6d122ef3655d670205d75
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598934
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Always allocate explicitly zeroed DMA memory and remove the
unnecessary memset() from the alloc path for memory with a
kernel mapping.
JIRA NVGPU-418
Change-Id: I5a3df6e6969e2586df41b72325d1bff1e40206e6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598933
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It'll make the code be able to apply to gv11b too.
Jira EVLR-1671
Change-Id: I9a960fd1aaa9adc6bb39aa2c730049e75006fea7
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597379
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For gp10b and previous chips, RM server will issue fake mmu fault to
reset the channel. And the mmu fault event will be sent to vgpu client,
which will cause the client to abort the channel or tsg.
But on gv11b, RM server doesn't issue fake mmu fault any more. So I need
to abort it right after the force reset is finished.
Jira EVLR-1671
Change-Id: I11399fda84d31086ba1d4ffde5948e409cde2a28
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597378
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We no longer use code in nvgpu-t19x or t19x repo, so remove obsolete includes
from Makefile
Bug 200363166
Change-Id: I29e78931e90e0afffecf756bf7479ed8784dbc25
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599470
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linux-nvgpu
Bug 200363166
Change-Id: Ic662d7b44b673db28dc0aeba338ae67cf2a43d64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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Call nvgpu_dma_alloc_flags_sys without
NVGPU_DMA_NO_KERNEL_MAPPING flags, since
it makes CMA memory handling simple in t194
and fixes error during subcontext header free:
[ 340.378910] trying to free invalid coherent area: ffffffc0135ba000^M
[ 340.378921] ------------[ cut here ]------------^M
[ 340.378933] WARNING: CPU: 0 PID: 1618 at /code/volta/kernel/kernel-4.9/arch/arm64/mm/dma-mapping.c:1442 __arm_dma_free.isra.4+0x160/0x168^M
[ 340.378950] Modules linked in: nvgpu^M
[ 340.378958] ^M
[ 340.378966] CPU: 0 PID: 1618 Comm: nvogtest Tainted: G W 4.9.52-tegra-g170e0c4 #20^M
[ 340.378979] Hardware name: t194pre_si (DT)^M
[ 340.378988] task: ffffffc018930d80 task.stack: ffffffc017e08000^M
[ 340.378999] PC is at __arm_dma_free.isra.4+0x160/0x168^M
[ 340.379009] LR is at __arm_dma_free.isra.4+0x160/0x168^M
[ 340.379020] pc : [<ffffff800809cfd0>] lr : [<ffffff800809cfd0>] pstate: 60400045^M
[ 340.379032] sp : ffffffc017e0bbe0^M
[ 340.379039] x29: ffffffc017e0bbe0 x28: 00000000935ba000 ^M
[ 340.379051] x27: 0000000000001000 x26: ffffffc0135b9580 ^M
[ 340.379063] x25: ffffff8009ced1b0 x24: 0000000000000010 ^M
[ 340.379075] x23: ffffffc070746010 x22: 0000000080000000 ^M
[ 340.379088] x21: ffffffbf004d6e80 x20: ffffffc0135ba000 ^M
[ 340.379100] x19: 0000000000001000 x18: ffffffffffffffff ^M
[ 340.379112] x17: 0000007fa4d8fc60 x16: ffffff800823e370 ^M
[ 340.379124] x15: ffffff8009cd8690 x14: ffffff8089fb34bf ^M
[ 340.379135] x13: ffffff8009fb34cd x12: 0000000000000007 ^M
[ 340.379147] x11: 0000000000000325 x10: 0000000005f5e0ff ^M
[ 340.379159] x9 : 0000000000000326 x8 : 3331306366666666 ^M
[ 340.379172] x7 : 6666203a61657261 x6 : ffffff8009fb3505 ^M
[ 340.379184] x5 : 0000000000000012 x4 : 0000000000000000 ^M
[ 340.379196] x3 : 0000000000010000 x2 : 0000000000040934 ^M
[ 340.379207] x1 : 0000000000000000 x0 : 0000000000000036 ^M
[ 340.379219] ^M
[ 340.379224] ---[ end trace 9e7ab41f55eb32d2 ]---^M
[ 340.379232] Call trace:^M
[ 340.379241] [<ffffff800809cfd0>] __arm_dma_free.isra.4+0x160/0x168^M
[ 340.379254] [<ffffff800809e3a0>] arm_dma_free+0x48/0x60^M
[ 340.379827] [<ffffff8000f01250>] nvgpu_dma_free+0x260/0x410 [nvgpu]^M
[ 340.380403] [<ffffff8000fb2fac>] gv11b_free_subctx_header+0x5c/0x80 [nvgpu]^M
[ 340.380980] [<ffffff8000f3ed2c>] gk20a_free_channel_ctx+0x3c/0x150 [nvgpu]^M
After changing dma alloc flags to none, this issue got fixed.
Bug 1930032
Change-Id: I002236373c6a3ae5d7ec80a35f166429821662b7
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598193
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using
combination of timeslice and interleave levels to decide the priority
Hence remove the IOCTLs and all corresponding APIs
Jira NVGPU-393
Change-Id: Idce925631653784e39864223dc418a99a7e7ca3c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598582
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Check for interrupts or hangs while waiting for the preempt to complete.
During pbdma/eng preempt done polling, any stalling interrupts relating
to the runlist must be detected and handled in order for the preemption
to complete.
When PBDMA fault or CE fault occurs, the PBDMA will save out
automatically. TSG related to the context in which the fault occurred
will not be scheduled again until the fault is handled.
In the case of some other issue requiring the engine to be reset, TSG
will need to be manually preempted.
In all cases, a PBDMA interrupt may occur prior to the PBDMA being able to
switch out. SW must handle these interrupts according to the relevant handling
procedure before the PBDMA preempt can complete.
Opt for eng reset instead of waiting for preemption to be finished when
there is any stall interrupt pending during engine context preempt completion.
Bug 200277163
Bug 1945121
Change-Id: Icaef79e3046d82987b8486d15cbfc8365aa26f2e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522914
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Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
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-Program mc_elpg_enable and mss nvlink soc credits only
when bpmp is not running or bpmp is running but underlying
platorm is simulation. For simulation, bpmp does not execute
hot reset sequence. As part of gpu unpowergate, bpmp will
program mc_elpg_enable and also set mss nvlink soc credits
after bringing mss nvlink out of reset
-Remove updating mc_enable as writes to this register has no
effect
-Remove fifo_fb_iface_r read/write. This hack was added during
initial bring up of emulation platforms
Bug 2018223
Bug 200269361
Change-Id: Ie09c259e48295a93c6d15376308186152db973fa
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594495
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Use NETD firmware on gv11b.
GV11B_NETLIST_IMAGE_FW_NAME set to GK20A_NETLIST_IMAGE_D
Change-Id: I0301999851ffb14713beaf61b5b2cc97efac74eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597290
Reviewed-by: Automatic_Commit_Validation_User
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Use common preemption modes in common code instead of using linux specific
definitions
Jira NVGPU-392
Change-Id: Iff65ab4278973f2e2d7db33f6fedb561b2164c42
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596931
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- Update commit_global_timeslice to remove unused patch parameter
- Update calls to ctx_patch_write_begin/end to add update_patch_count param
JIRA ESRM-74
Bug 2012077
Change-Id: Ie2e640dfa0ab7193a062a58f588575f220e5efd3
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594791
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Add explicit #includes for <uapi/linux/nvgpu.h> for source code files
that depend on it.
JIRA NVGPU-388
Change-Id: I5d834e6f3b413cee9b1e4e055d710fc9f2c8f7c2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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vgpu printed GPU characteristics flags at probe time. Delete the
print in order to be able to remove GPU characteristics field.
JIRA NVGPU-388
Change-Id: Ib08325e7a67598a4f6734f7e839d1b96ba10bd55
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596245
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GPU class ids were moved to get_litter_value API, but vgpu was not
updated to remove assigning them in HAL initialization. Remove the
duplicate assignments.
JIRA NVGPU-388
Change-Id: If75944517d1ea813496b1f2a12a1faf03406d8d0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596244
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Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and
the related kind setup code. They are not needed anymore.
While we're doing these changes, remove a redundant assignment of
g->bootstrap_owner in hal_gv100.c.
Bug 1902982
Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560931
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After unbinding channel, following fields in
channel status needs to be cleared manually:
ccsr_channel_enable_clr_true
ccsr_channel_pbdma_faulted_reset
ccsr_channel_eng_faulted_reset
Unbinding channel expected to clear all other
channel status fields.
Bug 1972365
Change-Id: Ibfd84df2f41adc2eb437a026acde3f3d618d7758
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594671
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Updated clock gating prod settings for HWCL # 39314184.
This is corrected output after fixing issue in register
generator tool.
Bug 1994238
Change-Id: I646c4e1a134570016425367be636250205205005
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594605
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move sm_arch_* fields to nvgpu_gpu_params to make them available from
common code without accessing Linux specific GPU characteristics.
JIRA NVGPU-259
Change-Id: I8e7b542642b620f161d62954400777079065f49d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593692
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Return GPU classes in HAL get_litter_value() instead of assigning
them to GPU characteristics at HAL initialization time.
JIRA NVGPU-259
Change-Id: I92cbadf3bd07292a8715d30843972def879795f5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593691
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move fuse override DT handling to Linux code. All the chip specific
fuse override functions did the same thing, so delete the HAL and
call the same function to read the DT overrides on all chips.
Also remove the fuse override functionality from dGPU. There are no
DT entries for PCIe devices, so it would've failed anyway.
JIRA NVGPU-259
Change-Id: Ic672e25090cdfc207d9771ab61b6cf53185113a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593693
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add vgpu_gv11b_init_gpu_characteristics() and enable
NVGPU_SUPPORT_TSG_SUBCONTEXTS
Jira VFND-3797
Jira EVLR-1751
Change-Id: I288ac062e42ec399a302d693471b50b58c9a2653
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1543015
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id
and runqueu_sel to RM server. Use this command in gv11b's
implementation of gops->fifo.tsg_bind_channel.
Jira EVLR-1751
Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579840
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Switch two cases using the old NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_*
flags to the newer definitions, that is,
NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE. The legacy NVGPU_MAP_BUFFER_FLAGS_*
definitions have been deleted.
Bug 1902982
Change-Id: Ifbd2678b10005b4af2375600888469b01dd09f4e
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1592655
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement gv11b platform specific rail gating functions
by calling relevant powergate and unpowergate functions
and linux clock frmework functions:
gv11b_tegra_is_railgated
gv11b_tegra_railgate
gv11b_tegra_unrailgate
These calls will take care of hot reset sequence
required for gpu powergate and gpu unpowergate.
Bug 200269361
Bug 200273571
Change-Id: Ib1825e4324d51fc508b3b5dc9e5e2fdb252eeff4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589509
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix #includes in all the files to include platform_gk20a.h file with
correct path
NVGPU-316
Change-Id: Icb26d3c75076b8fdc8da992f751e1cfea22996be
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589939
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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API gr_gv11b_create_sysfs() and GR HAL create_gr_sysfs() right now receive
linux specific struct device
But since this function is called from/declared in common code, we need to
remove linux dependency from it
Hence update the API and GR HAL to receive struct gk20a pointer instead
of device pointer
Jira NVGPU-259
Change-Id: I65d717ad9f263f0397f8efa5761c64e55c7846eb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588465
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This patch adds kernel interface for dynamic TPC-PG feature.
User-space needs to send TPC-PG args to kernel via ioctl.
Dynamic TPC-PG feature will allow every context to specify the
number of TPC's it will use to run its workload.
This way, graphics driver can power off non-required TPC's
if a particular context has light to medium workload.
JIRA GPUT19x-16
Change-Id: Id4846245a6414b719599d04784cbe2ca5282f4ad
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1575848
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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T19x component for similar change in the main nvgpu code.
JIRA NVGPU-287
Change-Id: Ib126b3d1fb562850fbb3ab89103f2a7fdaa13306
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589430
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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TSG enable sequence in native has been modified due to a
hardware bug requiring enabling all channels with NEXT and
CTX_RELOAD set in a TSG, and then enabling rest of
channels.However it is not possible to check if NEXT and
CTX_RELOAD is set in vgpu. Have a separate implementation
for enabling tsg sequence in vgpu till the fix for
hardware bug is implemented for virtualized configuration.
Bug 200348087
Change-Id: I8e6c2ba8722531563de65e51e3d6af6acb7af213
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588739
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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Add GPU architecture and implementation to a new struct nvgpu_gpu_params
which is defined in common header file gk20a/gk20.h.
JIRA NVGPU-259
Change-Id: Idde2caded75fcb1e03e95be11f6aa2ec33a0962b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588033
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Use nvgpu specific nvgpu_kcalloc()/nvgpu_kfree() calls instead of linux specific
kcalloc()/kfree()
Jira NVGPU-259
Change-Id: I73034ea23561d1269230b9ac10360f8b171b8d41
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588221
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Try to fix invalid pte type repalayable faults only.
All other replayable faults will be cancelled so that
next mmu fault for same fault address will be triggered
as non-replayable fault and ch/tsg teardown will take place.
Bug 1958308
Change-Id: I63b90ce7c639ee183f87db3e771f253fd04c3567
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566576
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Teardown function should be passed appropriate id and
id_type. E.g. if a channel is marked as tsg, channel teardown/rc
function should be passed it's tsgid as id and type_tsg as
id_type
Bug 200277163
Change-Id: I2e83561c03d515fac28cbb8ce75a9f2c7bf746ac
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1557296
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Define GPUIDs without referring to constants defined in
<linux/uapi/nvgpu.h>.
JIRA NVGPU-259
Change-Id: I719ed5dd7e03c98f556d7932df132d9a39f25a9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1587282
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Fixups for the change of name subject in nvgpu.
JIRA NVGPU-287
Change-Id: I6c19733079061a42786b94fc48db374d715ccbef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586548
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Native code for verifying tsg status on ctx reload is not
possible on vgpu. Unset gops->fifo.tsg_verify_status_faulted
operation for vgpu for now. This needs to be implemented
separately for vgpu later.
Bug 200348087
Change-Id:Ib427f66e0897e37c34b882ead95ca8b84d595d72
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585784
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Update all Kconfig files and Makefiles to rely on the kernel overlay
feature. In particular, don't include any Kconfig files or Makefiles
from other overlays. -I directives in CFLAGS are not yet cleaned up.
Bug 1978395
Change-Id: I16386f7f1e76bd68b55f3128b25eada029ae82c1
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571165
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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t19x changes necessary for change in core MM code.
JIRA NVGPU-30
Change-Id: Id0d66543582abcef522e3182da0b01d0042f4b14
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585476
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Follow the sizing consideration in bug 1753763 to support dynamic TPC modes
and subcontexts.
bug 200350539
Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584034
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Make GPU characteristics flags specific to Linux code only. The
rest of driver is moved to using nvgpu_is_enabled() API.
JIRA NVGPU-259
Change-Id: I46a5a90bb34f170e9e755e7683be142ed6b18cce
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583992
GVS: Gerrit_Virtual_Submit
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Create an nvgpu internal nvgpu_gr_sm_error_state to store and
propagate SM error state within driver. Use
nvgpu_dbg_gpu_sm_error_state_record only in Linux code.
JIRA NVGPU-259
Change-Id: Ia2b347d0054365bdc790b4d6f2653a568935bdb0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585646
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