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* gpu: nvgpu: gv100 temperature read supportMahantesh Kumbar2018-04-06
| | | | | | | | | | | | | | | | | | | | | | - Enabled internal temperature sensor read for gv100 dgpu. - Added check to temperature read support before proceeding to read temperature from H/W - Assigned GP106 temperature HAL's for GV100 as no changes between GP106 & GV100 H/W registers. Bug 200352328 Change-Id: I86b5a1859b87ace49a07d0ff3749bb5b085bba91 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673347 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gk20a: Use ENOSPC instead of ENOMEMmpurohit2018-04-06
| | | | | | | | | | | | | | | | | | | | | | Modify gr_gk20a_add_zbc() to return -ENOSPC instead of -ENOMEM when all slots are already used. ENOMEM is more meant for memory allocation failures, anyway. This is required for porting nvgpu_gpu_zbc test case using libnvrm_gpu APIs. Bug 1967537 JIRA VQRM-3348 Change-Id: Ib7bcb6ba94d2ca168bcad517a8a7260fbf278a91 Signed-off-by: Mahesh Purohit <mpurohit@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1688302 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete unused variable in priv_ring_gp10b.cAlex Waterman2018-04-05
| | | | | | | | | | | | | | | | This slipped in recently since there's no compilation check for this type of error. JIRA NVGPU-525 Signed-off-by: Alex Waterman <alexw@nvidia.com> Change-Id: I68cdef6f3e090058cd490bf49e5db1afb9cc2b39 Reviewed-on: https://git-master.nvidia.com/r/1687091 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106: Reduce usage of os_linux.hAlex Waterman2018-04-05
| | | | | | | | | | | | | | | | | | | | | | In clk_gp106 the Linux platform specific data is only referenced if debugfs is being used. Thus only include the Linux OS stuff if debugfs is enabled. This allows us to compile the rest of the clk code in non- Linux kernel environments. Also delete os_linux.h from xve_gp106.c since that header is unused in the XVE code (and also do a minor cleanup by deleting the pr_warn()). JIRA NVGPU-525 Signed-off-by: Alex Waterman <alexw@nvidia.com> Change-Id: I5a20ba3b02eb2d8741c73ef2ded9276f6aebb957 Reviewed-on: https://git-master.nvidia.com/r/1687090 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cast negative int to u32 before shiftAlex Waterman2018-04-05
| | | | | | | | | | | | | | | | | | | A shift of a negative number is undefined; so to work around said warning simply cast to a u32 first. In this case the resulting operation should be ok since the sign bits are maintained when the 32 bit negative integer is shifted into a 24 bit negative integer. JIRA NVGPU-525 Change-Id: I0a35b0ccbccbcf4ac1b0767acad75c082143429e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673826 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: De-linuxify pmgr codeAlex Waterman2018-04-05
| | | | | | | | | | | | | | | | | | | | The pmgr code is in theory common code. However there were uses of Linux stuff within this code. This patch cleans that up by deleting the unnecessary os_linux.h includes, usage of kfree() and adds several platform fields to the gk20a struct. The platform data is copied to the gk20a struct in the platform initialization code so that this common code can access said data without requiring any knowledge of the OS platform data. JIRA NVGPU-525 Change-Id: Ic4bb6021f60b0a0778779ab5f3e15b7e5ca98306 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673825 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Only use gr.create_gr_sysfs with CONFIG_SYSFSAlex Waterman2018-04-05
| | | | | | | | | | | | | | Only populate the create_gr_sysfs() functions when the system actually has SYSFS (i.e is compiling for the Linux kernel). This allows non- Linux systems to compile. JIRA NVGPU-525 Change-Id: I3bac34feff376d89c0b63259772c77f7b4a03adc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673824 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Abstract PCI header usageAlex Waterman2018-04-05
| | | | | | | | | | | | | | | | | | | | The mclk code for gp106 requires access to the PCI device ID headers in Linux. This patch makes it so that the mclk code does not need to directly include the Linux headers. This allows us to compile and link the dGPU chips code in the user space unit testing framework. JIRA NVGPU-525 Change-Id: I89e2fa7fbb3b67f061e026e48a374951e7934aa5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673823 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: delete unnecessary Linux header includesAlex Waterman2018-04-05
| | | | | | | | | | | | Probably left overs from a bygone era. JIRA NVGPU-525 Change-Id: I3a83ccf1474e24b18312a600f786cb51ce634885 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673822 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add usermode submission interface HALSourab Gupta2018-04-05
| | | | | | | | | | | | | | | | | | | | The patch adds the HAL interfaces for handling the usermode submission, particularly allocating channel specific usermode userd. These interfaces are currently implemented only on QNX, and are created accordingly. As and when linux adds the usermode submission support, we can revisit them if any further changes are needed. Change-Id: I790e0ebdfaedcdc5f6bb624652b1af4549b7b062 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683392 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass alloc_gpfifo args to gk20a_channel_alloc_gpfifoSourab Gupta2018-04-05
| | | | | | | | | | | | | | | | The patch defines 'struct nvgpu_gpfifo_args' to be filled by alloc_gpfifo(_ex) ioctls and passed to the gk20a_channel_alloc_gpfifo function. This is required as a prep towards having the usermode submission support in the core channel core. Change-Id: I72acc00cc5558dd3623604da7d716bf849f0152c Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683391 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add corresponding whitelists for per-context registers.Debarshi Dutta2018-04-05
| | | | | | | | | | | | | | | | | | | | For gp10b, there is a single whitelist maintained for both global and per-context registers, for gm20b, there are separate whitelists maintained for global and per-context registers. This patch updates the failing registers in the bug into the per-context list. Bug 200363092 Change-Id: I1906ea46d4b37f9aa8d13833a5bba4a5f7c6bbe5 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1603660 (cherry picked from commit 1ec466151066eff40ca96ed41c8166602a7711ed) Reviewed-on: https://git-master.nvidia.com/r/1688274 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle misaligned_addr SM exceptionDeepak Nibade2018-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | We right now do not handle misaligned_addr SM exception explicitly and hence we incorrectly initiate CILP on this exception Handle this exception explicitly in this sequence - - set error notifier first - clear the interrupt - return error from gr_gv11b_handle_warp_esr_error_misaligned_addr() so that RC recovery is triggered by gk20a_gr_isr() Ensure that the error value is propagated back to gk20a_gr_isr() correctly Use nvgpu_set_error_notifier_if_empty() to set error notifier since this will prevent overwriting of error notifier value in case gk20a_gr_isr() also tries to write to some error notifier value Bug 200388475 Jira NVGPU-554 Change-Id: I84c4d202a8068e738567ccd344e05d9d5f6ad2f0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1686781 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use u64 for log maskTerje Bergstrom2018-04-04
| | | | | | | | | | | | | | | BIT() is defined as returning a 64-bit value. We use it to create the log mask values, but the functions that accept log mask take only u32 as parameter. Use u64 as log mask parameter for the logging functions to match the sizes. Change-Id: I6f0803a7d04ee6a2ee725b5defc4cc14b5b7acf5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683818 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use #define for stalling/nonstallingTerje Bergstrom2018-04-04
| | | | | | | | | | | | | We use stalling and non-stalling enums in many places where u32 is expected. enum conversion to u32 is considered unsafe, so change the definition to #define with a qualifier U. Change-Id: Ifa5cb9b6a0b0de79f7f8266979fc487d9823bafa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683817 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Correct sign qualifiers for LTC codeTerje Bergstrom2018-04-03
| | | | | | | | | | | | | In constants we use in LTC code we miss the qualifier indicating if the constant is signed or unsigned. Add qualifiers for LTC code and the ZBC related constant used in LTC code. Change-Id: Id80078722f8a4f50eb53370146437bebb72a3ffc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683859 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable rail gatingseshendra Gadagottu2018-04-03
| | | | | | | | | | | | | | | | | | Enable gpu rail gating with idle delay of 500msec. Bug 2051863 Change-Id: I1bdfc1b3db38dff871cd5d62542dd51efbd07496 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640557 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialize ctxsw state for golden context creationseshendra Gadagottu2018-04-03
| | | | | | | | | | | | | | | | | | | | If golden context creation happens before any gpu railgate then channel creation is always fine. If gpu railgate happens after gpu finalize poweon, but before golden context creation, then golden context creation is failing during first channel creation with watchdog timeout from ctxsw because of invalid ctxsw state. To Fix this issue, if the golden context is not created, then during finalize power on always query ctxsw image sizes, which is making ctxsw hw in correct state before golden context creation. Bug 2051863 Change-Id: I81d221100a099b12bad3adc2d252de4621c335a5 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1682265 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix address table for GPCS_TPC6 broadcast conversionDeepak Nibade2018-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_create_priv_addr_table() and gv11b_gr_egpc_etpc_priv_addr_table(), we create a table of unicast addresses from broadcast addresses For GPC boardcast addresses like NV_PGRAPH_PRI_EGPCS_ETPC6_SM_*, we generate the table assuming there are 7 TPCs in all the GPCs But this is incorrect in some cases like GV100 where GPC0/1 have only 6 TPCs And hence we end up generating registers which do not exist Fix this by explicitly checking the number of TPCs and ensuring that address generated is belongs to valid TPC Bug 200400376 Jira NVGPU-564 Change-Id: I65d7d6cd7f0bf16171eb54ed71f1f3840ade3495 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1686806 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle pm suspend/resume with runtime pm disableseshendra Gadagottu2018-04-02
| | | | | | | | | | | | | | | | | | | | | When runtime pm is disabled, then gpu rail will be on as soon as nvgpu module is loaded. If pm suspend/resume called before gpu hw initialization(g->poweron = false) then pm suspend is skipping gpu railgate, which is causing issues with SC7 entry/exit. To fix this issue: 1. During pm suspend, if g->poweron is false, check for runtime pm disable to railgate gpu rail. 2. On pm resume, check for runtime pm disable to enable gpu rail, though gpu driver not initialized. Bug 2073029 Change-Id: I7631109d79cda5882d2864557f1b7b3d2d89c9f6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679010 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "nvgpu: Remove ASYNC PROBE for vgpu"Aniruddha Banerjee2018-04-02
| | | | | | | | | | | | | | | | This reverts commit dbdf57fb3c34227b26c1858d85c83c18d34de453. The aync-probe was causing an issue because the arm-gic set_type did not have the proper locking constructs to prevent races in gic distributor. Bug 200385192 Change-Id: Ic4f51705e58da8145845b4812c8e61e1c73932cd Signed-off-by: Aniruddha Banerjee <aniruddhab@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676616 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: do not poll if stall intr is setSeema Khowala2018-03-30
| | | | | | | | | | | | | | | | | | | Do not continue polling if engine save has not started yet and stall intr is set because if a stall intr is hit, preemption will anyways not get completed. Just set the reset_eng_bitmask of the engine for which ctx_status was being polled, As part of teardown corresponding engine will be reset. Bug 2069807 Change-Id: I9a506e0bca1d891ed5cd5d4953e292a40356f8ff Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683694 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: set apply_ctxsw_timeout and ch_wdt_timeout_msVijayakumar2018-03-30
| | | | | | | | | | | | | | | -set apply_ctxsw_timeout_intr to NULL. This was added as part of DNI change SHA 1f71f475e25fe786ec76d76a986aac8afec51b01 -change ch_wdt_timeout_ms from 30ms to 7ms Bug 2040544 Bug 2069807 Change-Id: I9125207146e1e3e42325ecda6a2aa7f1c07fdd3a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683719 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 and missing types.h header fixesAlex Waterman2018-03-30
| | | | | | | | | | | | | | | | | | | | | | | Multiple places were missing explicit <nvgpu/types.h> includes but used various types anyway. Fix that by including <nvgpu/types.h> where necessary. A gp106 file directly used the Linux delay header instead of including <nvgpu/timers.h>. This patch fixes both problems. JIRA NVGPU-525 Change-Id: Ib7a30a8ed9098d469d646c0a2bba293087b8de90 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673821 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cleanup more set but unused variablesAlex Waterman2018-03-30
| | | | | | | | | | | | | | | | This time they were largely located in the various common directories. JIRA NVGPU-525 Change-Id: I3a6d523b060a0c6761b227267890298c6d2fb19f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673820 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete unused regops dataAlex Waterman2018-03-30
| | | | | | | | | | | | | | | | Flaged by CLANG, this data is unused and may now be deleted. JIRA NVGPU-525 Change-Id: Idf232b98aa3dfa6b03d29ec8b38cde58de20d29f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673819 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: WAR unlikely() bug in CLANGAlex Waterman2018-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CLANG, when compiling regops_gk20a.c sees the following warning: ../drivers/gpu/nvgpu/gk20a/regops_gk20a.c:464:30: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if (unlikely(skip_read_lo == false)) { ~~~~~~~~~~~~~^~~~~~~~ ../drivers/gpu/nvgpu/gk20a/regops_gk20a.c:464:30: note: remove extraneous parentheses around the comparison to silence this warning if (unlikely(skip_read_lo == false)) { ~ ^ ~ ../drivers/gpu/nvgpu/gk20a/regops_gk20a.c:464:30: note: use '=' to turn this equality comparison into an assignment if (unlikely(skip_read_lo == false)) { ^~ = 1 error generated. But this obviously is fine. However, it's simple enough to work around by just deleting the unlikely() call. We don't do anything with that anyway. JIRA NVGPU-525 Change-Id: I674855ad08daf65ac6d79ceab7d4f56f637d4437 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673818 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use proper signage in shift operationAlex Waterman2018-03-30
| | | | | | | | | | | | | | | | This fails with a warning when compiling with CLANG. JIRA NVGPU-525 Change-Id: Ied04e1683d1740d7f946902edc93299d223564fc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673817 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: channel_gk20a.c cleanup for POSIXAlex Waterman2018-03-30
| | | | | | | | | | | | | | Remove a variable which is assigned to but never used. Add proper include (<nvgpu/log2.h>) for ilog2(). JIRA NVGPU-525 Change-Id: I42f3fddad9c294dc64343082e1dbd44b19120089 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673816 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: set sched err and ctxsw_timeout halsVijayakumar2018-03-30
| | | | | | | | | | | | | | | gv100 does not have new fifo ctxsw timeout interrupt that is present on gv11b. Use non gv11b sched error and ctxsw timeout handlers. Bug 2069807 Change-Id: I9dc2b8d9212145d7a1b0fef656aa20d2f073ea13 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1668401 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add TEGRA_VGPU_EVENT_SET_ERROR_NOTIFIERRichard Zhao2018-03-29
| | | | | | | | | | | | | | | | RM server will notify clients with TEGRA_VGPU_EVENT_SET_ERROR_NOTIFIER whenever .set_error_notifier is called. Clients will set error notifier accordingly. Jira VQRM-3058 Change-Id: I2f435335867cce5dfd7fddb718ac6a1ff7cd66ae Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679711 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add TEGRA_VGPU_EVENT_CHANNEL_CLEANUPRichard Zhao2018-03-29
| | | | | | | | | | | | | | | RM server uses the command to notify clients to abort and clean up a channel. Clients will set has_timedout at the same time. Jira VQRM-3058 Change-Id: Iebd28ccdae52dd789ee93d65c4e816b83df8d891 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679710 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add event TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUPRichard Zhao2018-03-29
| | | | | | | | | | | | | | | | RM Server will implement callback for semaphore wakeup and broadcast event TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP. The patch adds handling of the event in vgpu code. Jira VQRM-3058 Change-Id: Ife38eff8252f5b4036e6df71f1c64c99cb58c1b5 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676240 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gops.fifo.setup_swSourab Gupta2018-03-29
| | | | | | | | | | | | | bar1/userd setup is different for RM server. created common function gk20a_init_fifo_setup_sw_common. Jira VQRM-3058 Change-Id: I655b54e21ed5f15dcb8e7b01bd9cd129b35ae7a3 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665691 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gops.fifo.set_error_notifierRichard Zhao2018-03-29
| | | | | | | | | | | | RM Server overrides it for handling stall interrupts. Jira VQRM-3058 Change-Id: I8b14f073e952d19c808cb693958626b8d8aee8ca Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679709 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gops.fifo.channel_suspend/channel_resumeRichard Zhao2018-03-29
| | | | | | | | | | | | RM Server acts differently for channel suspend/resume. Jira VQRM-3058 Change-Id: If41e3099164654db448d1157fd7f51dd00c5e201 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679707 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gops.fifo.check_tsg_ctxsw_timeout/check_ch_ctxsw_timeoutRichard Zhao2018-03-29
| | | | | | | | | | | | | RM Server acts differently for ctxsw timeout check. It won't check GP_GET or accumulated timeouts, but notify guest and go to recovery. Jira VQRM-3058 Change-Id: I428aea34dc517311eb7e73feb556145e916309fb Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679706 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gops.fifo.ch_abort_clean_upRichard Zhao2018-03-29
| | | | | | | | | | | | | | Channel abort clean up is only needed by native and vgpu driver but not RM server. RM server expects guest will clean up itself. RM server should not set the callback. Jira VQRM-3058 Change-Id: I11b49b6f2d51c871e31de16955d487dca82609cb Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679705 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make fifo/ch functions called by RM Server globalSourab Gupta2018-03-29
| | | | | | | | | | | | | | | | | | The patch declares globally few channel/fifo HAL functions required for QNX code compilation (as they are being referred elsewhere in QNX code). This is required as a part of bringing in the nvgpu Channel/FIFO HAL into QNX. Jira VQRM-3058 Change-Id: Ia176535b64de981d2f7ddb20f62015a0da74fd2a Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662411 GVS: Gerrit_Virtual_Submit Tested-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enhance pbus error reportingSeema Khowala2018-03-29
| | | | | | | | | | | | | | | | -Dump timeout save0 and save1 even if they could be unreliable when fecs_tgt in set in save0 . This is good to have for debug purposes. -Add priv_ring hal for decode_error_code -Decode fecs error code for supported error types Bug 1998067 Change-Id: I60cb6902d099df4a7df45fa624e44d9e0d46360f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683014 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use gpc_tpc_count[gpc] for number of tpc in a gpcSeema Khowala2018-03-29
| | | | | | | | | | | | | | | | | | | | | Using tpc_count instead of gpc_tpc_count indexed by gpc, will result in pbus error with decode error or client floorswept error codes. tpc_count represents total number of tpc while gpc_tpc_count[gpc] represents number of tpc in the indexed gpc. Bug 1998067 Change-Id: I9adfb98a6c3e209cbb02a8cd5090f6b6adc1ec4b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1682469 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix priv error register readsThomas Fleury2018-03-28
| | | | | | | | | | | | | | | | | | | | | | | | Current code does not compute priv error register offsets properly. This leads to invalid decoding of priv errors, and can also trigger additional priv errors. - add GPU_LIT_GPC_PRIV_STRIDE define - return proj_gpc_priv_stride for GPU_LIT_GPC_PRIV_STRIDE in hals - use GPU_LIT_GPC_PRIV_STRIDE instead of GPU_LIT_GPC_STRIDE in g->ops.priv_ring.isr() to compute priv error register offsets. Bug 2093058 Change-Id: Ia7c36ccba0441126784bb0e00452f2cf1196ef71 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1682118 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add accessor for gpc priv strideThomas Fleury2018-03-28
| | | | | | | | | | | | | | | | | Re-generate headers for proj_gpc_priv_stride accessor. This is needed to compute priv error register offsets. Bug 2093058 Change-Id: Ied4e2b072f650940757c44e261b416d388e8924c Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1682117 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: simplify job semaphore release in abortKonsta Holtta2018-03-28
| | | | | | | | | | | | | | | | | | | Instead of looping all jobs and releasing their semaphores separately, do just one semaphore release. All the jobs are using the same sema index, and the final, maximum value of it is known. Move also this resetting into ch->sync->set_min_eq_max() to be consistent with syncpoints. Change-Id: I03601aae67db0a65750c8df6b43387c042d383bd Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680362 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: delete semaphore release supportKonsta Holtta2018-03-27
| | | | | | | | | | | | | | | | | | | | | | | | Semaphores don't need to be released from CPU anymore, so clarify the code by deleting nvgpu_semaphore_release() and refactoring __nvgpu_semaphore_release() to nvgpu_semaphore_reset() that only "fast-forwards" the semaphore to a later value. While doing this, the meaning of nvgpu_semaphore_incr() changes, so rename it to nvgpu_semaphore_prepare(). Now it's only used to prepare an nvgpu_semaphore for a value that the HW will increment the sema to. Also change the BUG_ON that guards sema double-inits into just WARN_ON. Change-Id: I6f6df368ec5436cc97a229697742b6a4115dca51 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680361 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: handle_tpc_sm_ecc_exception set to NULLSeema Khowala2018-03-27
| | | | | | | | | | | | | | | | | | | | This is to fix *SM_ICACHE_ECC* priv errors for sm suspend resume test. gv100 has significantly less ECC protected SRAMs. gv11b ECC hals will not work for gv100. Bug 1998067 Change-Id: I437a7981ed1832c2070185f3ad8f802c7454e8c9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1681270 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sandarbh Jain <sanjain@nvidia.com> Tested-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Check return code in gp10b_get_pde0_pgsz()Alex Waterman2018-03-26
| | | | | | | | | | | | | | | nvgpu_mem_begin() needs to have it's return code checked to make sure that it did not fail. Coverity defect id: 2883904 Bug 200291879 Change-Id: Ic845a73439a905997a1f871708b1f847f5b93293 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1681249 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reset streaming on perfbuf_enable and perfbuf_disableMartin Radev2018-03-26
| | | | | | | | | | | | | | | | | Similarly to css_hw_(enable|disable)_snapshot the HWPM state should be reset on perfbuf_enable and perfbuf_disable to avoid leaking snapshot data into a freshly mapped buffer. Bug 1960846 Change-Id: I94826b209ef4b8cb6ad44d3b8667745270c6a7e1 Signed-off-by: Martin Radev <mradev@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676009 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix memory leaks in error pathDeepak Nibade2018-03-23
| | | | | | | | | | | | | | | | | | | Error path is not implemented in nvgpu_pci_probe(), and that could lead to memory leaks if any of the step in nvgpu_pci_probe() fails Fix this by implementing error path and freeing all allocated buffers Bug 200291879 Coverify defect id : 2845621 Change-Id: Iee1abb041089e47a517a6698f0a4067c9c4fa289 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1681028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disallow invalid syncpoint wait idsKonsta Holtta2018-03-23
| | | | | | | | | | | Instead of ignoring a wait when a raw syncpoint prefence has an invalid id, reject the submit with -EINVAL just like with syncpoints in syncfds. Change-Id: I9b5c417bd1c7cd081c79659d088ac2c915de8c0e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680281 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 02:38:14 -0500