summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu
Commit message (Collapse)AuthorAge
* gpu: nvgpu: fix race between do_idle() and unrailgate()Deepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | While we are executing do_idle() API, it is possible that unrailgate() gets invoked in midst of idling the GPU and this can result in failure of do_idle() To prevent simultaneous execution of these methods, add a mutex railgate_lock and acquire it during do_idle() and unrailgate() APIs Also, keep this lock held if do_idle() is successful. In success, lock will be released in do_unidle(), otherwise release this lock before returning Note that this lock should not be held in railgate() API since we do not want it to be blocked during do_idle() bug 1529160 Change-Id: I87114b5367eaa217376455a2699c0d21c451c889 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/434190 (cherry picked from commit 561dc8e0933ff2d72573292968b893a52f5f783a) Reviewed-on: http://git-master/r/435131 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* Revert "gpu: nvgpu: Dump offending push buffer fragment"Arto Merilainen2015-03-18
| | | | | | | | | | | | | | | | | | | Channel and gpfifo allocations are entirely separated from each other, however, the code here assumes that active channel means that the channel also has a gpfifo. This reverts commit a24602f094380539788696d1b1567a4f4d914b17 which added gpfifo dump. Changing debug dumping to be safe requires refactoring the channel release code to use proper locking. Bug 1530226 Change-Id: I2fb02542a17dd56a0a9ce732b327e34b85ade8b9 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/434038 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Exclude non-secure boot with CONFIG_TEGRA_ACRSeshendra Gadagottu2015-03-18
| | | | | | | | | | | Do not compile non-secure boot code if CONFIG_TEGRA_ACR is defined. Bug 1524197 Change-Id: Id1ec222e00e2229e1d28e406e4ddad99e368296e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/433356 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu:nvgpu: Enable Falcon trace printsVijayakumar2015-03-18
| | | | | | | | | | | Dump Falcon trace on PMU Crash and add debugfs node falc_trace. This needs Debug trace to be enabled in GPmu binary. Change-Id: I093ef196202958e46d8d9636a848bd6733b5e4cc Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/432732 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Update generic platformArto Merilainen2015-03-18
| | | | | | | | | | This patch adds .is_railgated() callback for the generic gpu platform. Change-Id: Ief13a6fba82b376aafbe861e8f3823a19bb7f679 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/433059 Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Support probing host1x link from appsArto Merilainen2015-03-18
| | | | | | | | | | | This patch adds support to check if the host1x link exists and is supported using the gpu characteristics ioctl. Bug 1459653 Change-Id: I832eea217ed7f007e341dfde5769887e0882d6bb Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/433058
* gpu:nvgpu:sysfs node to update aelpg parameterMahantesh Kumbar2015-03-18
| | | | | | | | | | | | | | | | Added sysfs node to update aelpg parameter. Pass parameter as below sequence, SAMPLING_PERIOD_PG_DEFAULT_US, MINIMUM_IDLE_FILTER_DEFAULT_US, MINIMUM_TARGET_SAVING_DEFAULT_US, POWER_BREAKEVEN_DEFAULT_US, CYCLES_PER_SAMPLE_MAX_DEFAULT Bug 1464737 Change-Id: I46873c463820f30f190c722d7ed038622cb2710f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/422702 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Remove GPU MMIO access on power/rail gateAlex Waterman2015-03-18
| | | | | | | | | | | | This is to weed out accesses to the GPU while it is gated. Otherwise the accesses are silently dropped or cause a HW hang (on older chips). Bug 1514949 Change-Id: Ice4cdb9f1f736978ebb3db847f39c7439bf98134 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/416339 Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Wait for idle via FIFO registersTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | Wait for engine idle via FIFO's engine status instead of submitting WFI to channel. Submitting WFI and waiting is not robust, and wait might invoke debug dump which cannot be done while powering down. Bug 1499214 Change-Id: I4d52e8558e1a862ad4292036594d81ebfbd5f36b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/432151 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Bump unmap retries if not siliconTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | | In simulation and emulation 50ms is not enough to ensure a job is complete. Bump it to 5s when not running on silicon. Bug 1510751 Change-Id: I90883b70ce2a75a8f07344f713d647b3fa0d0c7d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/432044 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Clear channel class on openTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | | | | Channel class needs to be cleared when a channel is opened. Otherwise previously used channel remains, and we can accidentally use KEPLER_C methods even if KEPLER_C is not allocated. Bug 1487928 Bug 200000669 Change-Id: I3e1ae8d5edbdd82fa569b38a89a89dedb69ee773 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428866 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Free allocated gr_ctxTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | gr_ctx is nowadays kalloc()'d separately. Adding kfree() to prevent memory leak. Bug 1528275 Change-Id: I942812a483adad47e82bc75a7bda5942c30c527a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428890 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shridhar Rasal <srasal@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: fix possible PMU isr raceDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Possible race description : - while PMU is booting, it sends messages to kernel which we process in gk20a_pmu_isr() - but when messages are processed it is possible that we are on the way to rail gate the GPU and we have already called pmu_destroy() - this could lead to hangs if while processing messages, GR is already off To fix this, introduce another mutex isr_enable_lock and a flag to turn on/off ISRs - when we enable PMU, get the lock and set the flag - in pmu_destroy(), get the lock and remove the flag - in pmu_isr(), take the lock, check if flag is set or not. If flag is not set return, otherwise proceed with the messages Bug 200014542 Bug 200014887 Change-Id: I0204d8a00e4563859eebc807d4ac7d26161316ea Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/428371 (cherry picked from commit 9a37528314f2a2504e4530719f817a93db9a5bf0) Reviewed-on: http://git-master/r/428352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* nvgpu: Modify ACR host to use physical trancfgSupriya2015-03-18
| | | | | | | | | | | | | | | | | PMU ucode and ACR ucode need 0th ctx dma to be programmed for Physical access. To stay in sync with ucodes, modified 0th transcfg to be physical access, and suitably modified all other ctx dma's sent. Bug 1509680 Change-Id: Ib3a24ebb8478488af57bb465d782e4045ca7d0d0 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/432084 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu:nvgpu:fix powergate disabling orderVijayakumar2015-03-18
| | | | | | | | | | | | | | | | | ELPG has to disabled before we write to clock gating registers If ELPG is engaged during clock gating register write it will cause error in ELPG engine Bug 200013495 Bug 200014542 Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/432117 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Fix definition of cbc_ctrl1 registersTerje Bergstrom2015-03-18
| | | | | | | | | | | | ltc_ltc0_lts0_cbc_ctrl1_r() was pointing to broadcast register. Change-Id: I1646f6c68ac944333474029bb78242844424c6f7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428919 Reviewed-by: Matt Craighead <mcraighead@nvidia.com> Tested-by: Matt Craighead <mcraighead@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Initialize PMU ucode only onceTerje Bergstrom2015-03-18
| | | | | | | | | | | Initialize PMU ucode only once, and skip on next GPU boot. Bug 1528275 Change-Id: Ifb95edb380518fae48fdc3b90b00b450fe30c439 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428897 Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: Wait for CBC op to finish for all LTCsTerje Bergstrom2015-03-18
| | | | | | | | | | | We broadcast CBC operation to all LTCs, but we wait for only one to finish. Bug 1507804 Change-Id: Ib10aa5fe3a34b31862b2d5162c77441f7444a7ba Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428123
* gpu: nvgpu: Boot FECS to secure modeTerje Bergstrom2015-03-18
| | | | | | | | | | Boot FECS to secure mode if ACR is enabled. Bug 200006956 Change-Id: Ifc107704a6456af837b7f6c513c04d152b2f4d3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424251
* gu: nvgpu: Add PMU state ELPG bootingTerje Bergstrom2015-03-18
| | | | | | | | | | | Add PMU state ELPG booting. Prevent ISR processing when PMU is in OFF state. Bug 200006956 Change-Id: Ibcf69a2d81965cc87f520bf864c4425681f04531 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424769
* gpu: nvgpu: Separate PMU firmware load from initTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Separate the code to load PMU firmware from the software init. This allows folding ACR and non-ACR PMU software initialization sequences. Bug 200006956 Change-Id: I74b289747852167e8ebf1be63036c790ae634da4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: do not abort probe if secure page alloc failsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | Do not abort GPU probe if secure page alloc fails. We can just note that this allocation failed (using bool secure_alloc_ready) and prevent further secure memory allocation if this flag is not set. Bug 1525465 Change-Id: Ie4eb6393951690174013d2de3db507876d7b657f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/427730 GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add timeout to L2 flushAlex Waterman2015-03-18
| | | | | | | | | | | | Add a timeout mechanism to the L2 flushing code for gm20b. Previously the code could spin forever in a loop if some issue were to occur with the L2 causing the flush to fail. Change-Id: I742c7671bac92aeb8e9674c43d30c45b2de4a836 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/423842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove extra g field in pmu_gk20aTerje Bergstrom2015-03-18
| | | | | | | | | | | pmu_gk20a has a pointer to struct gk20a *. As pmu_gk20a is part of gk20a, there's no need to have the circular dependency. Bug 200006956 Change-Id: I6d5d10a93b2fba4a26a1e28b3c5206506dc6cc04 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424767
* gpu: nvgpu: add TSG support for engine contextDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All channels in a TSG need to share same engine context i.e. pointer in RAMFC of all channels in a TSG must point to same NV_RAMIN_GR_WFI_TARGET To get this, add a pointer to gr_ctx inside TSG struct so that TSG can maintain its own unique gr_ctx Also, change the type of gr_ctx in a channel to pointer variable so that if channel is part of TSG it can point to TSG's gr_ctx otherwise it will point to its own gr_ctx In gk20a_alloc_obj_ctx(), allocate gr_ctx as below : 1) If channel is not part of any TSG - allocate its own gr_ctx buffer if it is already not allocated 2) If channel is part of TSG - Check if TSG has already allocated gr_ctx (as part of TSG) - If yes, channel's gr_ctx will point to that of TSG's - If not, then it means channels is first to be bounded to this TSG - And in this case we will allocate new gr_ctx on TSG first and then make channel's gr_ctx to point to this gr_ctx Also, gr_ctx will be released as below ; 1) If channels is not part of TSG, then it will be released when channels is closed 2) Otherwise, it will be released when TSG itself is closed Bug 1470692 Change-Id: Id347217d5b462e0e972cd3d79d17795b37034a50 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/417065 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add TSG support to runlistsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | - when a TSG channel is made runnable, add it to TSG's runnable list - when a TSG channel is removed from runlist, remove it from TSG's runnable list When we rewrite the entire runlist : - first add all the channels which are not part of any TSG - then find all active TSGs, add an entry in runlist for the TSG (with TSG id and length of TSG) - then write entries for each channel in that TSG Bug 1470692 Change-Id: Ic55a4d5959abc72cd20b8224eb4c31d3ff411861 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/416612 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add accessors for runlist ram entryDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | Add accessors to modify contents of runlist ram (RAMRL) entry. Using these accessors we can modify a runlist entry to specify it as regular channel or TSG entry Bug 1470692 Change-Id: If39759941ecb07af11152dbddb6fb5a67c14b26e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/416611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Randy Spurlock <rspurlock@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add kernel APIs for TSG supportDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | Add support to create/destroy TSGs using node "/dev/nvhost-tsg-gpu" Provide below IOCTLs to bind/unbind channels to/from TSGs : NVGPU_TSG_IOCTL_BIND_CHANNEL NVGPU_TSG_IOCTL_UNBIND_CHANNEL Bug 1470692 Change-Id: Iaf9f16a522379eb943906624548f8d28fc6d4486 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/416610
* gpu: nvgpu: make pm config as platform dataSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | | | Make gpu power management feature configurations as platform data. Keep existing sttaus for gk20a and disable all power features for gm20b. Bug 1523728 Change-Id: Ife7786863f18e21b882ac77085c7abc7c84d4cfc Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/426369 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add explicit wmb() before reg writeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | Add explict memory barrier wmb() before writing to register values. Also call writel_relaxed() instead of writel() to skip internal wmb() call which is conditional on some configs. Bug 200012037 Change-Id: I9c545138314b6e73fec2a4aff2b1956444fac806 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421463 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com>
* nvgpu: Host side changes to support HS modeSupriya2015-03-18
| | | | | | | | | | | | | | | | | | | GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Dump offending push buffer fragmentTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | When outputting debug dump, print the contents of current push buffer segment. Also changes the debug dump to use pr_cont when applicable, and dumps state before recovering in case channel was not loaded to an engine. Bug 1498688 Change-Id: I5ca12f64bae8f12333d82350278c700645d5007e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/422198
* gpu: nvgpu: do not idle timed out channelsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | While suspending the device, do not submit WFI on timed out channels Submitting WFI on timed out channels will cuase submit_wfi() to return error and as result of this, rail gating of device will be prevented Bug 200010416 Change-Id: Ic097bfdae59dbf9e1f2aea5d8d0431b5f1c3721b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/422743 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: bail out from poweroff if channel suspend failsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | During gk20a_pm_prepare_poweroff(), if call to gk20a_channel_suspend() fails, we proceed to disable other components and then return error. But when genpd sees the error, it will abort the suspend sequence and keep the device state as active. But since we have already disabled all the components, GPU lands in invalid state. Hence, if channel_suspend() fails then do not proceed but return the error immediately Bug 200010416 Change-Id: I553a2a25832a1be4941bb6b6ce490c950cdbe7fa Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/422248 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support non-secure bootSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | | | For non-secure FALCON boot support, by-pass MMU check. Bug 1524197 Change-Id: I735c10a1ea50357c1ea2d5514c73477e76db7e77 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/424005 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove unused vpr refetch functionsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | VPR resize is done by forcing GPU to idle and then updating VPR size from TLK. There is no need now to call vpr_resize funtion from kernel and hence these functions can be removed. Bug 1487804 Change-Id: I758a6e0a99a58757866f1138b0a89594e2a33908 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421703 (cherry picked from commit 391d9bacf053fe0dacffc76c36768f82912ad1f4) Reviewed-on: http://git-master/r/419612 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: allocate secure buffer in probeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Allocate dummy secure buffer of size PAGE_SIZE during gk20a_probe(). This will also help to initiate first secure memory (VPR) resize call while GPU is rail gated and in reset. This dummy buffer is released after we allocate some more secure memory buffers in alloc_global_ctx_buffers() Bug 1487804 Change-Id: I61604d9e5ffb585801ee893435c98a0d3e69d666 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421701 (cherry picked from commit 4236ab3323ee3c02fac562740d8b80d763589dea) Reviewed-on: http://git-master/r/419610 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add APIs to allocate/free dummy secure bufferDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | Add APIs to allocate and free dummy secure buffer of size PAGE_SIZE. Also, fix small errors during secure memory alloc/free. Bug 1487804 Change-Id: If078116fb973e81bfcee054b900c09a313e389c6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421700 (cherry picked from commit 5391515dab27cc88b921cf81913085dea98197e0) Reviewed-on: http://git-master/r/419609 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement L2 flush in fifo recoveryAlex Waterman2015-03-18
| | | | | | | | | | | | | Implement a full L2 flush (clean and invalidate) for gm20b in the fifo recovery path. Bug 1512176 Change-Id: Ibf89ede9cca65a6868ebff89825869053302a007 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/416435 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add cache management registersAlex Waterman2015-03-18
| | | | | | | | | | | | | Add the necessary cache management registers for doing a full L2 flush in GM20b. Bug 1512176 Change-Id: I7799e5e584238a0af02abbf4f49917d7590d97dc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/417260 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix compilation issues with PM disableSeshendra Gadagottu2015-03-18
| | | | | | | | | | | Fix gpu driver compilation issues with power mangement and runtime power management disable. Change-Id: I8e1873871d6f184013b2142dd0cbc32c67774177 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/417925 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Support semaphore sync when aborting jobsLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | When aborting jobs on channel error situations, we manually set the channel syncpoint's min == max in gk20a_disable_channel_no_update. Nvhost will notice this manual syncpoint increment, and will call back to gk20a_channel_update, which will clean up the job. With semaphore synchronization, we don't have anybody calling back to gk20a_channel_update, so we need to call it ourselves. Release job semaphores (the equivalent of set_min_eq_max) on gk20a_disable_channel_no_update, and if any semaphores were released, call gk20a_channel_update afterwards. Because we are actually calling gk20a_channel_update in some situations, gk20a_disable_channel_no_update is no longer an appropriate name for the function. Rename it to gk20a_channel_abort. Bug 1450122 Change-Id: I1267b099a5778041cbc8e91b7184844812145b93 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/422161 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Improve locking in semaphore_gk20a.cLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | Fix some possible race conditions when manipulating the mapping list of semaphore pools. Acquire a reference to the vm in gk20a_semaphore_pool_map, and release that reference in gk20a_semaphore_pool_unmap. Bug 1450122 Change-Id: I204e9c3dffd5162538b93e628d016dc06b3a5fb6 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/422160 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Destroy channel sync before releasing vmLauri Peltonen2015-03-18
| | | | | | | | | | | | | The semaphore backend of gk20a_channel_sync uses the channel vm. We must destroy the channel sync before freeing the channel vm. Bug 1450122 Change-Id: I578567b7500672534d53facc58643df49df8b305 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/422159 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update channel on semaphore releaseLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | When using semaphore based channel synchronization, a semaphore release may mean that a job has completed. Call gk20a_channel_update from gk20a_channel_semaphore_wakeup to check if there are memory refs to release or sync timelines to signal. Bug 1450122 Change-Id: Ib829c895dab05676c35f974d3f1c3d88c047c9b9 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/394576 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add semaphore based gk20a_channel_syncLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add semaphore implementation of the gk20a_channel_sync interface. Each channel has one semaphore pool, which is mapped as read-write to the channel vm. We allocate one or two semaphores from the pool for each submit. The first semaphore is only needed if we need to wait for an opaque sync fd. In that case, we allocate the semaphore, and ask GPU to wait for it's value to become 1 (semaphore acquire method). We also queue a kernel work that waits on the fence fd, and subsequently releases the semaphore (sets its value to 1) so that the command buffer can proceed. The second semaphore is used on every submit, and is used for work completion tracking. The GPU sets its value to 1 when the command buffer has been processed. The channel jobs need to hold references to both semaphores so that their backing semaphore pool slots are not reused while the job is in flight. Therefore gk20a_channel_fence will keep a reference to the semaphore that it represents (channel fences are stored in the job structure). This means that we must diligently close and dup the gk20a_channel_fence objects to avoid leaking semaphores. Bug 1450122 Bug 1445450 Change-Id: Ib61091a1b7632fa36efe0289011040ef7c4ae8f8 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/374844 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Turn on scaling when poweredAllen Yu2015-03-18
| | | | | | | | | | | | | | This patch reorders scaling resume to happen always when we power on the GPU, so as to balance the scaling suspend when we power off GPU. bug 200010911 Change-Id: I9fde817fbf9fed7d90c48ea06050db4b82e670a8 Signed-off-by: Allen Yu <alleny@nvidia.com> Reviewed-on: http://git-master/r/421541 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Do not warn about unknown ctxsw regionTerje Bergstrom2015-03-18
| | | | | | | | | | Do not warn about unknown regions in ctxsw firmware blob. Bug 1435870 Change-Id: I343d85a09a3cd1d7c1c881836af6868296409f07 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/420670
* gpu: nvgpu: Add rail gating trace eventsTerje Bergstrom2015-03-18
| | | | | | | Change-Id: I661f14b2858fb7bc993157a597d4a278859da837 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/418789 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: print intr code for class errorDeepak Nibade2015-03-18
| | | | | | | | | | | | Print interrupt code and channel id for unhandled gr class error. Bug 200010403 Change-Id: Iedceaf4b8b6363b26f1836256875fb9b5c43eded Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/419566 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 03:20:37 -0500