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* gpu: nvgpu: Use TPC_PG_MASK to powergate the TPCDivya Singhatwaria2019-08-02
| | | | | | | | | | | | | | | | | | | | | | | - In GV11B, read fuse_status_opt_tpc_gpc register to read which TPCs are floorswept. - The driver will also read sysfs node: tpc_pg_mask - Based on these two values "can_tpc_powergate" will be set to true or false and mask will be used to write to fuse_ctrl_opt_tpc_gpc register to powergate the TPC. - can_tpc_powergate = true indicates that the mask value sent from userspace is valid and can be used to power gate the desired TPC - can_tpc_powergate = false indicates that the mask value sent from userspace is not valid and cannot be used to power gate the desired TPC. Bug 200532639 Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2159219 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix the race between runtime PM and L2 flushDebarshi Dutta2019-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | gk20a_mm_l2_flush flushes the L2 cache when "struct gk20a->power_on" is true. But it doesn't acquire power lock when doing that, which creates a race that runtime PM might suspend the GPU in the middle of L2 flush. The FB flush looks having the same issue with L2 flushing. This patch fixes that by calling pm_runtime_get_if_in_use at the beginning of the ioctl. This API from PM does a compare and add to the usage count. If the device was not in use, it simply returns without incrementing the usage count as its unnecessary to wake up the GPU(using e.g. a call to gk20a_busy()) as the caches are flushed when the device would be resumed anyways. Bug 2643951 Change-Id: I2417f7ca3223c722dcb4d9057d32a7e065b9e574 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2151532 GVS: Gerrit_Virtual_Submit Reviewed-by: Mark Zhang <markz@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove reversed ordering for deadlockJeremy Ho2019-07-16
| | | | | | | | | | | | | | | | | | | | | | | In some cases, we would get deadlock issue due to there are two locks acquisition on common clk driver's lock and nvgpu driver's locks. At the bug, inconsistent lock ordering problem will come with one thread gets "nvgpu lock -> clk lock" and the other thread gets "clk lock -> nvgpu lock". Slove the latter path with one-time initializing clk_parent entry and use cached data afterward. Bug 2555115 Change-Id: I31c5c2728f406307e7cfd4e555f4db0c163234d8 Signed-off-by: Jeremy Ho <jeremyh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2146727 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: correct param to sysfs_attr_initsumitg2019-06-11
| | | | | | | | | | | | | | | | | | | | | Pass correct attr parameter to sysfs_attr_init(). This fixes the compilation error on enabling debug lock alloc. error: ‘struct device_attribute’ has no member named ‘key’ Bug 200464909 Bug 2604007 Change-Id: Ia0d2672b1c8fe9eb4807b4809892dcdc0cff2669 Signed-off-by: sumitg <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2034954 (cherry picked from commit daa4d7e42b3dcb0dc590b1b3c3356259ee0423d6) Reviewed-on: https://git-master.nvidia.com/r/2132154 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Phoenix Jung <pjung@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add DT support for TPC_PG_POWERGATEDebarshi Dutta2019-05-15
| | | | | | | | | | | | | | | | | | Added support for TPC_PG_POWERGATE during probe for nvgpu via DT. A new DT binding GV11B_FUSE_OPT_TPC_DISABLE is supported by nvgpu driver that checks for valid masks and updates the global tpc_pg_mask flag. Bug 200518434 Change-Id: Ia65ae518b48e36d28de5e9375bc994232f6a9438 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2117783 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fecs ctxsw trace for gm20bDebarshi Dutta2019-05-14
| | | | | | | | | | | | | | | | | | Register gk20a non-arch-specific functions for gm20b gpu_ops.fecs_trace, Register nvgpu_os_linux_ops.fecs_trace.init_debugfs gp10b_fecs_trace_flush is now replaced by gm20b_fecs_trace_flush in fecs_trace_gm20b.* and the fecs_trace_gp10b.* files are removed. Bug 2052906 Change-Id: I245c91ae8e6015b87bafeb3ec023b98fe4c57501 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115247 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: cache gpu clk rate"Peng Liu2019-05-10
| | | | | | | | | | | | | | | | | | | | | | | This reverts commit e9a6d179a42e ("gpu: nvgpu: cache gpu clk rate") - Real clock rate doesn't always equal clock rate requested by caller - call of clk_set_rate() and update of cached_rate are not atomic - Real root cause for Bug 2051688 is in bpmp and gboost design Bug 2538692 Change-Id: I9248e0c69e2271ed2d0070587db59afa6f8160f2 Signed-off-by: Peng Liu <pengliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109708 (cherry picked from commit cc70f89bb4efd106b81c2da5ecd6cbeb69c990d8) Reviewed-on: https://git-master.nvidia.com/r/2113647 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aaron Tian <atian@nvidia.com> Tested-by: Aaron Tian <atian@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add cg and pg functionDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new power/clock gating functions that can be called by other units. New clock_gating functions will reside in cg.c under common/power_features/cg unit. New power gating functions will reside in pg.c under common/power_features/pg unit. Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable elpg and also in gr_gk20a_elpg_protected macro to access gr registers. Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled and slcg_enabled thread safe. JIRA NVGPU-2014 Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2025493 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2108406 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: Change the path in the dependent filesAnuj Gangwar2019-05-03
| | | | | | | | | | | | | | | | | | | | changes in path because we move the nvhost linux user-interface from include/linux/ to include/uapi/linux depends on I2e116dc8f6c33f53c03fb56b923931b6e600b534 Bug 2062672 Change-Id: If2e165852432d5795cf6680cfeb5d4b661fdee74 Signed-off-by: Anuj Gangwar <anujg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1953731 (cherry picked from commit 4e7333967da9cc5a5e4c01288cbc3dd6a25b9fe1) Reviewed-on: https://git-master.nvidia.com/r/2110254 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: using pmu counters for load estimatePeng Liu2019-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | PMU counters #0 and #4 are used to count total cycles and busy cycles. These counts are used by podgov to estimate GPU load. PMU idle intr status register is used to monitor overflow. Overflow rarely occurs because frequency governor reads and resets the counters at a high cadence. When overflow occurs, 100% work load is reported to frequency governor. Bug 1963732 Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69 Signed-off-by: Peng Liu <pengliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1939547 (cherry picked from commit 34df0035194e0203f68f679acdd84e5533a48149) Reviewed-on: https://git-master.nvidia.com/r/1979495 Reviewed-by: Aaron Tian <atian@nvidia.com> Tested-by: Aaron Tian <atian@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Tested-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove gk20a_is_channel_marked_as_tsgSeema Khowala2019-03-18
| | | | | | | | | | | | | | | | | | | | | Use tsg_gk20a_from_ch to get tsg pointer for tsgid of a channel. For invalid tsgid, tsg pointer will be NULL Bug 2092051 Bug 2429295 Bug 2484211 Change-Id: I82cd6a2dc5fab4acb147202af667ca97a2842a73 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2006722 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 13f37f9c70b9ae2e0d179830cded93a0a6f86494 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2025507 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add compatibility versionPreetham Chandru R2019-03-13
| | | | | | | | | | | | | | | | | Add compatibility version to page table and dma mapping structure. Bug 200438879 Change-Id: I04b4601f71ae2b3e75843f39f5445ecca2b16677 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029086 (cherry picked from commit 8bbbd09caa06f7c0f17a48e129d4fd07ce6fa9be) Reviewed-on: https://git-master.nvidia.com/r/2071427 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: more changes to clean loading/unloadingDmitry Pervushin2019-03-11
| | | | | | | | | | | | | | Bug 200487652 Change-Id: Ib52cc6a85a19ea0396c8ab584c5ce9970f93085a Signed-off-by: Dmitry Pervushin <dpervushin@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2020386 (cherry picked from commit 617dff478c3687a08ed5b77f4ac2073b290c57ea) Reviewed-on: https://git-master.nvidia.com/r/2035720 GVS: Gerrit_Virtual_Submit Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: do not release managed resourceDmitry Pervushin2019-03-11
| | | | | | | | | | | | | | | l->bar is a managed resource, it will be released automatically Therefore, there is no need to explicitly unmap it Bug 200487652 Change-Id: Ic543baa770d9cbcf7e7319281c4a27fab4b4b4df Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012324 GVS: Gerrit_Virtual_Submit Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename dma map/umap interfacesPreetham Chandru R2019-02-14
| | | | | | | | | | | | | | | | On Desktop verion, map is called nvidia_p2p_dma_map_pages and umap is called nvidia_p2p_dma_umap_pages. So renamed these two apis to match the desktop version. Bug 200438879 Change-Id: I66301c48b832dfed8c3950678f473c2f82b8761a Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2014940 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename has_timedout and make it thread safeSeema Khowala2019-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently has_timedout variable is protected by wmb at places where it is being set and there is no correspoding rmb whenever has_timedout variable is read. This is prone to errors for concurrent execution. This change is supposed to fix this issue. Rename has_timedout variable of channel struct to ch_timedout. Also to avoid rmb every time ch_timedout is read, ch_timedout_spinlock is added to protect ch_timedout variable for taking care of concurrent execution. Bug 2404865 Bug 2092051 Change-Id: I0bee9f50af0a48720aa8b54cbc3af97ef9f6df00 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1930935 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 1f54ea09e3445d9ca3cf7a69b4967849cc9defc8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2016975 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace input parameter tsgid with pointer to struct tsg_gk20aDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | gv11b_fifo_preempt_tsg needs to access the runlist_id of the tsg as well as pass the tsg pointer to other public functions such as gk20a_fifo_disable_tsg_sched. This qualifies the preempt_tsg to use a pointer to a struct tsg_gk20a instead of just using the tsgid. Jira NVGPU-1461 Change-Id: I01fbd2370b5746c2a597a0351e0301b0f7d25175 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1959068 (cherry picked from commit 1e78d47f15ff050edbb10a88550012178d353288 in rel-32) Reviewed-on: https://git-master.nvidia.com/r/2013725 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: channel: make chid u32Philip Elcan2019-02-05
| | | | | | | | | | | | | | | | | | The chid member of the channel_gk20a struct was being used as a unsigned value. By being declared as an int, it was causing MISRA 10.3 violations for implicit assignment of different types. JIRA NVGPU-647 Change-Id: I7477fad6f0c837cf7ede1dba803158b1dda717af Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1918470 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 1c7bb9b538200a11aa3ef31d72038d8ba820dfca in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008514 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make tsgid a consistent typePhilip Elcan2019-02-05
| | | | | | | | | | | | | | | | | | Different units were declaring tsgid as int or u32. This makes everyone use u32. This change resolves MISRA 10.3 violations for implicit assingment to different types. JIRA NVGPU-647 Change-Id: I78660e737acb0dad76dd538e5dd37f4527cf5acd Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1918469 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit f5cac144a04a3ef83762ecb2e3f405196beffd68 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008513 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvgpu locks to vanilla Linux locksPreetham Chandru Ramchandra2019-01-22
| | | | | | | | | | | | | | | | | | | | | Replace nvgpu locks to vanilla Linux locks. For the custom kernel driver when they include nv-p2p.h, nvgpu/linux/lock.h will not be available because nvgpu/linux/lock.h is not copied to /usr/src/kernel_header_file. Bug 200438879 Change-Id: I55b52c6f791970650388b7d51c4d30b5fe75bbb8 Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1997950 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit eb887094e4f4446e6eed9c17e88f4a36ac5ae972) Reviewed-on: https://git-master.nvidia.com/r/2000831
* gpu: nvgpu: move nv-p2p.h to include/linuxPreetham Chandru Ramchandra2019-01-22
| | | | | | | | | | | | | | | | | Move nv-p2p.h to include/linux so that it is available to external kernel modules to be used. Bug 200438879 Change-Id: I40707fe9f798b3ccf077dbdc942f8d6fc9019458 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1986646 (cherry picked from commit cfe4a2e5e87560519aedb92e2d12e39e09473a54) Reviewed-on: https://git-master.nvidia.com/r/2000830 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: cleanup init thread on destroyPeter Daifuku2018-12-15
| | | | | | | | | | | | | | | | | | | | | | | | In nvgpu_kill_task_pg_init(), call nvgpu_thread_join() if the init thread is no longer running in order to reclaim thread resources. Bug 2452799 JIRA ESRM-437 Change-Id: Id9c67f689027f00039ac2df226ee9c28ad89dd1d Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1967983 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1970058 Reviewed-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Tested-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com>
* gpu: nvgpu: RDMA implementationPreetham Chandru R2018-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | This change adds RDMA supports for tegra iGPU. 1. Cuda Process allocates the memory and passes the VA and size to the custom kernel driver. 2. The custom kernel driver maps the user allocated buf and does the DMA to/from it. 3. Only supports iGPU + cudaHostAlloc sysmem 4. Works only for a given process. 5. Address should be sysmem page aligned and size should be multiple of sysmem page size. 6. The custom kernel driver must register a free_callback when get_page() function is called. Bug 200438879 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I43ec45734eb46d30341d0701550206c16e051106 Reviewed-on: https://git-master.nvidia.com/r/1953780 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add reboot handlerKary Jin2018-10-29
| | | | | | | | | | | | | | | | | | | Add a reboot handler to make sure that nvgpu does not try to busy the GPU if the system is going down. If the system is going down then any number of subsystems nvgpu depends on may already have been deinitialized. Bug 200333709 Bug 200454316 Change-Id: I2ceaf7ca4fb88643310874b5b26937ef44c6e3dd Signed-off-by: Kary Jin <karyj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1927018 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Define functions static if DEBUG_FS=nNicolin Chen2018-10-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When turning off CONFIG_DEBUG_FS, there are build errors: drivers/gpu/nvgpu/os/linux/os_ops_gp106.o: In function `nvgpu_fecs_trace_init_debugfs': os_ops_gp106.c:(.text+0x8): multiple definition of `nvgpu_fecs_trace_init_debugfs' drivers/gpu/nvgpu/os/linux/os_ops_gp10b.o:os_ops_gp10b.c:(.text+0x0): first defined here drivers/gpu/nvgpu/os/linux/os_ops_gv100.o: In function `gp106_therm_init_debugfs': os_ops_gv100.c:(.text+0x0): multiple definition of `gp106_therm_init_debugfs' drivers/gpu/nvgpu/os/linux/os_ops_gp106.o:os_ops_gp106.c:(.text+0x0): first defined here drivers/gpu/nvgpu/os/linux/os_ops_tu104.o: In function `gv100_clk_init_debugfs': os_ops_tu104.c:(.text+0x0): multiple definition of `gv100_clk_init_debugfs' drivers/gpu/nvgpu/os/linux/os_ops_gv100.o:os_ops_gv100.c:(.text+0x10): first defined here This is because those functions aren't marked as static. So this patch just simply fixes the bug. Bug 2284925 Change-Id: I1da39345c653dfb50c509adb0c822b4657646c56 Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929355 (cherry picked from commit 0fd9c84f870731705d6fdbf83d8e94519ff9d3bd) Reviewed-on: https://git-master.nvidia.com/r/1933889 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support for clk.measure_freq for igpuPeter Daifuku2018-09-29
| | | | | | | | | | | | | | | | | | | | | Add support for the measure_freq clock op for igpu: - add nvgpu_clk_measure_freq(), which in turn calls the get_rate() clock op. - Initialize the measure_freq clock op to nvgpu_clk_measure_freq() for native linux and vgpu. JIRA ESRM-398 Change-Id: I8a3b2ee79e29e3491a16f55281494f05cd841b07 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850585 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do nothing on invalid tsg releaseKonsta Holtta2018-09-29
| | | | | | | | | | | | | If nvgpu_ioctl_tsg_open() fails, this file has no priv data yet on release(). In that case there is nothing to free so just return. Jira NVGPU-967 Change-Id: I02dd1bb12a27745a3b28aaa4a943d79d82b14d2c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1847592 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: support clk-arbAparna Das2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | 1. Implement the following vgpu functions to support clk-arb: - vgpu_clk_get_range() to return min and max freqs from supported frequencies - implement vgpu_clk_get_round_rate() which sets rounded rate to input rate. Rounding is handled in RM Server - modify vgpu_clk_get_freqs() to retrieve freq table in IVM memory instead of copying the value in array as part of cmd message. 2. Add support for clk-arb related HALs for vgpu. 3. support_clk_freq_controller is assigned true for vgpu provided guest VM has the privilege to set clock frequency. Bug 200422845 Bug 2363882 Jira EVLR-3254 Change-Id: I91fc392db381c5db1d52b19d45ec0481fdc27554 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812379 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Standardize HAS_SYNCPOINTs checkAlex Waterman2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nvgpu uses many ways to check if sync points are enabled. The four ways used to be: platform->has_syncpoints g->has_syncpoints nvgpu_is_enabled(g, NVPGU_HAS_SYNCPOINTS) gk20a_platform_has_syncpoints() This patch standardizes all usage to now be nvgpu_has_syncpoints() which is based on gk20a_platform_has_syncpoints() - just renamed to be general to nvgpu. All usage of the other forms have now been consolidated. However, under the hood nvgpu_has_syncpoints() does check the is_enabled flag. This flag is now set where g->has_syncpoints used to be set based on the platform data. The basic dependency chain is this: nvgpu_has_syncpoints -> NVGPU_HAS_SYNCPOINTS -> platform->has_syncpoints However, note: there are several places where syncpoints can be disabled if some other driver initialization fails (for ex. host1x). Also note that nvgpu_has_syncpoints() also considers a disable variable set by debugfs. Bug 2327574 Change-Id: Ia2375a80f5f2e27285e6175568dd13e6bb25fd33 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803975 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Disable ELCG for GV100absalam2018-09-27
| | | | | | | | | | | | | | | Disable ELCG as it is not POR for GV100 Disable in Platform data for SKU250 Bug 200446261 Change-Id: I70bddf450c7e41e91498c613f315e0c82ac5e8e2 Signed-off-by: absalam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828022 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu:Add sysfs node for GV100 clocksabsalam2018-09-27
| | | | | | | | | | | | | | Creates sysfs nodes to read clk freq on GV100 Following sysfs nodes are created: gpcclk,xbarclk,sysclk Uses default clock source and counters for measurement Bug 200446261 Change-Id: I6903ba77fbe34e3f486f4b663e70eab4e7c5d662 Signed-off-by: absalam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828030 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gpu: Support multiple tpc-pg masks.Deepak Goyal2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - TPC powergating should be done before calling gk20a_enable_gr_hw. gk20a_enable_gr_hw() issues a GR engine reset. Without this fix, enabling 1 TPC from each PES causes ctxsw timeout error while running GFX Benchmark. - Adds valid tpc-pg mask for 1/2/3/4 active TPC configs. TPC Config - TPC-MASK 4 TPC configuration - 0x0 3 TPC configuration - 0x1/0x2/0x4/0x8 2 TPC configuration - 0x5/0x9/0x6/0xa - We should not write to gr_fe_tpc_pesmask_r() as part of TPC-PG sequence. This register is for debug purpose only. Bug 200442360 Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809772 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move header location of gk20a.hDebarshi Dutta2018-09-25
| | | | | | | | | | | | | | | | | | | | | | | 1) Update header path of gk20a.h files present in os/ to <nvgpu/gk20a.h> 2) os_fence_android_sema.c indirectly was dependent on gk20a.h via semaphore.h. So, added #include <nvgpu/gk20a.h> in os_fence_android_sema.c and replaced the header with forward declaration of struct gk20a in semaphore.h Jira NVGPU-597 Change-Id: I96e23befeb80713f3a399071eb5498f6f580211d Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1842868 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add missing include for K4.14Kyle Guo2018-09-25
| | | | | | | | | | | | | | | | | | Include linux/slab.h in vgpu_linux.c to fix the error of missing kzalloc and kfree when compiling with kernel 4.14. Bug 200428570 Change-Id: I522cfdd47f0f7e27ca5fcb435e916a08ea20309c Signed-off-by: Kyle Guo <kyleg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1820886 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move tsg code to commonKonsta Holtta2018-09-24
| | | | | | | | | | | | | | | tsg_gk20a.c doesn't depend on any specific hardware, so move it to the common directory. Rename the posix tsg file to posix-tsg.c. Jira NVGPU-967 Change-Id: I6e8908a8f6cf43132db8dffe3a99e424e4f764b1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821509 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: Add low level unit test IO mockingNicolas Benech2018-09-24
| | | | | | | | | | | | | | | | | | Add an interface that the unit test modules can use to interact with nvgpu IO accessors. This interface is incredibly simple but not the easiest to use. More simple wrappers will be added later. JIRA NVGPU-1040 Change-Id: I325f09a1739a58ea6bcb1c74834037d6977ce0e8 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741952 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: read GPC mask from h/wDeepak Nibade2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_ctrl_ioctl_gpu_characteristics() we right now just calculate GPC mask in s/w and return to user space But this could give incorrect result as any GPC could be floorswept in h/w Add gops.fuse.fuse_status_opt_gpc() to read GPC floorsweep status from fuse Add gops.gr.get_gpc_mask() to get actual GPC mask from h/w Set these HALs only for dGPUs right now. Fuse register to read GPC mask is not yet supported in simulation and hence simulation boot fails These HALs will be set for iGPU once simulation issue is resolved Use gops.gr.get_gpc_mask() if it is defined in gk20a_ctrl_ioctl_gpu_characteristics() to send the actual GPC mask to user space Jira NVGPUT-132 Change-Id: I3b552de07883328fcfa41d4334ec0d777e04bdd3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822811 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ACR code refactorMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl"Konsta Holtta2018-09-21
| | | | | | | | | | | | | This reverts commit c5810a670d367ae1dc405fcc3108e11265df34bb. Bug 2400508 Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ie2a2c21f9285ff0349c7033fae24766a7117b462 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1837223
* gpu: nvgpu: remove circular dependency between hal.c and gk20a/ddutta2018-09-21
| | | | | | | | | | | | | | | | | gk20a/hal.c depends on HAL init functions in all chips. But all chips also depend on gk20a. That creates a circular dependency. In order to solve the above, move gpu_init_hal and gk20a_detect_chip to common/init/hal_init.c. These methods are declared in include/nvgpu/hal_init.h. Also, the above methods are renamed to nvgpu_init_hal and nvgpu_detect_chip respectively. Jira NVGPU-613 Change-Id: Ib0df90287d4491571e4751475739b75fabd1041b Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827576 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctlaalex2018-09-21
| | | | | | | | | | | | | | | added hal layer for SM exception mask handling for taking care of vitualization case. Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544 Signed-off-by: aalex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816284 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: fix implementation of fls()Philip Elcan2018-09-20
| | | | | | | | | | | | | | | | | The POSIX implementation of fls() wasn't compliant with the Linux which returns fls(0)=0 fls(1)=1, etc. Bug found as result of JIRA NVGPU-1042. Change-Id: Id0279e36332ffe236ed792c013c32f2da841f557 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828361 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: restructure vgpu clk implementationAparna Das2018-09-20
| | | | | | | | | | | | | | | | Move OS agnostic parts of vgpu clk code out of os/linux specific path. This includes implementation sending rpc commands to RM Server. Move Linux specific vgpu clk code to platform vgpu files keeping it consistent with native implementation. Bug 2363882 Jira EVLR-3254 Change-Id: I0aae014ef16415bb356c81e9bfd76bc65206d9fd Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1820674 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: restrict devfreq during active clk_arb set requestsDebarshi Dutta2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | Restrict access to devfreq when there are active set requests in the clk_arbiter. We make the following changes in the patch. 1) Add a global counter in the struct gk20a named clk_arb_global_nr which is used to track the number of active set requests in the system. 2) Anytime a set request is successfully made by the userspace, clk_arb_global_nr is incremented by 1 and during the completion of request(releasing the corresponding file handle), clk_arb_global_nr is decremented by 1. 3) gk20a_scale_target(invoked by devfreq to set the new frequency based on load) atomically checks clk_arb_global_nr. If the value = 0, the code simply continue or else if its > 0, it quits thus making devfreq requests mutually exclusive with the clk_arbiter. Bug 2061372 Change-Id: I5d19de03e45520f4ff8fccb97b1f1589d04c8ab8 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add igpu support for clk_arbiter.Debarshi Dutta2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch constructs clk_arbiter specific code for gp10b as well as gv11b and does the necessary plumbing in the clk_arbiter code. The changes made are as follows. 1) Constructed clk_arb_gp10b.* files which add support for clk_arb related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb. This doesn't have support for debugfs nor the VFUpdateEvent yet and consequently no support for arb->notifications. 2) Added gpcclk specific variables corresponding to every gpc2clk in a given clk_arb related struct. 3) Linux specific support_clk_freq_controller is assigned true in platform_gp10b.c and platform_gv11b.c files. 4) Incremented the clk_arb_worker.put atomic variable during worker_deinit so as to allow the worker thread to be stopped. 5) Added the flag clk_arb_events_supported as part of struct nvgpu_clk_arb. This flag is used to selectively account for the extra refcounting present in OS specific code i.e. nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is reduced during nvgpu_clk_arb_release_completion_dev. Bug 2061372 Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774281 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: expose linux clock controls via HALddutta2018-09-20
| | | | | | | | | | | | | | | | | | | | Expose the linux specific clock implementations via the HAL interface to allow nvgpu to use the controls globally. This patch does the following. 1) Implement a new ops interface and a corresponding linux specific implementation for allowing nvgpu to iterate through a list of available clock frequencies via nvgpu_linux_clk_get_f_points(). 2) Implement nvgpu_linux_clk_get_range(). Bug 2061372 Change-Id: I7ce9a999dbdcd9fafcc84301af148545f6ca97a9 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774280 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE APIAnup Mahindre2018-09-19
| | | | | | | | | | | | Remove the API as it has no use cases. Bug 200445906 Change-Id: Ia2803bd05d78853963011a67091b34ba5bdb3732 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817629 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use single lock for gpu power on-offNitin Kumbhar2018-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | Using two separate locks (poweron_lock and poweroff_lock) allows concurrent gpu power-on and power-off. This shall not happen as driver won't be able to maintain correct gpu state. Use a single power_lock to manage gpu power state. This lock will be used to manage gpu power state from multiple triggers like gpu idle, gpu gc-off, etc. JIRA NVGPU-1100 Change-Id: Ia9b4aeda024a5844ae9f182d453cd6341876680a Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827812 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel_sync_gk20a.* to common directoryDebarshi Dutta2018-09-18
| | | | | | | | | | | | | | | | | | | | 1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they donot program any hardware registers. Also as an add-on rename channel_sync_gk20a.* to channel_sync.* and update the headers in required files. 2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also, corresponding syncpt and semaphore versions of the struct alongwith related methods are renamed by removing "gk20a" from their names and adding "nvgpu". 3) Add misra-c cleanups Jira NVGPU-1086 Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812594 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Don't include MC HW header in vgpu LinuxTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | vgpu Linux code does not access MC registers. Remove the include directive for hw_mc_gk20a.h. JIRA NVGPU-954 Change-Id: I38ccfd6613256fab03add0a4f71701d5a0fa1f2a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813521 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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