| Commit message (Collapse) | Author | Age |
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Move OS agnostic parts of vgpu clk code out of os/linux specific
path. This includes implementation sending rpc commands to
RM Server. Move Linux specific vgpu clk code to platform vgpu files
keeping it consistent with native implementation.
Bug 2363882
Jira EVLR-3254
Change-Id: I0aae014ef16415bb356c81e9bfd76bc65206d9fd
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1820674
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Restrict access to devfreq when there are active set requests in the
clk_arbiter. We make the following changes in the patch.
1) Add a global counter in the struct gk20a named clk_arb_global_nr which
is used to track the number of active set requests in the system.
2) Anytime a set request is successfully made by the userspace,
clk_arb_global_nr is incremented by 1 and during the completion of
request(releasing the corresponding file handle), clk_arb_global_nr is
decremented by 1.
3) gk20a_scale_target(invoked by devfreq to set the new frequency based
on load) atomically checks clk_arb_global_nr. If the value = 0, the
code simply continue or else if its > 0, it quits thus making devfreq
requests mutually exclusive with the clk_arbiter.
Bug 2061372
Change-Id: I5d19de03e45520f4ff8fccb97b1f1589d04c8ab8
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790002
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This patch constructs clk_arbiter specific code for gp10b as well as
gv11b and does the necessary plumbing in the clk_arbiter code. The
changes made are as follows.
1) Constructed clk_arb_gp10b.* files which add support for clk_arb
related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb.
This doesn't have support for debugfs nor the VFUpdateEvent yet and
consequently no support for arb->notifications.
2) Added gpcclk specific variables corresponding to every gpc2clk in
a given clk_arb related struct.
3) Linux specific support_clk_freq_controller is assigned true in
platform_gp10b.c and platform_gv11b.c files.
4) Incremented the clk_arb_worker.put atomic variable during
worker_deinit so as to allow the worker thread to be stopped.
5) Added the flag clk_arb_events_supported as part of struct
nvgpu_clk_arb. This flag is used to selectively account for the extra
refcounting present in OS specific code i.e.
nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is
reduced during nvgpu_clk_arb_release_completion_dev.
Bug 2061372
Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774281
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Expose the linux specific clock implementations via the HAL
interface to allow nvgpu to use the controls globally. This patch
does the following.
1) Implement a new ops interface and a corresponding linux specific
implementation for allowing nvgpu to iterate through a list of
available clock frequencies via nvgpu_linux_clk_get_f_points().
2) Implement nvgpu_linux_clk_get_range().
Bug 2061372
Change-Id: I7ce9a999dbdcd9fafcc84301af148545f6ca97a9
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774280
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Remove the API as it has no use cases.
Bug 200445906
Change-Id: Ia2803bd05d78853963011a67091b34ba5bdb3732
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1817629
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Using two separate locks (poweron_lock and poweroff_lock)
allows concurrent gpu power-on and power-off. This shall
not happen as driver won't be able to maintain correct
gpu state.
Use a single power_lock to manage gpu power state. This
lock will be used to manage gpu power state from multiple
triggers like gpu idle, gpu gc-off, etc.
JIRA NVGPU-1100
Change-Id: Ia9b4aeda024a5844ae9f182d453cd6341876680a
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827812
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they
donot program any hardware registers. Also as an add-on rename
channel_sync_gk20a.* to channel_sync.* and update the headers
in required files.
2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also,
corresponding syncpt and semaphore versions of the struct alongwith
related methods are renamed by removing "gk20a" from their names and
adding "nvgpu".
3) Add misra-c cleanups
Jira NVGPU-1086
Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812594
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vgpu Linux code does not access MC registers. Remove the include
directive for hw_mc_gk20a.h.
JIRA NVGPU-954
Change-Id: I38ccfd6613256fab03add0a4f71701d5a0fa1f2a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813521
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Move implementation of MC HAL to common/mc. Also bump gk20a
implementation to gm20b.
gk20a_mc_boot_0 was used via a HAL, but we have only one possible
implementation. It also has to be anyway called directly to detect
which HALs to assign, so make it a true common function.
mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c
so move it there.
JIRA NVGPU-954
Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813519
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If platform didn't set railgate/unrailgate callbacks, it means it does
not support railgate.
It avoids vgpu calling tegra_fuse_clock_disable/enable.
Bug 200436689
Jira EVLR-2983
Change-Id: I759dc23145429a59f40cec6e9c1de9536dcf43c4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1821663
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This reverts commit 4f01d6a9b9a54cf6042db157de0d40965077f6a2.
Change-Id: I604acef2a1f322a521df3ceb39e7df5d249a5716
Reviewed-on: https://git-master.nvidia.com/r/1818387
Reviewed-by: Emad Mir <emir@nvidia.com>
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This shouldn't happen, but is dangerous enough to warrant its own
warning if it does. A message might help debug a rare corruption bug.
Bug 2038362
Change-Id: I7915760fc31e7acaa0148a10f9acae303d53ea95
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1815863
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Bug 2343124
JIRA NVGPU-1065
Change-Id: I43a436673117af8ac2490d075cea07532f01af0b
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818164
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NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was
resident in engine or not.
Regops are broken down into batches of 128 and each batch is executed
together. Since there only 32 bits were available in IOCTL args, returning
is ctx was resident isn't possible for all batches.
Hence return if the ctx was resident for the first batch.
Bug 200445575
Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812975
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Add fecs trace debugfs initialization as an os op. The
debugfs nodes are set up for gpu versions which call
gk20a_fecs_trace_init().
JIRA NVGPU-602
Change-Id: I606ec31acbf04f633500be4c342db32f3f537794
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812449
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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- Add gv11b specific init function
- This init function will set a chip specific
value for emc3d_ratio and then call the gp10b
init function
Bug 200438743
Change-Id: If6128c2156e4b65086827615909ed17cce1d9224
Signed-off-by: Mubushir Rahman <mubushirr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808673
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page_idx is an element of the struct nvgpu_semaphore_pool, defined in
include/nvgpu/semaphore.h file.
page_idx can not be negative so changing it from int to u64 and its
related changes in various files.
This also fixes MISRA 10.4 violations in these files.
Jira NVGPU-992
Change-Id: Ie9696dab7da9e139bc31563783b422c84144f18b
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801632
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Add sysfs to indicate if GPU has ever been powered on.
This allows an application to avoid booting dGPU, when there is no
need for it. For instance the fan controller can check this value,
and refrain from booting the GPU, only to check the temperature.
This will save power, and also avoid locking some registers which
currently prevent from using VBIOS update tool.
Bug 200408936
Change-Id: I6344001e91e9eee8762ff8b227ca6698d8c6786f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1802098
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Update nvgpu_ltc_alloc_cbc() API to accept a flag for vidmem allocation
and allocate CBC memory into vidmem if flag is set
Bug 2180284
Jira NVGPUT-12
Change-Id: Ia6b9bb670c9fab6b5787de15526fcc753d702a73
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805468
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Below regops HALs are not being called from anywhere, so remove them
gops.regops.get_runcontrol_whitelist_ranges()
gops.regops.get_runcontrol_whitelist_ranges_count()
gops.regops.get_qctl_whitelist_ranges()
gops.regops.get_qctl_whitelist_ranges_count()
HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it
was originally only needed for gk20a which is not unsupported
So remove this HAL and its call too
Jira NVGPU-620
Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813106
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channel_gk20a is clear from chip specifics and from most dependencies,
so move it under the common directory.
Jira NVGPU-967
Change-Id: I41f2160b96d4ec84064288ecc22bb360e82352df
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810578
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This migrates the common DMA code (os agnostic) to the
common directory. This new unit will be the common DMA
allocator that lets users allocate SYSMEM, VIDMEM, or
either. Other units will be responsible for actually
handling the mechanics of allocating VIDMEM or SYSMEM.
Also update the names of the DMA related files so that
tmake doesn't complain about duplicate C file names. To
do this call the common DMA file dma.c and prepend the
OS to the other DMA files. So now we have:
common/mm/dma.c
os/posix/posix-dma.c
os/linux/linux-dma.c
JIRA NVGPU-990
Change-Id: I22d2d41803ad89be7d9c28f87864ce4fedf10836
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799807
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Move debugfs related part of pmgr to linux files.
JIRA NVGPU-603
Change-Id: I478491e06e2e7cdbe3826166aafd8491d1e6c1e7
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801086
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Move debugfs related code of therm from common driver to linux
specific part of the driver. gp106_therm_debugfs_init()
is updated to use nvgpu_os_linux_ops.
This also affects gv100 as gp106_therm_debugfs_init is used
for gv100 as well.
JIRA NVGPU-603
Change-Id: Ia293d14599bc0c91fd1e917b5a430bd8f3d96e56
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797906
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Use nvgpu_os_linux_ops to initialize gm20b debugfs
functions.
gm20b_clk_init_debugfs() will be invoked during initialization
from nvgpu_finalize_poweron_linux().
JIRA NVGPU-603
Change-Id: Ie89e427cc589ae14e1e7f5918d918126fb4afd77
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797905
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Move linux dependencies and CONFIG_DEBUG_FS to linux specific
code from common driver for gp106 clk debugfs. There is no
code change in functions moved from gp106/clk_gp106.c.
It uses nvgpu_os_linux_ops to add gp106 specific clk debugfs
ops. The linux specific part of nvgpu driver uses this op
to initialize gp106 clk debugfs.
As gv100 also uses gp106 clk debugfs ops, set up os ops for
gv100.
JIRA NVGPU-603
Change-Id: Ib55ef051b13366e5907e1d05376bb18bf42c8653
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797904
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Adding a comptag_mem_deduct in the platform_gk20a has certain problems:
1) It's not really convenient for platform users to configure it.
2) All products using the same GPU have to share the same configuration.
So this patch moves this comptag_mem_deduct from struct platform_gk20a
to struct gr_gk20a (per device). And it adds an sysfs node for products
or platform users to easily configure from user space.
Note: The comptag memory will not be allocated until the GPU driver goes
through the final poweron routine. So the user space has a small window
to configure this sysfs node.
Bug 2327574
Bug 2284925
Change-Id: Ie7d00b082704e422645c0ea254b59e22f9fc3b7f
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810334
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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There are two (would be more) places calculating the ram size in MB from
page numbers, so this patch just simply adds a macro for simplification.
Bug 2327574
Bug 2284925
Change-Id: Ie5dc387d547e1b8ce98946f0637dc17a6897e5a6
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810333
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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g->clk_arb is currently initialized as a part of gk20a_finalize_poweron().
Any subsequent call to gk20a_finalize_poweron reinitializes the clk_arb
and leading to memory leaks. This is resolved by protecting the
g->clk_arb initialization with a mutex clk_arb_enable_lock in struct
gk20a. We skip initializing the g->clk_arb if its not NULL.
Bug 2061372
Change-Id: I59158e0a5e4c827fdbd6d9ea2d04c78d0986347a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1811650
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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print the correct error code when the sync_fence construction fails
instead of just an error message.
Bug 200421587
Change-Id: I9d6f9df8bec0e43d0a1198fbe7ab2631f12f572a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809642
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Declare the ID table as a device table to enable autoloading
of the module as the device tree is instantiated.
Change-Id: I4f29259a0a9af6b72be99ed27789ee4d5d7a1aa2
Signed-off-by: Preetha Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809174
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.
In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.
Bug 200412641
Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Remove the usage of NVGPU_CTXSW_FILTER_ISSET splattered
across nvgpu, and replace with a MACRO defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "uapi/linux/nvgpu.h" from common code.
EVLR-3078
Change-Id: I60b0e1627576a4b255671d58530d8c773ea6154c
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803210
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Convert linux nvgpu ctxsw tags type of the form
of NVGPU_CTXSW_TAG_* into common nvgpu ctxsw tags
type of the form of NVGPU_GPU_CTXSW_TAG_*
EVLR-3078
Change-Id: I337487722c103c05003457f74ad6e05bf3bd38fc
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803209
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Remove the usage of nvgpu_ctxsw_trace_entry splattered
across nvgpu, and replace with a struct defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "asm/barrier.h" as "nvgpu/barrier.h" is already
included.
EVLR-3078
Change-Id: Iabfb105b891b0078ed326a8047ef14ebe1888cf2
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803208
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The common channel header was missing include guards, so add them. Also
rename the Linux channel header guard that was in conflict.
Jira NVGPU-967
Change-Id: If782407ef1497202196a362893ef9c1b2330977a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807372
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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GM20B GPCPLL registers are accessed via sys address space with the
exception of the last dvfs2 register that can be accessed only through
bcast address. However, in debugfs loop dvfs2 sys address should be
used as loop terminator; otherwise, loop body is never executed, and
GPCPLL registers debugfs node is broken. Fixed it in this commit.
Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808784
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debug_clk.c implements clk debugfs of gm20b. Rename the file
to reflect clk debugfs functions implemented for gm20b.
JIRA NVGPU-603
Change-Id: I6ff4b71abe400b8fc2a8d79e12e53e2048ccdc05
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797903
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Currently only cde uses nvgpu_os_linux_ops to set up linux
specific ops. Move nvgpu_os_linux_ops of a gpu to a common
file so that those can be reused for other os ops of that
gpu.
JIRA NVGPU-603
Change-Id: Icf1ff275d3832229137f730fe8183b8015e82673
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797902
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h
JIRA-597
Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The comptag allocates memory based on the available total RAM, which
theoretically should be the MAX physical RAM size however practically
should deduct the part being taken by the running system. Otherwise,
the taken memory part will never get used and wasted.
This change adds a comptag_mem_deduct to each platform and to allow
them to assign the deductible value based on their own use cases so
as to save memory.
Bug 2327574
Bug 2284925
Change-Id: I124e20a66183c22723c34a7ec6ce34832c12f02e
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804157
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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nvgpu_os_fence_syncpt_create returns ERR_PTR instead of NULL whenever
its unable to construct a valid struct sync_fence instance. The
current code is not handled to detect errors returned using
ERR_PTR. This patch replaces the !fence check with IS_ERR() that
handles the return correctly.
Bug 200421587
Change-Id: I0ecfa8a651b8d5b743d11aab80d7a4cd71be8b1a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804509
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add READ_SM_ERROR IOCTL support to TSG level.
Moved the struct to save the sm_error details
from gr to tsg as the sm_error support is context
based, not global.
Also corrected MISRA 21.1 error in header file.
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and
nvgpu_dbg_gpu_ioctl_read_single_sm_error_state
functions are modified to use the tsg struct
nvgpu_tsg_sm_error_state.
Bug 200412642
Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794856
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Many files used declarations from timers.h implicitly via another header
file(s). Add several #includes explicitly to their users.
Jira NVGPU-967
Change-Id: I88b515061db87c69bd85e3655b74d0271a80d9bf
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804611
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove a few unnecessary includes from channel_gk20a.h and add them to c
files where needed.
Jira NVGPU-967
Change-Id: Ic38132c776a56b6966424806faab7871575b6c10
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804609
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Do a simple rename of channel_gk20a.c to common/fifo/channel.c. Header
cleanup and the like will soon follow. Also rename the os-specific files
to have unique names across directories because tmake requires that.
Jira NVGPU-967
Change-Id: I302bbbbe29735264e832378d444a176a4023e3e1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804608
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Changed the enum gmmu_pgsz_gk20a into macros and changed all the
instances of it.
The enum gmmu_pgsz_gk20a was being used in for loops, where it was
compared with an integer. This violates MISRA rule 10.4, which only
allows arithmetic operations on operands of the same essential type
category. Changing this enum into macro will fix this violation.
JIRA NVGPU-993
Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795593
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add a WAR for gm20b that allows us to force the PMU VM to use
128K large pages. For some reason setting the small page size
to 64K breaks the PMU boot. Unclear why. Bug needs to be filed
and fixed. Once fixed this patch can and should be reverted.
Bug 200105199
Change-Id: I2b4c9e214e2a6dff33bea18bd2359c33364ba03f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1782769
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This change frees tsg_private structure in nvgpu_ioctl_tsg_open() when
gk20a_busy() fails and avoids a memory leak.
Bug 2268533
JIRA NVGPU-1016
Change-Id: I0428cc40e042b881537f7cb597e5ebeaad815b32
Signed-off-by: Preetha Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800955
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHE as it is unused and has
a broken implementation.
Bug 200439908
Change-Id: Iab6f08cf3dd4853ba6c95cbc8443331bf505e514
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800797
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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