| Commit message (Collapse) | Author | Age |
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Use nvgpu_os_linux_ops to initialize gm20b debugfs
functions.
gm20b_clk_init_debugfs() will be invoked during initialization
from nvgpu_finalize_poweron_linux().
JIRA NVGPU-603
Change-Id: Ie89e427cc589ae14e1e7f5918d918126fb4afd77
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797905
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Move linux dependencies and CONFIG_DEBUG_FS to linux specific
code from common driver for gp106 clk debugfs. There is no
code change in functions moved from gp106/clk_gp106.c.
It uses nvgpu_os_linux_ops to add gp106 specific clk debugfs
ops. The linux specific part of nvgpu driver uses this op
to initialize gp106 clk debugfs.
As gv100 also uses gp106 clk debugfs ops, set up os ops for
gv100.
JIRA NVGPU-603
Change-Id: Ib55ef051b13366e5907e1d05376bb18bf42c8653
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797904
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Adding a comptag_mem_deduct in the platform_gk20a has certain problems:
1) It's not really convenient for platform users to configure it.
2) All products using the same GPU have to share the same configuration.
So this patch moves this comptag_mem_deduct from struct platform_gk20a
to struct gr_gk20a (per device). And it adds an sysfs node for products
or platform users to easily configure from user space.
Note: The comptag memory will not be allocated until the GPU driver goes
through the final poweron routine. So the user space has a small window
to configure this sysfs node.
Bug 2327574
Bug 2284925
Change-Id: Ie7d00b082704e422645c0ea254b59e22f9fc3b7f
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810334
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There are two (would be more) places calculating the ram size in MB from
page numbers, so this patch just simply adds a macro for simplification.
Bug 2327574
Bug 2284925
Change-Id: Ie5dc387d547e1b8ce98946f0637dc17a6897e5a6
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810333
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g->clk_arb is currently initialized as a part of gk20a_finalize_poweron().
Any subsequent call to gk20a_finalize_poweron reinitializes the clk_arb
and leading to memory leaks. This is resolved by protecting the
g->clk_arb initialization with a mutex clk_arb_enable_lock in struct
gk20a. We skip initializing the g->clk_arb if its not NULL.
Bug 2061372
Change-Id: I59158e0a5e4c827fdbd6d9ea2d04c78d0986347a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1811650
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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print the correct error code when the sync_fence construction fails
instead of just an error message.
Bug 200421587
Change-Id: I9d6f9df8bec0e43d0a1198fbe7ab2631f12f572a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809642
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Declare the ID table as a device table to enable autoloading
of the module as the device tree is instantiated.
Change-Id: I4f29259a0a9af6b72be99ed27789ee4d5d7a1aa2
Signed-off-by: Preetha Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809174
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Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.
In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.
Bug 200412641
Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
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- Remove the usage of NVGPU_CTXSW_FILTER_ISSET splattered
across nvgpu, and replace with a MACRO defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "uapi/linux/nvgpu.h" from common code.
EVLR-3078
Change-Id: I60b0e1627576a4b255671d58530d8c773ea6154c
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803210
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Convert linux nvgpu ctxsw tags type of the form
of NVGPU_CTXSW_TAG_* into common nvgpu ctxsw tags
type of the form of NVGPU_GPU_CTXSW_TAG_*
EVLR-3078
Change-Id: I337487722c103c05003457f74ad6e05bf3bd38fc
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803209
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- Remove the usage of nvgpu_ctxsw_trace_entry splattered
across nvgpu, and replace with a struct defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "asm/barrier.h" as "nvgpu/barrier.h" is already
included.
EVLR-3078
Change-Id: Iabfb105b891b0078ed326a8047ef14ebe1888cf2
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803208
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The common channel header was missing include guards, so add them. Also
rename the Linux channel header guard that was in conflict.
Jira NVGPU-967
Change-Id: If782407ef1497202196a362893ef9c1b2330977a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807372
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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GM20B GPCPLL registers are accessed via sys address space with the
exception of the last dvfs2 register that can be accessed only through
bcast address. However, in debugfs loop dvfs2 sys address should be
used as loop terminator; otherwise, loop body is never executed, and
GPCPLL registers debugfs node is broken. Fixed it in this commit.
Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808784
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debug_clk.c implements clk debugfs of gm20b. Rename the file
to reflect clk debugfs functions implemented for gm20b.
JIRA NVGPU-603
Change-Id: I6ff4b71abe400b8fc2a8d79e12e53e2048ccdc05
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797903
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Currently only cde uses nvgpu_os_linux_ops to set up linux
specific ops. Move nvgpu_os_linux_ops of a gpu to a common
file so that those can be reused for other os ops of that
gpu.
JIRA NVGPU-603
Change-Id: Icf1ff275d3832229137f730fe8183b8015e82673
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797902
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In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h
JIRA-597
Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
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The comptag allocates memory based on the available total RAM, which
theoretically should be the MAX physical RAM size however practically
should deduct the part being taken by the running system. Otherwise,
the taken memory part will never get used and wasted.
This change adds a comptag_mem_deduct to each platform and to allow
them to assign the deductible value based on their own use cases so
as to save memory.
Bug 2327574
Bug 2284925
Change-Id: I124e20a66183c22723c34a7ec6ce34832c12f02e
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804157
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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nvgpu_os_fence_syncpt_create returns ERR_PTR instead of NULL whenever
its unable to construct a valid struct sync_fence instance. The
current code is not handled to detect errors returned using
ERR_PTR. This patch replaces the !fence check with IS_ERR() that
handles the return correctly.
Bug 200421587
Change-Id: I0ecfa8a651b8d5b743d11aab80d7a4cd71be8b1a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804509
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Add READ_SM_ERROR IOCTL support to TSG level.
Moved the struct to save the sm_error details
from gr to tsg as the sm_error support is context
based, not global.
Also corrected MISRA 21.1 error in header file.
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and
nvgpu_dbg_gpu_ioctl_read_single_sm_error_state
functions are modified to use the tsg struct
nvgpu_tsg_sm_error_state.
Bug 200412642
Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794856
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Many files used declarations from timers.h implicitly via another header
file(s). Add several #includes explicitly to their users.
Jira NVGPU-967
Change-Id: I88b515061db87c69bd85e3655b74d0271a80d9bf
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804611
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Remove a few unnecessary includes from channel_gk20a.h and add them to c
files where needed.
Jira NVGPU-967
Change-Id: Ic38132c776a56b6966424806faab7871575b6c10
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804609
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Do a simple rename of channel_gk20a.c to common/fifo/channel.c. Header
cleanup and the like will soon follow. Also rename the os-specific files
to have unique names across directories because tmake requires that.
Jira NVGPU-967
Change-Id: I302bbbbe29735264e832378d444a176a4023e3e1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804608
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Changed the enum gmmu_pgsz_gk20a into macros and changed all the
instances of it.
The enum gmmu_pgsz_gk20a was being used in for loops, where it was
compared with an integer. This violates MISRA rule 10.4, which only
allows arithmetic operations on operands of the same essential type
category. Changing this enum into macro will fix this violation.
JIRA NVGPU-993
Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795593
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Add a WAR for gm20b that allows us to force the PMU VM to use
128K large pages. For some reason setting the small page size
to 64K breaks the PMU boot. Unclear why. Bug needs to be filed
and fixed. Once fixed this patch can and should be reverted.
Bug 200105199
Change-Id: I2b4c9e214e2a6dff33bea18bd2359c33364ba03f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1782769
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This change frees tsg_private structure in nvgpu_ioctl_tsg_open() when
gk20a_busy() fails and avoids a memory leak.
Bug 2268533
JIRA NVGPU-1016
Change-Id: I0428cc40e042b881537f7cb597e5ebeaad815b32
Signed-off-by: Preetha Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800955
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHE as it is unused and has
a broken implementation.
Bug 200439908
Change-Id: Iab6f08cf3dd4853ba6c95cbc8443331bf505e514
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800797
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This flag - has_physical_mode - doesn't seem to do much other than
force the PTE/PDE and inst block addresses to be physical instead
of potentially IOMMUed.
There is a reason to do this on volta (nvlink not being IOMMU'able
being the primary reason) but this flag is too general it seems.
The flag was being enabled on all native platforms. The problem is
that some page tables (the maxwell small page directories) could
be larger than 4KB which meant that the allocation used for them
could be potentially discontiguous. Discontiguous page directories
obviously is incorrect.
This patch deletes the has_physical_mode flag and instead replaces
the places where it's checked with a check for nvlink being
enabled. Since we _do_ want to program phyiscal PDEs and PTEs for
NVLINK devices (regardless of IOMMU status they always access
memory by physical address) we need a check for NVLINK state.
Bug 200414723
Change-Id: I09ad86b12d8aabcf9648a22503f4747fd63514dd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792163
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- fetch ecc info from RM server and create sysfs nodes
- new file ecc_vgpu.c for platform-independent code
- add 2 new commands: GET_ECC_INFO and GET_ECC_COUNTER_VALUE
JIRA EVLR-2590
Change-Id: I040a9fcd23326e432ca93e9a028319f9c1c570f0
Signed-off-by: Kyle Guo <kyleg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777428
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The nvgpu_ioctl_tsg_open() does not make sure that GPU is
unpowergated. Due to this it leads to kernel
panic when GPU registers are accessed when powergated.
__gk20a_warn_on_no_regs+0x38/0x58 [nvgpu]
__nvgpu_readl+0x74/0xc8 [nvgpu]
nvgpu_readl+0x28/0x60 [nvgpu]
xxxxx_ce_get_num_pce+0x28/0x70 [nvgpu]
xxxxx_fifo_init_eng_method_buffers+0x64/0x1c0 [nvgpu]
gk20a_tsg_open+0x110/0x1e0 [nvgpu]
nvgpu_ioctl_tsg_open+0x88/0x100 [nvgpu]
gk20a_ctrl_dev_ioctl+0x734/0x2388 [nvgpu]
do_vfs_ioctl+0xc4/0x918
SyS_ioctl+0x94/0xa8
This change fixes this issue by calling gk20a_busy()/gk20a_idle()
in nvgpu_ioctl_tsg_open()
Bug 2268533
JIRA NVGPU-1016
Change-Id: I578289e7eb60295d6b6169b754a5cc60f7546fd5
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794324
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This reverts commit b79c350d68bac79ec9ed80ef5f19f15a0d0eedf4.
Underlying PRAMIN infrastructure enforces 4 byte aligned size only,
so the API should enforce that too
Bug 2285052
Change-Id: I2b4a209edd479d72992708b35e1d52940ff20637
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795653
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Removed the utils.h include from gk20a.h
utils.h is included in those files which
make use of the macros in utils.h
JIRA NVGPU-1005
Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1785952
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We right now define HAL exec_reg_ops() under gops.dbg_session_ops operations
But we have separate gops.regops operations for all the regops and this would
be logically correct place for exec_reg_ops()
Move exec_reg_ops() from gops.dbg_session_ops to gops.regops
Also rename it to exec_regops()
Jira NVGPU-620
Change-Id: If4f70639ffbc892c605f7540a83bce12ed821b52
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794999
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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CBC base needs to be aligned to 64KB. On Linux this is
achieved making compbit backing size multiple of 64KB.
However QNX nvmap alloc function does not allocate
memory aligned to requested size and needs to overallocate
to satisfy alignment requirement. Make cbc alloc function OS
specific to be able to modify QNX code.
Also align cbc base address to 64KB before writing to CBC BASE
register.
Bug 200426427
Change-Id: Ic867501403f2e2a4ba41ad5a8ed6f9c5c8ffa3f4
Signed-off-by: Aparna Das <aparnad@nvidia.com>
(cherry picked from commit 3f1e1133a46ebfc9763c649d7b839d069cae5a36)
Reviewed-on: https://git-master.nvidia.com/r/1786046
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The error returned from the execution of exec_reg_ops was ignored
leading to not propagating the error values to the caller methods.
This patch handles the error occurence in the exec_reg_ops call.
Bug 2245743
Change-Id: I0d696c116fc1b2fce0e14ac7a05e1d85b5d18129
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775818
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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clk_arb.h and gk20a.h has circular dependencies to each other. This is
removed by forward declaring struct gk20a in clk_arb.h and removing the
header gk20a.h from clk_arb.h and similarly forward declaring struct
nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h
alongwith putting headers in every execution unit which calls clk_arb.h
related methods.
JIRA NVGPU-597
Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790915
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is
added to dbg session.
Currently support SM_EXCEPTION_TYPE_MASK_FATAL type
If this type is set then the code will skip RC recovery,
instead trigger CILP preemption.
bug 200412641
JIRA NVGPU-702
Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729792
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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ce2.c is free of all Linux'isms and can be moved to
the common code, so that it can be used by other
OS'es.
VQRM-3705
Change-Id: Id4644a24188e9af2ba5f6875d1b8bc58b4450519
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792100
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The sysfs_attr_init accepts pointer of struct attribute instead of
struct device_attribute. This patch fixes build error when
CONFIG_DEBUG_LOCK_ALLOC is enabled.
Bug 200432223
Change-Id: Id655ca18102c5252485db378ba2499a66d758882
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786590
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gpc_tpc_mask uses gpc/tpc IDs directly read from fuse, so it needs to
use max_gpc_count for any possible cases rather not gpc_count.
Bug 2302005
Change-Id: I903ee3e0c10c4b329dd0d76c40d3516dc36ed303
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790464
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In nvgpu_ioctl_channel_reg_ops(), we right now first check if context is
allocated or not and if context is not allocated we fail the regops operation
But it is possible that the regops operation only includes global regops which
does not need global context allocated
So move this global context check from nvgpu_ioctl_channel_reg_ops() to
exec_regops_gk20a() and only if we have context ops included in the regops
Bug 200431958
Change-Id: Iaa4953235d95b2106d5f81a456141d3a57603fb9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1789262
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add support for PCI device id 0x1efa which has same driver data as of 0x1eba
device
Change-Id: If3d53fe116c711bf63a10eae0e731537b3705bc1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1788694
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The use of the _THIS_IP_ macro in nvgpu introduces two separate
MISRA Rule 11.6 violations.
The first is when when the label address (which gcc generates as
a void *) is cast to an unsigned long and the second is when that
unsigned long is cast back to a void * in the timer and kmem code
that track the value.
Skipping the intermediate use of unsigned long eliminates these
violations. To do this, references to _THIS_IP_ are replaced
with a new (compliant) _NVGPU_GET_IP_ macro.
JIRA NVGPU-895 : MISRA Rule 11.6 violations
Change-Id: I5ea999d8e2b467257fa190b485fa971adcbd0a2b
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774531
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h
JIRA NVGPU-597
Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For IOCTL NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY, we do not allow size of buffer
which is not 4 byte aligned
Remove this hard restriction and allow non 4 byte aligned buffer sizes too
since we don't really need to enforce this restriction
Bug 2265535
Change-Id: Ic4d60604be3698e8629f2b289c9e2d19e20ea525
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784511
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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During driver remove, if nvlink is set up, gracefully
shut it down so that it can be enumerated again.
Bug 1987855
Change-Id: Ibd83a5e29364b22264e689aa879569a9cccf0f79
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1746073
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In order to avoid the circular dependencies,
rearrange the static inline functions from
gk20a.h file.
Moved gk20a_gr_flush_channel_tlb function to
gr_gk20a.c and removed the #include gr_gk20a.h
from gk20a.h
Added a helper function utils.h to
move all generic static inline functions which
have no reference to gpu related structures.
ptimer related functions are moved to
ptimer.h
Implementations for as and pmu are moved to
corresponding files.
JIRA NVGPU-624
Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1781941
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added debugfs node under ltc directory with name:
intr_illegal_compstat_enable
Enabling/disabling of ltc_illegal_compstat intr is
possible through debugfs node.
Since ltc state is lost with rail gate, this setting is
cached and will be populated during ltc initialization.
Bug 2099406
Change-Id: I4bf62228dfd2bbb94f87f923f9f4f6e5ad0b07f0
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774683
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- adds static tpc-powergating through sysfs.
- active tpc count will remain till the GPU/systems is not booted again.
- tpc_pg_mask can be written only after GPU probe finishes and
GPU boot is triggered.
Note:
To be able to use this feature, we need to change boot/init
scripts of the OS(used with nvgpu driver) to write to sysfs nodes before
posting discover image size query to FECS.
Bug 200406784
Change-Id: Id749c7a617422c625f77d0c1a9aada2eb960c4d0
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742422
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- create common file common/ecc.c which include common functions for add
ecc counters and remove counters.
- common code will create a list of all counter which make it easier to
iterate all counters.
- Add chip specific file for adding ecc counters.
- add linux specific file os/linux/ecc_sysfs.c to export counters to
sysfs.
- remove obsolete code
- MISRA violation for using snprintf is not solved, tracking with
jira NVGPU-859
Jira NVGPUT-115
Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763536
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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nvmemleak detected memleak in the error path of gk20a_ctrl_dev_open.
nvkmemleak: Writing 'scan' to /sys/kernel/debug/kmemleak.
unreferenced object 0xffffffc0a6fffa80 (size 128):
comm "nvgpu_gpu_zcull", pid 9675, jiffies 4294948258 (age 195.764s)
hex dump (first 32 bytes):
10 28 09 ba c0 ff ff ff 00 00 69 b2 c0 ff ff ff .(........i.....
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
backtrace:
[<ffffff800824cec4>] __kmalloc+0x26c/0x308
[<ffffff8000e70990>] __nvgpu_kzalloc+0x30/0x88 [nvgpu]
[<ffffff8000e71f70>] gk20a_ctrl_dev_open+0x60/0x108 [nvgpu]
[<ffffff800827ef20>] chrdev_open+0xb8/0x1d0
[<ffffff8008274654>] do_dentry_open+0x224/0x330
[<ffffff8008275c60>] vfs_open+0x58/0x90
[<ffffff800828aeb4>] do_last+0x3e4/0xd98
[<ffffff800828b90c>] path_openat+0xa4/0x2d8
[<ffffff800828cf0c>] do_filp_open+0x84/0x108
[<ffffff800827610c>] do_sys_open+0x164/0x278
[<ffffff80082762a4>] SyS_openat+0x3c/0x50
[<ffffff8008083600>] el0_svc_naked+0x34/0x38
[<ffffffffffffffff>] 0xffffffffffffffff
Bug 200422739
Change-Id: I4ad03713ef5c8fc0e213bf4b649d38829a54a1ac
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777656
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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