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* gpu: nvgpu: remove unused register accessors for voltaDeepak Nibade2018-09-20
| | | | | | | | | | | | | | | | Remove some unused register/field accessors for gv100/gv11b since they are not being accessed anymore on these chips Bug 2173122 Change-Id: Ia4692a72e23024d2ee71a80b08040885af21a9ef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1830312 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix race condition in pmu_rpc_handlerThomas Fleury2018-09-20
| | | | | | | | | | | | | | | | | There was a race condition between pmu_rpc_handler and nvgpu_pmu_rpc_execute. The later could free the buffer before pmu_rpc_handler could access related data. Added explicit field in rpc_payload, so that nvgpu_pmu_rpc_execute can wait until pmu_rpc_handler completes. Bug 2331655 Change-Id: Ic2653524159eff10504b9c2625b5241610b5f5f0 Reviewed-on: https://git-master.nvidia.com/r/1811299 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817582 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Update number of LUT entriesVaikundanathan S2018-09-20
| | | | | | | | | | | | | | CTRL_CLK_LUT_NUM_ENTRIES to 128 And fix build issues that appeared with 128 entries. Bug 2331655 Change-Id: If116bff14be9a1923e075f783fdb9a2e992208b8 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810493 Reviewed-on: https://git-master.nvidia.com/r/1813861 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add GV10x perf eventVaikundanathan S2018-09-20
| | | | | | | | | | | | | | | In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: restrict devfreq during active clk_arb set requestsDebarshi Dutta2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | Restrict access to devfreq when there are active set requests in the clk_arbiter. We make the following changes in the patch. 1) Add a global counter in the struct gk20a named clk_arb_global_nr which is used to track the number of active set requests in the system. 2) Anytime a set request is successfully made by the userspace, clk_arb_global_nr is incremented by 1 and during the completion of request(releasing the corresponding file handle), clk_arb_global_nr is decremented by 1. 3) gk20a_scale_target(invoked by devfreq to set the new frequency based on load) atomically checks clk_arb_global_nr. If the value = 0, the code simply continue or else if its > 0, it quits thus making devfreq requests mutually exclusive with the clk_arbiter. Bug 2061372 Change-Id: I5d19de03e45520f4ff8fccb97b1f1589d04c8ab8 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add igpu support for clk_arbiter.Debarshi Dutta2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch constructs clk_arbiter specific code for gp10b as well as gv11b and does the necessary plumbing in the clk_arbiter code. The changes made are as follows. 1) Constructed clk_arb_gp10b.* files which add support for clk_arb related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb. This doesn't have support for debugfs nor the VFUpdateEvent yet and consequently no support for arb->notifications. 2) Added gpcclk specific variables corresponding to every gpc2clk in a given clk_arb related struct. 3) Linux specific support_clk_freq_controller is assigned true in platform_gp10b.c and platform_gv11b.c files. 4) Incremented the clk_arb_worker.put atomic variable during worker_deinit so as to allow the worker thread to be stopped. 5) Added the flag clk_arb_events_supported as part of struct nvgpu_clk_arb. This flag is used to selectively account for the extra refcounting present in OS specific code i.e. nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is reduced during nvgpu_clk_arb_release_completion_dev. Bug 2061372 Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774281 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: expose linux clock controls via HALddutta2018-09-20
| | | | | | | | | | | | | | | | | | | | Expose the linux specific clock implementations via the HAL interface to allow nvgpu to use the controls globally. This patch does the following. 1) Implement a new ops interface and a corresponding linux specific implementation for allowing nvgpu to iterate through a list of available clock frequencies via nvgpu_linux_clk_get_f_points(). 2) Implement nvgpu_linux_clk_get_range(). Bug 2061372 Change-Id: I7ce9a999dbdcd9fafcc84301af148545f6ca97a9 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774280 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: minor fixes in channel_sync.cddutta2018-09-20
| | | | | | | | | | | | | | | | | | | | This patch comes as a follow up to commit 2517d59be282426eec7a97745b76d745ff36c388 containing minor fixes i.e. changing type of 'pos' to u32 instead of int and renaming syncpt_get_id to channel_sync_syncpt_get_id Jira NVGPU-1086 Change-Id: I8bd9271c20d88ff5f68ccfc48a0b533844bbcaaa Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1829832 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE APIAnup Mahindre2018-09-19
| | | | | | | | | | | | Remove the API as it has no use cases. Bug 200445906 Change-Id: Ia2803bd05d78853963011a67091b34ba5bdb3732 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817629 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: common: MISRA 10.1 boolean fixesAmulya2018-09-19
| | | | | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in gpu/nvgpu/common. JIRA NVGPU-646 Change-Id: I9773d863b715f83ae1772b75d5373f77244bc8ca Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807132 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use single lock for gpu power on-offNitin Kumbhar2018-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | Using two separate locks (poweron_lock and poweroff_lock) allows concurrent gpu power-on and power-off. This shall not happen as driver won't be able to maintain correct gpu state. Use a single power_lock to manage gpu power state. This lock will be used to manage gpu power state from multiple triggers like gpu idle, gpu gc-off, etc. JIRA NVGPU-1100 Change-Id: Ia9b4aeda024a5844ae9f182d453cd6341876680a Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827812 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel_sync_gk20a.* to common directoryDebarshi Dutta2018-09-18
| | | | | | | | | | | | | | | | | | | | 1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they donot program any hardware registers. Also as an add-on rename channel_sync_gk20a.* to channel_sync.* and update the headers in required files. 2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also, corresponding syncpt and semaphore versions of the struct alongwith related methods are renamed by removing "gk20a" from their names and adding "nvgpu". 3) Add misra-c cleanups Jira NVGPU-1086 Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812594 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>ddutta2018-09-14
| | | | | | | | | | | | | | | | | | | | Update the include location of gk20a.h to include/nvgpu/gk20a.h in the following directories. nvgpu/gm20b/ nvgpu/gp10b/ nvgpu/gv11b/ Jira NVGPU-597 Change-Id: Ie38d4a72bb65c41bd30058350509bfa7e87bb64e Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822789 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: dump falcon stats for fecs watchdogSeema Khowala2018-09-14
| | | | | | | | | | | | | | | After fecs watchdog gets triggered, system will not do anything useful as it cannot context switch. Dumping falcon stats will help debug the issue since s/w is not triggering recovery. Bug 2113657 Change-Id: I03ccd5ad7c03daac0581775dc615174cc0e77328 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812720 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FBPA interrupt HAL to MCTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | FBPA interrupt is reported via a register in MC. Move the HAL dealing with that interrupt to MC. JIRA NVGPU-954 Change-Id: Ic2b8439e82788f851536bcbb5cba6580f4d5ee7e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813520 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move MC HAL to commonTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | | | | | | | | Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gsp accessors for GV100Deepak Nibade2018-09-12
| | | | | | | | | | | | | Change-Id: I0b0992e2eda98209ed3d7277a69a7fcf1d01f083 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816025 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (pd_cache.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Fixes for all the pd_cache functions that use '__' prefixes. This was trivial: the '__' prefix was simply deleted. JIRA NVGPU-1029 Change-Id: Ia91dabe3ef97fb17a2a85105935fb3a72d7c2c5e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813643 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (nvgpu_mem.c, mm.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Handle the 21.2 fixes for nvgpu_mem.c and mm.c; this deletes the '__' prefixes and slightly renames the __nvgpu_aperture_mask() function since there's a coherent version and a general version. Change-Id: Iee871ad90db3f2622f9099bd9992eb994e0fbf34 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813623 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (public allocator APIs)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. This fixes places in the public allocator APIs. This consists of the various init routines which are used to create an allocator and the debug macro used within the allocator code. The buddy allocator was handled by collapsing the internal '__' prepended version with the non-prefixed version. The only required change was in the page_allocator code which now had to pass in a NULL vm pointer (since the VM is not needed for managing VIDMEM). JIRA NVGPU-1029 Change-Id: I484a144e61789bf594c525c1ca307b96d120830f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813578 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gk20a.h to include/nvgpu/gk20a.hddutta2018-09-12
| | | | | | | | | | | | | | | | | | | Move the contents of the gk20a/gk20a.h to <nvgpu/gk20a.h>. In order to enable a smooth transition, include <nvgpu/gk20a.h> in the current file (i.e. gk20a/gk20a.h). Jira NVGPU-597 Change-Id: I998da0e7688a5827e2974e88ab8ad6849083aa4a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813140 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 15.6 violationssmadhavan2018-09-12
| | | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: I8046a09fa7ffc74c3d737ba57132a0a9ae2ff195 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797699 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix some MISRA 10.3 violationsPhilip Elcan2018-09-10
| | | | | | | | | | | | | | | | Fix MISRA 10.3 violations in mclk_gp106.c. Cleanup cases where values were being assigned to narrower types. Changes in mclk_gp106.c required updates to other files to resolve errors and prevent introducing new violations. JIRA NVGPU-647 Change-Id: Ifdb03ad41d9dbf05dbcf79494ae8565fff6ee083 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming of debug page to FBTerje Bergstrom2018-09-10
| | | | | | | | | | | | | | | Debug page was allocated and programmed to HUB MMU in GR code. This introduces a dependency from GR to FB and is anyway the wrong place. Move the code to allocate memory to generic MM code, and the code to program the addresses to FB. Change-Id: Ib6d3c96efde6794cf5e8cd4c908525c85b57c233 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801423 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu:ps35: Clock domain changesVaikundanathan S2018-09-10
| | | | | | | | | | | | | | | | 1. PMU interface changes 2. Split PS3.0 and PS3.5 into two dev init functions. 3. Split construct and pmu_data_init to two funcitons. 4. Fixing GV100 impact on PS3.5 changes Change-Id: I46ba80325d4a249918edbe4cf868ddf47c778aa1 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1777739 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: include: MISRA Rule 21.2 header guard fixessmadhavan2018-09-10
| | | | | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in the include directory by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H'. JIRA NVGPU-1028 Change-Id: I14e3558c80511314e32ef79c2b609a9fd9cf0a44 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813123 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move fecs trace debugfs to linuxNitin Kumbhar2018-09-09
| | | | | | | | | | | | | | | | | | Add fecs trace debugfs initialization as an os op. The debugfs nodes are set up for gpu versions which call gk20a_fecs_trace_init(). JIRA NVGPU-602 Change-Id: I606ec31acbf04f633500be4c342db32f3f537794 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812449 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix several issues with the buddy allocatorAlex Waterman2018-09-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issues are: 1. Non-fixed allocs must take into account explicit PTE size requests. Previously the PTE size was determines from the allocation size which was incorect. To do this, the PTE size is now plumbed through all GPU VA allocations. This is what the new alloc_pte() op does. 2. Fix buddy PTE size assignment. This changes a '<=' into a '<' in the buddy allocation logic. Effectively this is now leaving the PTE size for buddy blocks equal to the PDE block size as 'ANY'. This prevents a buddy block of PDE size which has yet to be allocated from having a specific PDE size. Without this its possible to do a fixed alloc that fails unexpectedly due to mismatching PDE sizes. Consider two PDE block sized fixed allocs that are contained in one buddy twice the size of a PDE block. Let's call these fixed allocs S and B (small and big). Let's assume that two fixed allocs are done, each targeting S and B, in that order. With the current logic the first alloc, when we create the two buddies S and B, causes both S and B to have a PTE size of SMALL. Now when the second alloc happens we attempt to find a buddy B with a PTE size of either BIG or ANY. But we cannot becasue B already has size SMALL. This casues us to appear like we have a conflicting fixed alloc despite this not being the case. 3. Misc cleanups & bug fixes: - Clean up some MISRA issues - Delete an extraneous unlock that could have caused a deadlock. Bug 200105199 Change-Id: Ib5447ec6705a5a289ac0cf3d5e90c79b5d67582d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768582 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: changing page_idx from int to u64Sai Nikhil2018-09-07
| | | | | | | | | | | | | | | | | | | | | page_idx is an element of the struct nvgpu_semaphore_pool, defined in include/nvgpu/semaphore.h file. page_idx can not be negative so changing it from int to u64 and its related changes in various files. This also fixes MISRA 10.4 violations in these files. Jira NVGPU-992 Change-Id: Ie9696dab7da9e139bc31563783b422c84144f18b Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801632 Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix nvgpu_sim_esc_readl MISRA 17.7 violationsNicolas Benech2018-09-06
| | | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_sim_esc_readl by changing its return to void and printing an error message instead. JIRA NVGPU-677 Change-Id: I949bea253dafc316c7dfbf870eb1225b6fc5b9c3 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812887 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support allocating CBC in vidmemDeepak Nibade2018-09-06
| | | | | | | | | | | | | | | | Update nvgpu_ltc_alloc_cbc() API to accept a flag for vidmem allocation and allocate CBC memory into vidmem if flag is set Bug 2180284 Jira NVGPUT-12 Change-Id: Ia6b9bb670c9fab6b5787de15526fcc753d702a73 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805468 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add BIT8() and BIT16() macrosAmulya2018-09-06
| | | | | | | | | | | | | | | Added BIT8() and BIT16() macros to bit-shift u8 and u16 respectively. Change-Id: I5ca43165b0dcf3702a49bc5f5b120ad7a63b39a8 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813039 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel header to commonKonsta Holtta2018-09-05
| | | | | | | | | | | | | channel_gk20a is clear from chip specifics and from most dependencies, so move it under the common directory. Jira NVGPU-967 Change-Id: I41f2160b96d4ec84064288ecc22bb360e82352df Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810578 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: common: MISRA 10.1 boolean fixesAmulya2018-09-05
| | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in gpu/nvgpu/common. JIRA NVGPU-646 Change-Id: I91baa5cf1d38081161336bde5fbc06661b741273 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807133 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix mutex MISRA 17.7 violationsNicolas Benech2018-09-05
| | | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_mutex_init and improves related error handling. JIRA NVGPU-677 Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805598 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move common DMA code to common/mmAlex Waterman2018-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | This migrates the common DMA code (os agnostic) to the common directory. This new unit will be the common DMA allocator that lets users allocate SYSMEM, VIDMEM, or either. Other units will be responsible for actually handling the mechanics of allocating VIDMEM or SYSMEM. Also update the names of the DMA related files so that tmake doesn't complain about duplicate C file names. To do this call the common DMA file dma.c and prepend the OS to the other DMA files. So now we have: common/mm/dma.c os/posix/posix-dma.c os/linux/linux-dma.c JIRA NVGPU-990 Change-Id: I22d2d41803ad89be7d9c28f87864ce4fedf10836 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1799807 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gp106 clk debugfs to linuxNitin Kumbhar2018-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | Move linux dependencies and CONFIG_DEBUG_FS to linux specific code from common driver for gp106 clk debugfs. There is no code change in functions moved from gp106/clk_gp106.c. It uses nvgpu_os_linux_ops to add gp106 specific clk debugfs ops. The linux specific part of nvgpu driver uses this op to initialize gp106 clk debugfs. As gv100 also uses gp106 clk debugfs ops, set up os ops for gv100. JIRA NVGPU-603 Change-Id: Ib55ef051b13366e5907e1d05376bb18bf42c8653 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797904 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix __nvgpu_set_enabled MISRA 17.7 violationsNicolas Benech2018-09-04
| | | | | | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch changes the signature of __nvgpu_set_enabled to return void since the signature never implied it should return the final value of the flag. No code within NVGPU was using the return value anyway. JIRA NVGPU-677 Change-Id: Ib5d44d9a6a604a68c1f94b9475e9596eb14d1032 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810717 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmuif: Fix MISRA Rule 21.2 violationsSrirangan2018-09-04
| | | | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards in pmuif by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H'. JIRA NVGPU-1028 Change-Id: I19471ed8d8f7b278f497df74f760cdb1edc43ed0 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808133 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: gv11b: enable RMW for gpu atomics"Richard Zhao2018-09-04
| | | | | | | | | | | | | | | | The original change caused cuda atomic perf regression. Bug 2310618 This reverts commit 10c3d4447d4206302f5d51695bf1f193255dd889. Change-Id: Iea5391a89fdfadfb9a79cda57e71f1c9e87ca882 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1793880 (cherry picked from commit d0e51ddcb8139de70916335f124a80b8b588308b) Reviewed-on: https://git-master.nvidia.com/r/1804945 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gp106 specific clk_arbiter code into HALDebarshi Dutta2018-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, clock arbiter code is extensively using dgpu specific implementation. This patch restructures the clk_arbiter code and moves gp106 specific code into HAL. Following changes are made in this patch 1) clk_domain_get_f_points is now invoked via HAL for gp106 i.e. g->ops.clk.clk_domain_get_f_points. 2) moved nvgpu_clk_arb_change_vf_point and other related static functions to clk_arb_gp106.c. 3) Instead of only checking if get_arbiter_clk_domain is empty, a check for support_clk_freq_controller is also added. This is to enable the clk_arbiter based on support from both the OS and the chips. Bug 2061372 Change-Id: I65b0a4e02145a86fbbfb420ed591b1fa3c86f6dc Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774279 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove use of NVGPU_CTXSW_FILTER_ISSETVaibhav Kachore2018-08-31
| | | | | | | | | | | | | | | | | - Remove the usage of NVGPU_CTXSW_FILTER_ISSET splattered across nvgpu, and replace with a MACRO defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the fecs trace path. - Remove "uapi/linux/nvgpu.h" from common code. EVLR-3078 Change-Id: I60b0e1627576a4b255671d58530d8c773ea6154c Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803210 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: convert linux nvgpu ctxsw tagsVaibhav Kachore2018-08-31
| | | | | | | | | | | | | | Convert linux nvgpu ctxsw tags type of the form of NVGPU_CTXSW_TAG_* into common nvgpu ctxsw tags type of the form of NVGPU_GPU_CTXSW_TAG_* EVLR-3078 Change-Id: I337487722c103c05003457f74ad6e05bf3bd38fc Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove use of nvgpu_ctxsw_trace_entryVaibhav Kachore2018-08-31
| | | | | | | | | | | | | | | | | | - Remove the usage of nvgpu_ctxsw_trace_entry splattered across nvgpu, and replace with a struct defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the fecs trace path. - Remove "asm/barrier.h" as "nvgpu/barrier.h" is already included. EVLR-3078 Change-Id: Iabfb105b891b0078ed326a8047ef14ebe1888cf2 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803208 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix channel include guardsKonsta Holtta2018-08-31
| | | | | | | | | | | | | | | | | | The common channel header was missing include guards, so add them. Also rename the Linux channel header guard that was in conflict. Jira NVGPU-967 Change-Id: If782407ef1497202196a362893ef9c1b2330977a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807372 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Sync kernel headers with generator toolTerje Bergstrom2018-08-30
| | | | | | | | | | | | | | | | | | HW headers in nvgpu have gotten a bit out of date. Regenerate headers and add the following registers: * Add PTIMER timeout registers to all chips * Add PD, SCC, SSYNC and MME interrupt registers to all chips * Add HWW ESR INFO register to all chips Change-Id: I34e09371083ac1568666b0cd487a106fad56aa12 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807709 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove lists of kindsTerje Bergstrom2018-08-30
| | | | | | | | | | | Management of kinds was moved to user space. Remove the lists of kind types in kernel. Change-Id: I9872626850d19132715fb8903a0bb13a0d319654 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807708 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HALDebarshi Dutta2018-08-29
| | | | | | | | | | | | | | | | | | | | In nvgpu repository, we have multiple accesses to methods in pmu_gk20a.h which have register accesses. Instead of directly invoking these methods, these are now called via HALs. Some common methods such as pmu_wait_message_cond which donot have any register accesses are moved to pmu_ipc.c and the method declarations are moved to pmu.h. Also, changed gm20b_pmu_dbg to nvgpu_dbg_pmu all across the code base. This would remove all indirect dependencies via gk20a.h into pmu_gk20a.h. As a result pmu_gk20a.h is now removed from gk20a.h JIRA-597 Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804283 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: fix MISRA Rule 10.4Sai Nikhil2018-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fix violations where an arithmetic operation is performed on signed and unsigned int types. In balloc_get_order_list() the argument "int order" has been changed to a u64 because all callers of this function pass a u64 argument. JIRA NVGPU-992 Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1784419 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 10.1-Using boolean as a bitAmulya2018-08-28
| | | | | | | | | | | | | | | | | | Fix violations where a boolean is used as an operand in bit-shift operations and is interpreted as a numerical value. JIRA NVGPU-649 Change-Id: I4494c3b69d0e53319331b47d0a4de0b3de279f4f Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1799322 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-06-30 20:39:10 -0400